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FreeDATA
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adjusted timing

pull/704/head
dj2ls 2024-03-31 19:07:15 +02:00
parent beb9589880
commit 20a76a80bb
1 changed files with 1 additions and 1 deletions
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2
modem/arq_session_iss.py
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@ -26,7 +26,7 @@ class ARQSessionISS(arq_session.ARQSession):
# DJ2LS: 3.5 seconds is working well WITHOUT a channel busy detection delay
TIMEOUT_CHANNEL_BUSY = 0
TIMEOUT_CONNECT_ACK = 3.5 + TIMEOUT_CHANNEL_BUSY
TIMEOUT_TRANSFER = 1 + TIMEOUT_CHANNEL_BUSY
TIMEOUT_TRANSFER = 1.5 + TIMEOUT_CHANNEL_BUSY
TIMEOUT_STOP_ACK = 3.5 + TIMEOUT_CHANNEL_BUSY
STATE_TRANSITION = {