mirror of https://github.com/drowe67/codec2.git
287 lines
8.7 KiB
C
287 lines
8.7 KiB
C
/*---------------------------------------------------------------------------*\
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FILE........: stm32f4_adc.c
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AUTHOR......: David Rowe
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DATE CREATED: 4 June 2013
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Two channel ADC driver module for STM32F4. Pin PA1 connects to ADC1, pin
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PA2 connects to ADC2.
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\*---------------------------------------------------------------------------*/
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/*
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Copyright (C) 2013 David Rowe
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All rights reserved.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License version 2.1, as
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published by the Free Software Foundation. This program is
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distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <assert.h>
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#include <stdlib.h>
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#include <string.h>
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#include "stm32f4xx_adc.h"
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#include "stm32f4xx_gpio.h"
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#include "stm32f4xx_rcc.h"
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#include "codec2_fifo.h"
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#include "stm32f4_adc.h"
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#include "debugblinky.h"
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struct FIFO *adc1_fifo;
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struct FIFO *adc2_fifo;
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unsigned short adc_buf[ADC_BUF_SZ];
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int adc_overflow1, adc_overflow2;
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int half,full;
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#define ADCx_DR_ADDRESS ((uint32_t)0x4001204C)
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#define DMA_CHANNELx DMA_Channel_0
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#define DMA_STREAMx DMA2_Stream0
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#define ADCx ADC1
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void adc_configure();
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static void tim2_config(int fs_divisor);
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// You can optionally supply your own storage for the FIFO buffers bu1 and buf2,
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// or set them to NULL and they will be malloc-ed for you
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void adc_open(int fs_divisor, int fifo_sz, short *buf1, short *buf2) {
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if (buf1 == NULL) {
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adc1_fifo = codec2_fifo_create(fifo_sz);
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adc2_fifo = codec2_fifo_create(fifo_sz);
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} else {
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adc1_fifo = codec2_fifo_create_buf(fifo_sz, buf1);
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adc2_fifo = codec2_fifo_create_buf(fifo_sz, buf2);
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}
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tim2_config(fs_divisor);
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adc_configure();
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init_debug_blinky();
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}
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/* n signed 16 bit samples in buf[] if return != -1 */
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int adc1_read(short buf[], int n) {
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return codec2_fifo_read(adc1_fifo, buf, n);
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}
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/* n signed 16 bit samples in buf[] if return != -1 */
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int adc2_read(short buf[], int n) {
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return codec2_fifo_read(adc2_fifo, buf, n);
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}
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/* Returns number of signed 16 bit samples in the FIFO currently */
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int adc1_samps(){
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return codec2_fifo_used(adc1_fifo);
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}
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/* Returns number of signed 16 bit samples in the FIFO currently */
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int adc2_samps(){
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return codec2_fifo_used(adc2_fifo);
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}
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static void tim2_config(int fs_divisor)
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{
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TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
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/* TIM2 Periph clock enable */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
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/* --------------------------------------------------------
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TIM2 input clock (TIM2CLK) is set to 2 * APB1 clock (PCLK1), since
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APB1 prescaler is different from 1 (see system_stm32f4xx.c and Fig
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13 clock tree figure in DM0031020.pdf).
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Sample rate Fs = 2*PCLK1/TIM_ClockDivision
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= (HCLK/2)/TIM_ClockDivision
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----------------------------------------------------------- */
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/* Time base configuration */
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TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
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TIM_TimeBaseStructure.TIM_Period = fs_divisor - 1;
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TIM_TimeBaseStructure.TIM_Prescaler = 0;
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TIM_TimeBaseStructure.TIM_ClockDivision = 0;
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TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
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TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
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/* TIM2 TRGO selection */
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TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_Update);
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/* TIM2 enable counter */
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TIM_Cmd(TIM2, ENABLE);
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}
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void adc_configure(){
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ADC_InitTypeDef ADC_init_structure;
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GPIO_InitTypeDef GPIO_initStructre;
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DMA_InitTypeDef DMA_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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// Clock configuration
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1,ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1ENR_GPIOAEN,ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
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// Analog pin configuration ADC1->PA1, ADC2->PA2
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GPIO_initStructre.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2;
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GPIO_initStructre.GPIO_Mode = GPIO_Mode_AN;
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GPIO_initStructre.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(GPIOA,&GPIO_initStructre);
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// ADC structure configuration
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ADC_DeInit();
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ADC_init_structure.ADC_DataAlign = ADC_DataAlign_Left;
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ADC_init_structure.ADC_Resolution = ADC_Resolution_12b;
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ADC_init_structure.ADC_ContinuousConvMode = DISABLE;
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ADC_init_structure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T2_TRGO;
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ADC_init_structure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_Rising;
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ADC_init_structure.ADC_NbrOfConversion = 2;
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ADC_init_structure.ADC_ScanConvMode = ENABLE;
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ADC_Init(ADCx,&ADC_init_structure);
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// Select the channel to be read from
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ADC_RegularChannelConfig(ADCx,ADC_Channel_1,1,ADC_SampleTime_144Cycles);
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ADC_RegularChannelConfig(ADCx,ADC_Channel_2,2,ADC_SampleTime_144Cycles);
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//ADC_VBATCmd(ENABLE);
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/* DMA configuration **************************************/
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DMA_DeInit(DMA_STREAMx);
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DMA_InitStructure.DMA_Channel = DMA_CHANNELx;
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)ADCx_DR_ADDRESS;
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DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)adc_buf;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
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DMA_InitStructure.DMA_BufferSize = ADC_BUF_SZ;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
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DMA_InitStructure.DMA_Priority = DMA_Priority_High;
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DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
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DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;
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DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
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DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
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DMA_Init(DMA_STREAMx, &DMA_InitStructure);
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/* Enable DMA request after last transfer (Single-ADC mode) */
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ADC_DMARequestAfterLastTransferCmd(ADCx, ENABLE);
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/* Enable ADC1 DMA */
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ADC_DMACmd(ADCx, ENABLE);
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/* DMA2_Stream0 enable */
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DMA_Cmd(DMA_STREAMx, ENABLE);
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/* Enable DMA Half & Complete interrupts */
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DMA_ITConfig(DMA2_Stream0, DMA_IT_TC | DMA_IT_HT, ENABLE);
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/* Enable the DMA Stream IRQ Channel */
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NVIC_InitStructure.NVIC_IRQChannel = DMA2_Stream0_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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// Enable and start ADC conversion
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ADC_Cmd(ADC1,ENABLE);
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ADC_SoftwareStartConv(ADC1);
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}
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/*
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This function handles DMA Stream interrupt request.
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*/
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void DMA2_Stream0_IRQHandler(void) {
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int i, j, sam;
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short signed_buf1[ADC_BUF_SZ/2];
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short signed_buf2[ADC_BUF_SZ/2];
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GPIOE->ODR |= (1 << 0);
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/* Half transfer interrupt */
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if(DMA_GetITStatus(DMA2_Stream0, DMA_IT_HTIF0) != RESET) {
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half++;
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/* convert to signed */
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for(i=0, j=0; i<ADC_BUF_SZ/2; i+=2,j++) {
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sam = (int)adc_buf[i] - 32768;
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signed_buf1[j] = sam;
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sam = (int)adc_buf[i+1] - 32768;
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signed_buf2[j] = sam;
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}
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/* write first half to fifo */
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if (codec2_fifo_write(adc1_fifo, signed_buf1, ADC_BUF_SZ/4) == -1) {
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adc_overflow1++;
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}
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if (codec2_fifo_write(adc2_fifo, signed_buf2, ADC_BUF_SZ/4) == -1) {
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adc_overflow2++;
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}
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/* Clear DMA Stream Transfer Complete interrupt pending bit */
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DMA_ClearITPendingBit(DMA2_Stream0, DMA_IT_HTIF0);
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}
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/* Transfer complete interrupt */
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if(DMA_GetITStatus(DMA2_Stream0, DMA_IT_TCIF0) != RESET) {
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full++;
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/* convert to signed */
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for(i=0, j=0; i<ADC_BUF_SZ/2; i+=2,j++) {
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sam = (int)adc_buf[ADC_BUF_SZ/2 + i] - 32768;
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signed_buf1[j] = sam;
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sam = (int)adc_buf[ADC_BUF_SZ/2 + i+1] - 32768;
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signed_buf2[j] = sam;
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}
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/* write second half to fifo */
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if (codec2_fifo_write(adc1_fifo, signed_buf1, ADC_BUF_SZ/4) == -1) {
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adc_overflow1++;
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}
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if (codec2_fifo_write(adc2_fifo, signed_buf2, ADC_BUF_SZ/4) == -1) {
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adc_overflow2++;
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}
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/* Clear DMA Stream Transfer Complete interrupt pending bit */
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DMA_ClearITPendingBit(DMA2_Stream0, DMA_IT_TCIF0);
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}
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GPIOE->ODR &= ~(1 << 0);
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}
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