mirror of https://github.com/drowe67/codec2.git
428 lines
14 KiB
C
428 lines
14 KiB
C
/*---------------------------------------------------------------------------*\
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FILE........: stm32f4_dac.c
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AUTHOR......: David Rowe
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DATE CREATED: 1 June 2013
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DAC driver module for STM32F4. DAC1 is connected to pin PA4, DAC2
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is connected to pin PA5.
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\*---------------------------------------------------------------------------*/
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/*
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Copyright (C) 2013 David Rowe
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All rights reserved.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License version 2.1, as
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published by the Free Software Foundation. This program is
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distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <assert.h>
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#include <stdlib.h>
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#include <string.h>
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#include "stm32f4xx.h"
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#include "codec2_fifo.h"
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#include "stm32f4_dac.h"
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#include "debugblinky.h"
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/* write to these registers for 12 bit left aligned data, as per data sheet
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make sure 4 least sig bits set to 0 */
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#define DAC_DHR12R1_ADDRESS 0x40007408
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#define DAC_DHR12R2_ADDRESS 0x40007414
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#define DAC_MAX 4096 /* maximum amplitude */
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/* y=mx+c mapping of samples16 bit shorts to DAC samples. Table: 74
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of data sheet indicates With DAC buffer on, DAC range is limited to
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0x0E0 to 0xF1C at VREF+ = 3.6 V, we have Vref=3.3V which is close.
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*/
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#define M ((3868.0-224.0)/65536.0)
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#define C 2047.0
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static struct FIFO *dac1_fifo;
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static struct FIFO *dac2_fifo;
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static unsigned short dac1_buf[DAC_BUF_SZ];
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static unsigned short dac2_buf[DAC_BUF_SZ];
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static void tim6_config(int fs_divisor);
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static void dac1_config(void);
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static void dac2_config(void);
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int dac_underflow;
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// You can optionally supply your own storage for the FIFO buffers bu1 and buf2,
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// or set them to NULL and they will be malloc-ed for you
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void dac_open(int fs_divisor, int fifo_size, short *buf1, short *buf2) {
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memset(dac1_buf, 32768, sizeof(short)*DAC_BUF_SZ);
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memset(dac2_buf, 32768, sizeof(short)*DAC_BUF_SZ);
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/* Create fifos */
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if ((buf1 == NULL) && (buf2 == NULL)) {
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dac1_fifo = codec2_fifo_create(fifo_size);
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dac2_fifo = codec2_fifo_create(fifo_size);
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} else {
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dac1_fifo = codec2_fifo_create_buf(fifo_size, buf1);
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dac2_fifo = codec2_fifo_create_buf(fifo_size, buf2);
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}
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/* Turn on the clocks we need -----------------------------------------------*/
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/* DMA1 clock enable */
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
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/* GPIOA clock enable (to be used with DAC) */
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
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/* DAC Periph clock enable */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
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/* GPIO Pin configuration DAC1->PA.4, DAC2->PA.5 configuration --------------*/
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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/* Timer and DAC 1 & 2 Configuration ----------------------------------------*/
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tim6_config(fs_divisor);
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dac1_config();
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dac2_config();
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init_debug_blinky();
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}
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/* Call these functions to send samples to the DACs. For your
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convenience they accept signed 16 bit samples. You can optionally
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limit how much data to store in the fifo */
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int dac1_write(short buf[], int n, int limit) {
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/* artificial limit < FIFO size */
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if (limit) {
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if ((codec2_fifo_used(dac1_fifo) + n) <= limit)
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return codec2_fifo_write(dac1_fifo, buf, n);
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else
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return -1;
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}
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/* normal operation */
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return codec2_fifo_write(dac1_fifo, buf, n);
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}
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int dac2_write(short buf[], int n, int limit) {
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/* artificial limit < FIFO size */
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if (limit) {
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if ((codec2_fifo_used(dac2_fifo) + n) <= limit)
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return codec2_fifo_write(dac2_fifo, buf, n);
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else
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return -1;
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}
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/* normal operation */
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return codec2_fifo_write(dac2_fifo, buf, n);
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}
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int dac1_free() {
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return codec2_fifo_free(dac1_fifo);
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}
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int dac2_free() {
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return codec2_fifo_free(dac2_fifo);
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}
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static void tim6_config(int fs_divisor)
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{
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TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
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/* TIM6 Periph clock enable */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE);
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/* --------------------------------------------------------
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TIM6 input clock (TIM6CLK) is set to 2 * APB1 clock (PCLK1), since
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APB1 prescaler is different from 1 (see system_stm32f4xx.c and Fig
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13 clock tree figure in DM0031020.pdf).
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Sample rate Fs = 2*PCLK1/TIM_ClockDivision
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= (HCLK/2)/TIM_ClockDivision
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----------------------------------------------------------- */
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/* Time base configuration */
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TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
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TIM_TimeBaseStructure.TIM_Period = fs_divisor - 1;
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TIM_TimeBaseStructure.TIM_Prescaler = 0;
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TIM_TimeBaseStructure.TIM_ClockDivision = 0;
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TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
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TIM_TimeBaseInit(TIM6, &TIM_TimeBaseStructure);
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/* TIM6 TRGO selection */
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TIM_SelectOutputTrigger(TIM6, TIM_TRGOSource_Update);
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/* TIM6 enable counter */
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TIM_Cmd(TIM6, ENABLE);
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}
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static void dac1_config(void)
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{
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DAC_InitTypeDef DAC_InitStructure;
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DMA_InitTypeDef DMA_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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/* DAC channel 1 Configuration */
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/*
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This line fixed a bug that cost me 5 days, bad wave amplitude
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value, and some STM32F4 periph library bugs caused triangle wave
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generation to be enable resulting in a low level tone on the
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SM1000, that we thought was caused by analog issues like layour
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or power supply biasing
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*/
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DAC_StructInit(&DAC_InitStructure);
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DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO;
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DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
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DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
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DAC_Init(DAC_Channel_1, &DAC_InitStructure);
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/* DMA1_Stream5 channel7 configuration **************************************/
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/* Table 35 page 219 of the monster data sheet */
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DMA_DeInit(DMA1_Stream5);
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DMA_InitStructure.DMA_Channel = DMA_Channel_7;
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DAC_DHR12R1_ADDRESS;
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DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)dac1_buf;
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DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
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DMA_InitStructure.DMA_BufferSize = DAC_BUF_SZ;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
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DMA_InitStructure.DMA_Priority = DMA_Priority_High;
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DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
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DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;
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DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
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DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
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DMA_Init(DMA1_Stream5, &DMA_InitStructure);
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/* Enable DMA Half & Complete interrupts */
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DMA_ITConfig(DMA1_Stream5, DMA_IT_TC | DMA_IT_HT, ENABLE);
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/* Enable the DMA Stream IRQ Channel */
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NVIC_InitStructure.NVIC_IRQChannel = DMA1_Stream5_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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/* Enable DMA1_Stream5 */
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DMA_Cmd(DMA1_Stream5, ENABLE);
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/* Enable DAC Channel 1 */
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DAC_Cmd(DAC_Channel_1, ENABLE);
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/* Enable DMA for DAC Channel 1 */
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DAC_DMACmd(DAC_Channel_1, ENABLE);
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}
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static void dac2_config(void)
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{
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DAC_InitTypeDef DAC_InitStructure;
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DMA_InitTypeDef DMA_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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/* DAC channel 2 Configuration (see notes in dac1_config() above) */
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DAC_StructInit(&DAC_InitStructure);
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DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO;
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DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
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DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
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DAC_Init(DAC_Channel_2, &DAC_InitStructure);
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/* DMA1_Stream6 channel7 configuration **************************************/
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DMA_DeInit(DMA1_Stream6);
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DMA_InitStructure.DMA_Channel = DMA_Channel_7;
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DAC_DHR12R2_ADDRESS;
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DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)dac2_buf;
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DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
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DMA_InitStructure.DMA_BufferSize = DAC_BUF_SZ;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
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DMA_InitStructure.DMA_Priority = DMA_Priority_High;
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DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
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DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;
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DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
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DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
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DMA_Init(DMA1_Stream6, &DMA_InitStructure);
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/* Enable DMA Half & Complete interrupts */
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DMA_ITConfig(DMA1_Stream6, DMA_IT_TC | DMA_IT_HT, ENABLE);
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/* Enable the DMA Stream IRQ Channel */
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NVIC_InitStructure.NVIC_IRQChannel = DMA1_Stream6_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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/* Enable DMA1_Stream6 */
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DMA_Cmd(DMA1_Stream6, ENABLE);
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/* Enable DAC Channel 2 */
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DAC_Cmd(DAC_Channel_2, ENABLE);
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/* Enable DMA for DAC Channel 2 */
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DAC_DMACmd(DAC_Channel_2, ENABLE);
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}
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/******************************************************************************/
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/* STM32F4xx Peripherals Interrupt Handlers */
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/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
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/* available peripheral interrupt handler's name please refer to the startup */
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/* file (startup_stm32f40xx.s/startup_stm32f427x.s). */
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/******************************************************************************/
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/*
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This function handles DMA1 Stream 5 interrupt request for DAC1.
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*/
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void DMA1_Stream5_IRQHandler(void) {
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int i, j, sam;
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short signed_buf[DAC_BUF_SZ/2];
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GPIOE->ODR |= (1 << 1);
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/* Transfer half empty interrupt - refill first half */
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if(DMA_GetITStatus(DMA1_Stream5, DMA_IT_HTIF5) != RESET) {
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/* fill first half from fifo */
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if (codec2_fifo_read(dac1_fifo, signed_buf, DAC_BUF_SZ/2) == -1) {
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memset(signed_buf, 0, sizeof(short)*DAC_BUF_SZ/2);
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dac_underflow++;
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}
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/* convert to unsigned */
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for(i=0; i<DAC_BUF_SZ/2; i++) {
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sam = (int)(M*(float)signed_buf[i] + C);
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dac1_buf[i] = (unsigned short)sam;
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}
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/* Clear DMA Stream Transfer Complete interrupt pending bit */
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DMA_ClearITPendingBit(DMA1_Stream5, DMA_IT_HTIF5);
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}
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/* Transfer complete interrupt - refill 2nd half */
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if(DMA_GetITStatus(DMA1_Stream5, DMA_IT_TCIF5) != RESET) {
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/* fill second half from fifo */
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if (codec2_fifo_read(dac1_fifo, signed_buf, DAC_BUF_SZ/2) == -1) {
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memset(signed_buf, 0, sizeof(short)*DAC_BUF_SZ/2);
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dac_underflow++;
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}
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/* convert to unsigned */
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for(i=0, j=DAC_BUF_SZ/2; i<DAC_BUF_SZ/2; i++,j++) {
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sam = (int)(M*(float)signed_buf[i] + C);
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dac1_buf[j] = (unsigned short)sam;
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}
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/* Clear DMA Stream Transfer Complete interrupt pending bit */
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DMA_ClearITPendingBit(DMA1_Stream5, DMA_IT_TCIF5);
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}
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GPIOE->ODR &= ~(1 << 1);
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}
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/*
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This function handles DMA1 Stream 6 interrupt request for DAC2.
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*/
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void DMA1_Stream6_IRQHandler(void) {
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int i, j, sam;
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short signed_buf[DAC_BUF_SZ/2];
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GPIOE->ODR |= (1 << 2);
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/* Transfer half empty interrupt - refill first half */
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if(DMA_GetITStatus(DMA1_Stream6, DMA_IT_HTIF6) != RESET) {
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/* fill first half from fifo */
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if (codec2_fifo_read(dac2_fifo, signed_buf, DAC_BUF_SZ/2) == -1) {
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memset(signed_buf, 0, sizeof(short)*DAC_BUF_SZ/2);
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dac_underflow++;
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}
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/* convert to unsigned */
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for(i=0; i<DAC_BUF_SZ/2; i++) {
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sam = (int)(M*(float)signed_buf[i] + C);
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dac2_buf[i] = (unsigned short)sam;
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}
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/* Clear DMA Stream Transfer Complete interrupt pending bit */
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DMA_ClearITPendingBit(DMA1_Stream6, DMA_IT_HTIF6);
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}
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/* Transfer complete interrupt - refill 2nd half */
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if(DMA_GetITStatus(DMA1_Stream6, DMA_IT_TCIF6) != RESET) {
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/* fill second half from fifo */
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if (codec2_fifo_read(dac2_fifo, signed_buf, DAC_BUF_SZ/2) == -1) {
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memset(signed_buf, 0, sizeof(short)*DAC_BUF_SZ/2);
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dac_underflow++;
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}
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/* convert to unsigned */
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for(i=0, j=DAC_BUF_SZ/2; i<DAC_BUF_SZ/2; i++,j++) {
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sam = (int)(M*(float)signed_buf[i] + C);
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dac2_buf[j] = (unsigned short)sam;
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}
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/* Clear DMA Stream Transfer Complete interrupt pending bit */
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DMA_ClearITPendingBit(DMA1_Stream6, DMA_IT_TCIF6);
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}
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GPIOE->ODR &= ~(1 << 2);
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}
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