mirror of https://github.com/drowe67/librtlsdr.git
rtl_ir: merge some init code from Linux dvb-usb-v2 driver
9256d5a308/drivers/media/usb/dvb-usb-v2/rtl28xxu.c
rxseger
parent
024f3c57a2
commit
4b4942fb05
341
src/rtl_ir.c
341
src/rtl_ir.c
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@ -1,5 +1,8 @@
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/*
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* rtl-sdr, turns your Realtek RTL2832 based DVB dongle into a SDR receiver
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* Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
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* Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
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* Copyright (C) 2012 Thomas Mair <thomas.mair86@googlemail.com>
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* Copyright (C) 2012 by Steve Markgraf <steve@steve-m.de>
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* Copyright (C) 2012 by Hoernchen <la@tfc-server.de>
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* Copyright (C) 2012 by Kyle Keen <keenerd@gmail.com>
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@ -48,19 +51,263 @@
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#include "rtl-sdr.h"
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#include "convenience/convenience.h"
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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// Registers from Linux drivers/media/usb/dvb-usb-v2/rtl28xxu.h TODO: merge into librtlsdr?
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struct rtl28xxu_req {
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uint16_t value;
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uint16_t index;
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uint16_t size;
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uint8_t *data;
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};
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struct rtl28xxu_reg_val {
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uint16_t reg;
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uint8_t val;
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};
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struct rtl28xxu_reg_val_mask {
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uint16_t reg;
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uint8_t val;
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uint8_t mask;
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};
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/*
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* memory map
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*
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* 0x0000 DEMOD : demodulator
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* 0x2000 USB : SIE, USB endpoint, debug, DMA
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* 0x3000 SYS : system
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* 0xfc00 RC : remote controller (not RTL2831U)
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*/
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/*
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* USB registers
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*/
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/* SIE Control Registers */
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#define USB_SYSCTL 0x2000 /* USB system control */
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#define USB_SYSCTL_0 0x2000 /* USB system control */
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#define USB_SYSCTL_1 0x2001 /* USB system control */
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#define USB_SYSCTL_2 0x2002 /* USB system control */
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#define USB_SYSCTL_3 0x2003 /* USB system control */
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#define USB_IRQSTAT 0x2008 /* SIE interrupt status */
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#define USB_IRQEN 0x200C /* SIE interrupt enable */
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#define USB_CTRL 0x2010 /* USB control */
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#define USB_STAT 0x2014 /* USB status */
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#define USB_DEVADDR 0x2018 /* USB device address */
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#define USB_TEST 0x201C /* USB test mode */
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#define USB_FRAME_NUMBER 0x2020 /* frame number */
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#define USB_FIFO_ADDR 0x2028 /* address of SIE FIFO RAM */
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#define USB_FIFO_CMD 0x202A /* SIE FIFO RAM access command */
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#define USB_FIFO_DATA 0x2030 /* SIE FIFO RAM data */
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/* Endpoint Registers */
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#define EP0_SETUPA 0x20F8 /* EP 0 setup packet lower byte */
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#define EP0_SETUPB 0x20FC /* EP 0 setup packet higher byte */
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#define USB_EP0_CFG 0x2104 /* EP 0 configure */
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#define USB_EP0_CTL 0x2108 /* EP 0 control */
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#define USB_EP0_STAT 0x210C /* EP 0 status */
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#define USB_EP0_IRQSTAT 0x2110 /* EP 0 interrupt status */
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#define USB_EP0_IRQEN 0x2114 /* EP 0 interrupt enable */
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#define USB_EP0_MAXPKT 0x2118 /* EP 0 max packet size */
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#define USB_EP0_BC 0x2120 /* EP 0 FIFO byte counter */
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#define USB_EPA_CFG 0x2144 /* EP A configure */
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#define USB_EPA_CFG_0 0x2144 /* EP A configure */
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#define USB_EPA_CFG_1 0x2145 /* EP A configure */
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#define USB_EPA_CFG_2 0x2146 /* EP A configure */
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#define USB_EPA_CFG_3 0x2147 /* EP A configure */
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#define USB_EPA_CTL 0x2148 /* EP A control */
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#define USB_EPA_CTL_0 0x2148 /* EP A control */
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#define USB_EPA_CTL_1 0x2149 /* EP A control */
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#define USB_EPA_CTL_2 0x214A /* EP A control */
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#define USB_EPA_CTL_3 0x214B /* EP A control */
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#define USB_EPA_STAT 0x214C /* EP A status */
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#define USB_EPA_IRQSTAT 0x2150 /* EP A interrupt status */
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#define USB_EPA_IRQEN 0x2154 /* EP A interrupt enable */
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#define USB_EPA_MAXPKT 0x2158 /* EP A max packet size */
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#define USB_EPA_MAXPKT_0 0x2158 /* EP A max packet size */
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#define USB_EPA_MAXPKT_1 0x2159 /* EP A max packet size */
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#define USB_EPA_MAXPKT_2 0x215A /* EP A max packet size */
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#define USB_EPA_MAXPKT_3 0x215B /* EP A max packet size */
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#define USB_EPA_FIFO_CFG 0x2160 /* EP A FIFO configure */
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#define USB_EPA_FIFO_CFG_0 0x2160 /* EP A FIFO configure */
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#define USB_EPA_FIFO_CFG_1 0x2161 /* EP A FIFO configure */
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#define USB_EPA_FIFO_CFG_2 0x2162 /* EP A FIFO configure */
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#define USB_EPA_FIFO_CFG_3 0x2163 /* EP A FIFO configure */
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/* Debug Registers */
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#define USB_PHYTSTDIS 0x2F04 /* PHY test disable */
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#define USB_TOUT_VAL 0x2F08 /* USB time-out time */
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#define USB_VDRCTRL 0x2F10 /* UTMI vendor signal control */
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#define USB_VSTAIN 0x2F14 /* UTMI vendor signal status in */
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#define USB_VLOADM 0x2F18 /* UTMI load vendor signal status in */
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#define USB_VSTAOUT 0x2F1C /* UTMI vendor signal status out */
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#define USB_UTMI_TST 0x2F80 /* UTMI test */
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#define USB_UTMI_STATUS 0x2F84 /* UTMI status */
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#define USB_TSTCTL 0x2F88 /* test control */
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#define USB_TSTCTL2 0x2F8C /* test control 2 */
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#define USB_PID_FORCE 0x2F90 /* force PID */
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#define USB_PKTERR_CNT 0x2F94 /* packet error counter */
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#define USB_RXERR_CNT 0x2F98 /* RX error counter */
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#define USB_MEM_BIST 0x2F9C /* MEM BIST test */
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#define USB_SLBBIST 0x2FA0 /* self-loop-back BIST */
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#define USB_CNTTEST 0x2FA4 /* counter test */
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#define USB_PHYTST 0x2FC0 /* USB PHY test */
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#define USB_DBGIDX 0x2FF0 /* select individual block debug signal */
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#define USB_DBGMUX 0x2FF4 /* debug signal module mux */
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/*
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* SYS registers
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*/
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/* demod control registers */
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#define SYS_SYS0 0x3000 /* include DEMOD_CTL, GPO, GPI, GPOE */
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#define SYS_DEMOD_CTL 0x3000 /* control register for DVB-T demodulator */
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/* GPIO registers */
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#define SYS_GPIO_OUT_VAL 0x3001 /* output value of GPIO */
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#define SYS_GPIO_IN_VAL 0x3002 /* input value of GPIO */
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#define SYS_GPIO_OUT_EN 0x3003 /* output enable of GPIO */
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#define SYS_SYS1 0x3004 /* include GPD, SYSINTE, SYSINTS, GP_CFG0 */
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#define SYS_GPIO_DIR 0x3004 /* direction control for GPIO */
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#define SYS_SYSINTE 0x3005 /* system interrupt enable */
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#define SYS_SYSINTS 0x3006 /* system interrupt status */
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#define SYS_GPIO_CFG0 0x3007 /* PAD configuration for GPIO0-GPIO3 */
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#define SYS_SYS2 0x3008 /* include GP_CFG1 and 3 reserved bytes */
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#define SYS_GPIO_CFG1 0x3008 /* PAD configuration for GPIO4 */
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#define SYS_DEMOD_CTL1 0x300B
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/* IrDA registers */
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#define SYS_IRRC_PSR 0x3020 /* IR protocol selection */
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#define SYS_IRRC_PER 0x3024 /* IR protocol extension */
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#define SYS_IRRC_SF 0x3028 /* IR sampling frequency */
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#define SYS_IRRC_DPIR 0x302C /* IR data package interval */
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#define SYS_IRRC_CR 0x3030 /* IR control */
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#define SYS_IRRC_RP 0x3034 /* IR read port */
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#define SYS_IRRC_SR 0x3038 /* IR status */
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/* I2C master registers */
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#define SYS_I2CCR 0x3040 /* I2C clock */
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#define SYS_I2CMCR 0x3044 /* I2C master control */
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#define SYS_I2CMSTR 0x3048 /* I2C master SCL timing */
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#define SYS_I2CMSR 0x304C /* I2C master status */
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#define SYS_I2CMFR 0x3050 /* I2C master FIFO */
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/*
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* IR registers
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*/
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#define IR_RX_BUF 0xFC00
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#define IR_RX_IE 0xFD00
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#define IR_RX_IF 0xFD01
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#define IR_RX_CTRL 0xFD02
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#define IR_RX_CFG 0xFD03
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#define IR_MAX_DURATION0 0xFD04
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#define IR_MAX_DURATION1 0xFD05
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#define IR_IDLE_LEN0 0xFD06
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#define IR_IDLE_LEN1 0xFD07
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#define IR_GLITCH_LEN 0xFD08
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#define IR_RX_BUF_CTRL 0xFD09
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#define IR_RX_BUF_DATA 0xFD0A
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#define IR_RX_BC 0xFD0B
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#define IR_RX_CLK 0xFD0C
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#define IR_RX_C_COUNT_L 0xFD0D
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#define IR_RX_C_COUNT_H 0xFD0E
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#define IR_SUSPEND_CTRL 0xFD10
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#define IR_ERR_TOL_CTRL 0xFD11
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#define IR_UNIT_LEN 0xFD12
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#define IR_ERR_TOL_LEN 0xFD13
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#define IR_MAX_H_TOL_LEN 0xFD14
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#define IR_MAX_L_TOL_LEN 0xFD15
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#define IR_MASK_CTRL 0xFD16
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#define IR_MASK_DATA 0xFD17
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#define IR_RES_MASK_ADDR 0xFD18
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#define IR_RES_MASK_T_LEN 0xFD19
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static volatile int do_exit = 0;
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struct dongle_state
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{
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int exit_flag;
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int rc_active;
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pthread_t thread;
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rtlsdr_dev_t *dev;
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int dev_index;
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};
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// Register I/O
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static int rtl28xxu_wr_regs(struct dongle_state *d, uint16_t reg, uint8_t *val, int len)
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{
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/* TODO
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struct rtl28xxu_req req;
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if (reg < 0x3000)
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req.index = CMD_USB_WR;
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else if (reg < 0x4000)
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req.index = CMD_SYS_WR;
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else
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req.index = CMD_IR_WR;
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req.value = reg;
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req.size = len;
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req.data = val;
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return rtl28xxu_ctrl_msg(d, &req);
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*/
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}
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static int rtl28xxu_rd_regs(struct dongle_state *d, uint16_t reg, uint8_t *val, int len)
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{
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/* TODO
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struct rtl28xxu_req req;
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if (reg < 0x3000)
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req.index = CMD_USB_RD;
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else if (reg < 0x4000)
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req.index = CMD_SYS_RD;
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else
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req.index = CMD_IR_RD;
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req.value = reg;
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req.size = len;
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req.data = val;
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return rtl28xxu_ctrl_msg(d, &req);
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*/
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}
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static int rtl28xxu_wr_reg(struct dongle_state *d, uint16_t reg, uint8_t val)
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{
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return rtl28xxu_wr_regs(d, reg, &val, 1);
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}
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static int rtl28xxu_rd_reg(struct dongle_state *d, uint16_t reg, uint8_t *val)
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{
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return rtl28xxu_rd_regs(d, reg, val, 1);
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}
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static int rtl28xxu_wr_reg_mask(struct dongle_state *d, uint16_t reg, uint8_t val,
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uint8_t mask)
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{
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int ret;
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uint8_t tmp;
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/* no need for read if whole reg is written */
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if (mask != 0xff) {
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ret = rtl28xxu_rd_reg(d, reg, &tmp);
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if (ret)
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return ret;
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val &= mask;
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tmp &= ~mask;
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val |= tmp;
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}
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return rtl28xxu_wr_reg(d, reg, val);
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}
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struct rtlsdr_dev2 {
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libusb_context *ctx;
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struct libusb_device_handle *devh;
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};
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void dongle_init(struct dongle_state *s)
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{
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s->dev_index = 0;
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bzero(s, sizeof(struct dongle_state));
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}
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struct dongle_state dongle;
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@ -103,6 +350,98 @@ static void *dongle_thread_fn(void *arg)
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return 0;
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}
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static int rtl2832u_rc_query(struct dongle_state *d)
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{
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int ret, i, len;
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rtlsdr_dev_t *dev = d->dev;
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uint8_t buf[128];
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static const struct rtl28xxu_reg_val_mask refresh_tab[] = {
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{IR_RX_IF, 0x03, 0xff},
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{IR_RX_BUF_CTRL, 0x80, 0xff},
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{IR_RX_CTRL, 0x80, 0xff},
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};
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/* init remote controller */
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if (!d->rc_active) {
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static const struct rtl28xxu_reg_val_mask init_tab[] = {
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{SYS_DEMOD_CTL1, 0x00, 0x04},
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{SYS_DEMOD_CTL1, 0x00, 0x08},
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{USB_CTRL, 0x20, 0x20},
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{SYS_GPIO_DIR, 0x00, 0x08},
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{SYS_GPIO_OUT_EN, 0x08, 0x08},
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{SYS_GPIO_OUT_VAL, 0x08, 0x08},
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{IR_MAX_DURATION0, 0xd0, 0xff},
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{IR_MAX_DURATION1, 0x07, 0xff},
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{IR_IDLE_LEN0, 0xc0, 0xff},
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{IR_IDLE_LEN1, 0x00, 0xff},
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{IR_GLITCH_LEN, 0x03, 0xff},
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{IR_RX_CLK, 0x09, 0xff},
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{IR_RX_CFG, 0x1c, 0xff},
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{IR_MAX_H_TOL_LEN, 0x1e, 0xff},
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{IR_MAX_L_TOL_LEN, 0x1e, 0xff},
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{IR_RX_CTRL, 0x80, 0xff},
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};
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for (i = 0; i < ARRAY_SIZE(init_tab); i++) {
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ret = rtl28xxu_wr_reg_mask(d, init_tab[i].reg,
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init_tab[i].val, init_tab[i].mask);
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if (ret)
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goto err;
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}
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d->rc_active = 1;
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}
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ret = rtl28xxu_rd_reg(d, IR_RX_IF, &buf[0]);
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if (ret)
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goto err;
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if (buf[0] != 0x83)
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goto exit;
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ret = rtl28xxu_rd_reg(d, IR_RX_BC, &buf[0]);
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if (ret)
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goto err;
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len = buf[0];
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/* read raw code from hw */
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ret = rtl28xxu_rd_regs(d, IR_RX_BUF, buf, len);
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if (ret)
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goto err;
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/* let hw receive new code */
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for (i = 0; i < ARRAY_SIZE(refresh_tab); i++) {
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ret = rtl28xxu_wr_reg_mask(d, refresh_tab[i].reg,
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refresh_tab[i].val, refresh_tab[i].mask);
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if (ret)
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goto err;
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}
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/* pass data to Kernel IR decoder */
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//TODO init_ir_raw_event(&ev);
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printf("IR: \n");
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for (i = 0; i < len; i++) {
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//ev.pulse = buf[i] >> 7;
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//ev.duration = 50800 * (buf[i] & 0x7f);
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printf("pulse %d, duration %d\n", buf[i] >> 7, 50800 * (buf[i] & 0x7f));
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//TODO
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//ir_raw_event_store_with_filter(d->rc_dev, &ev);
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}
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/* 'flush' ir_raw_event_store_with_filter() */
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/*TODO
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ir_raw_event_set_idle(d->rc_dev, true);
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ir_raw_event_handle(d->rc_dev);
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*/
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exit:
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return ret;
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err:
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//dev_dbg(&d->intf->dev, "failed=%d\n", ret);
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return ret;
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}
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int main(int argc, char **argv) {
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#ifndef _WIN32
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