mirror of https://github.com/drowe67/librtlsdr.git
activate/use RTL's IF AGC control .. from https://github.com/old-dab/rtlsdr
purpose: make AGC more smooth .. and NOT freeze Signed-off-by: hayati ayguen <h_ayguen@web.de>development
hayati ayguen
parent
bff8cf771d
commit
a3349bd52b
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@ -9,6 +9,9 @@
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#define FC2580_CHECK_ADDR 0x01
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#define FC2580_CHECK_VAL 0x56
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/* 16.384 MHz (at least on the Logilink VG0002A) */
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#define FC2580_XTAL_FREQ 16384000
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typedef enum {
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FC2580_UHF_BAND,
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FC2580_L_BAND,
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@ -100,6 +100,11 @@
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#define INIT_R820T_TUNER_GAIN 0
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/* activate/use RTL's IF AGC control .. from https://github.com/old-dab/rtlsdr
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* purpose: make AGC more smooth .. and NOT freeze
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* most of it is in switch case on tuner_type in rtlsdr_open() */
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#define USE_OLD_DAB_IF_GAIN 1
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typedef struct rtlsdr_tuner_iface {
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/* tuner interface */
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@ -460,10 +465,12 @@ int rtlsdr_vga_control( rtlsdr_dev_t* devt, int rc, int rtl_vga_control ) {
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if ( rtl_vga_control != devt->rtl_vga_control ) {
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/* enable/disable RF AGC loop */
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#if USE_OLD_DAB_IF_GAIN == 0
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rc = rtlsdr_demod_write_reg(devt, 1, 0x04, rtl_vga_control ? 0x80 : 0x00, 1);
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if ( devt->verbose )
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fprintf(stderr, "rtlsdr_vga_control(%s) returned %d\n"
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, rtl_vga_control ? "activate" : "deactivate", rc );
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#endif
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devt->rtl_vga_control = rtl_vga_control;
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}
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return rc;
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@ -1034,7 +1041,9 @@ void rtlsdr_init_baseband(rtlsdr_dev_t *dev)
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rtlsdr_demod_write_reg(dev, 1, 0x11, 0x00, 1);
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/* disable RF and IF AGC loop */
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#if USE_OLD_DAB_IF_GAIN == 0
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rtlsdr_demod_write_reg(dev, 1, 0x04, 0x00, 1);
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#endif
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dev->rtl_vga_control = 0;
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/* disable PID filter (enable_PID = 0) */
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@ -3069,20 +3078,97 @@ found:
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dev->tuner = &tuners[dev->tuner_type];
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switch (dev->tuner_type) {
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case RTLSDR_TUNER_FC2580:
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#if USE_OLD_DAB_IF_GAIN
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dev->tun_xtal = FC2580_XTAL_FREQ;
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#endif
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break;
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case RTLSDR_TUNER_E4000:
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#if USE_OLD_DAB_IF_GAIN
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rtlsdr_demod_write_reg(dev, 1, 0x12, 0x5a, 1);//DVBT_DAGC_TRG_VAL
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rtlsdr_demod_write_reg(dev, 1, 0x02, 0x40, 1);//DVBT_AGC_TARG_VAL_0
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rtlsdr_demod_write_reg(dev, 1, 0x03, 0x5a, 1);//DVBT_AGC_TARG_VAL_8_1
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rtlsdr_demod_write_reg(dev, 1, 0xc7, 0x30, 1);//DVBT_AAGC_LOOP_GAIN
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rtlsdr_demod_write_reg(dev, 1, 0x04, 0xd0, 1);//DVBT_LOOP_GAIN2_3_0
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rtlsdr_demod_write_reg(dev, 1, 0x05, 0xbe, 1);//DVBT_LOOP_GAIN2_4
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rtlsdr_demod_write_reg(dev, 1, 0xc8, 0x18, 1);//DVBT_LOOP_GAIN3
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rtlsdr_demod_write_reg(dev, 1, 0x06, 0x35, 1);//DVBT_VTOP1
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rtlsdr_demod_write_reg(dev, 1, 0xc9, 0x21, 1);//DVBT_VTOP2
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rtlsdr_demod_write_reg(dev, 1, 0xca, 0x21, 1);//DVBT_VTOP3
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rtlsdr_demod_write_reg(dev, 1, 0xcb, 0x00, 1);//DVBT_KRF1
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rtlsdr_demod_write_reg(dev, 1, 0x07, 0x40, 1);//DVBT_KRF2
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rtlsdr_demod_write_reg(dev, 1, 0xcd, 0x10, 1);//DVBT_KRF3
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rtlsdr_demod_write_reg(dev, 1, 0xce, 0x10, 1);//DVBT_KRF4
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rtlsdr_demod_write_reg(dev, 0, 0x11, 0xe9d4, 2);//DVBT_AD7_SETTING
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rtlsdr_demod_write_reg(dev, 1, 0xe5, 0xf0, 1);//DVBT_EN_GI_PGA
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rtlsdr_demod_write_reg(dev, 1, 0xd9, 0x00, 1);//DVBT_THD_LOCK_UP
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rtlsdr_demod_write_reg(dev, 1, 0xdb, 0x00, 1);//DVBT_THD_LOCK_DW
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rtlsdr_demod_write_reg(dev, 1, 0xdd, 0x14, 1);//DVBT_THD_UP1
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rtlsdr_demod_write_reg(dev, 1, 0xde, 0xec, 1);//DVBT_THD_DW1
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rtlsdr_demod_write_reg(dev, 1, 0xd8, 0x0c, 1);//DVBT_INTER_CNT_LEN
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rtlsdr_demod_write_reg(dev, 1, 0xe6, 0x02, 1);//DVBT_GI_PGA_STATE
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rtlsdr_demod_write_reg(dev, 1, 0xd7, 0x09, 1);//DVBT_EN_AGC_PGA
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rtlsdr_demod_write_reg(dev, 0, 0x10, 0x49, 1);//DVBT_REG_GPO
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rtlsdr_demod_write_reg(dev, 0, 0x0d, 0x85, 1);//DVBT_REG_MON,DVBT_REG_MONSEL
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rtlsdr_demod_write_reg(dev, 0, 0x13, 0x02, 1);
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#endif
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break;
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case RTLSDR_TUNER_FC0012:
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case RTLSDR_TUNER_FC0013:
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#if USE_OLD_DAB_IF_GAIN
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rtlsdr_demod_write_reg(dev, 1, 0x12, 0x5a, 1);//DVBT_DAGC_TRG_VAL
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rtlsdr_demod_write_reg(dev, 1, 0x02, 0x40, 1);//DVBT_AGC_TARG_VAL_0
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rtlsdr_demod_write_reg(dev, 1, 0x03, 0x5a, 1);//DVBT_AGC_TARG_VAL_8_1
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rtlsdr_demod_write_reg(dev, 1, 0xc7, 0x2c, 1);//DVBT_AAGC_LOOP_GAIN
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rtlsdr_demod_write_reg(dev, 1, 0x04, 0xcc, 1);//DVBT_LOOP_GAIN2_3_0
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rtlsdr_demod_write_reg(dev, 1, 0x05, 0xbe, 1);//DVBT_LOOP_GAIN2_4
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rtlsdr_demod_write_reg(dev, 1, 0xc8, 0x16, 1);//DVBT_LOOP_GAIN3
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rtlsdr_demod_write_reg(dev, 1, 0x06, 0x35, 1);//DVBT_VTOP1
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rtlsdr_demod_write_reg(dev, 1, 0xc9, 0x21, 1);//DVBT_VTOP2
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rtlsdr_demod_write_reg(dev, 1, 0xca, 0x21, 1);//DVBT_VTOP3
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rtlsdr_demod_write_reg(dev, 1, 0xcb, 0x00, 1);//DVBT_KRF1
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rtlsdr_demod_write_reg(dev, 1, 0x07, 0x40, 1);//DVBT_KRF2
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rtlsdr_demod_write_reg(dev, 1, 0xcd, 0x10, 1);//DVBT_KRF3
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rtlsdr_demod_write_reg(dev, 1, 0xce, 0x10, 1);//DVBT_KRF4
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rtlsdr_demod_write_reg(dev, 0, 0x11, 0xe9bf, 2);//DVBT_AD7_SETTING
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rtlsdr_demod_write_reg(dev, 1, 0xe5, 0xf0, 1);//DVBT_EN_GI_PGA
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rtlsdr_demod_write_reg(dev, 1, 0xd9, 0x00, 1);//DVBT_THD_LOCK_UP
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rtlsdr_demod_write_reg(dev, 1, 0xdb, 0x00, 1);//DVBT_THD_LOCK_DW
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rtlsdr_demod_write_reg(dev, 1, 0xdd, 0x11, 1);//DVBT_THD_UP1
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rtlsdr_demod_write_reg(dev, 1, 0xde, 0xef, 1);//DVBT_THD_DW1
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rtlsdr_demod_write_reg(dev, 1, 0xd8, 0x0c, 1);//DVBT_INTER_CNT_LEN
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rtlsdr_demod_write_reg(dev, 1, 0xe6, 0x02, 1);//DVBT_GI_PGA_STATE
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rtlsdr_demod_write_reg(dev, 1, 0xd7, 0x09, 1);//DVBT_EN_AGC_PGA
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#endif
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break;
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case RTLSDR_TUNER_R828D:
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dev->tun_xtal = R828D_XTAL_FREQ;
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/* fall-through */
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case RTLSDR_TUNER_R820T:
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#if USE_OLD_DAB_IF_GAIN
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rtlsdr_demod_write_reg(dev, 1, 0x12, 0x5a, 1);//DVBT_DAGC_TRG_VAL
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rtlsdr_demod_write_reg(dev, 1, 0x02, 0x40, 1);//DVBT_AGC_TARG_VAL_0
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rtlsdr_demod_write_reg(dev, 1, 0x03, 0x80, 1);//DVBT_AGC_TARG_VAL_8_1
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rtlsdr_demod_write_reg(dev, 1, 0xc7, 0x24, 1);//DVBT_AAGC_LOOP_GAIN
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rtlsdr_demod_write_reg(dev, 1, 0x04, 0xcc, 1);//DVBT_LOOP_GAIN2_3_0
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rtlsdr_demod_write_reg(dev, 1, 0x05, 0xbe, 1);//DVBT_LOOP_GAIN2_4
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rtlsdr_demod_write_reg(dev, 1, 0xc8, 0x14, 1);//DVBT_LOOP_GAIN3
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rtlsdr_demod_write_reg(dev, 1, 0x06, 0x35, 1);//DVBT_VTOP1
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rtlsdr_demod_write_reg(dev, 1, 0xc9, 0x21, 1);//DVBT_VTOP2
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rtlsdr_demod_write_reg(dev, 1, 0xca, 0x21, 1);//DVBT_VTOP3
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rtlsdr_demod_write_reg(dev, 1, 0xcb, 0x00, 1);//DVBT_KRF1
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rtlsdr_demod_write_reg(dev, 1, 0x07, 0x40, 1);//DVBT_KRF2
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rtlsdr_demod_write_reg(dev, 1, 0xcd, 0x10, 1);//DVBT_KRF3
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rtlsdr_demod_write_reg(dev, 1, 0xce, 0x10, 1);//DVBT_KRF4
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rtlsdr_demod_write_reg(dev, 0, 0x11, 0xe9f4, 2);//DVBT_AD7_SETTING
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#endif
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/* disable Zero-IF mode */
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rtlsdr_demod_write_reg(dev, 1, 0xb1, 0x1a, 1);
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/* only enable In-phase ADC input */
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rtlsdr_demod_write_reg(dev, 0, 0x08, 0x4d, 1);
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/* the R82XX use 3.57 MHz IF for the DVB-T 6 MHz mode, and
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* 4.57 MHz for the 8 MHz mode */
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rtlsdr_set_if_freq(dev, R82XX_IF_FREQ);
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/* enable spectrum inversion */
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rtlsdr_demod_write_reg(dev, 1, 0x15, 0x01, 1);
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break;
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