mirror of https://github.com/drowe67/librtlsdr.git
added librtsdr options vcocmin/vcocmax/vcoalgo for testing
* see https://github.com/librtlsdr/librtlsdr/issues/91 * vcocmin/vcocmax: sets VCO current for R820T/2 * added tuner internal caching for VCO current, that register isn't written when unnecessary * added vcoalgo option: - vcoalgo=2 allows to select/use r82xx_set_pll() from https://github.com/rtlsdrblog/rtl-sdr.git - vcoalgo=1 is previous algorithm, just with higher vco_max=3.9GHz - vcoalgo=0 is previous algorithm - the default: kept this until https://github.com/steve-m/librtlsdr/pull/10 is measured * rtl_test: added options -f and -e to define where to start and end the tuner range test .. for quicker testing if the new options change/extend the tuner's frequency range Signed-off-by: hayati ayguen <h_ayguen@web.de>development
hayati ayguen
parent
907da08bfc
commit
c7d071e17e
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@ -68,6 +68,9 @@ enum r82xx_xtal_cap_value {
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struct r82xx_config {
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uint8_t i2c_addr;
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uint8_t vco_curr_min; /* VCO min/max current for R18/0x12 bits [7:5] in 0 .. 7. use 0xff for default */
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uint8_t vco_curr_max; /* value is inverted: programmed is 7-value, that 0 is lowest current */
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uint8_t vco_algo;
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uint32_t xtal;
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enum r82xx_chip rafael_chip;
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unsigned int max_i2c_msg_len;
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@ -89,6 +92,7 @@ struct r82xx_priv {
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* on which the band center shall be positioned */
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uint8_t fil_cal_code;
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uint8_t input;
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uint8_t last_vco_curr;
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int has_lock;
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int init_done;
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int sideband;
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@ -99,6 +99,8 @@
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#define LOG_API_SET_FREQ 0
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#define INIT_R820T_TUNER_GAIN 0
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#define ENABLE_VCO_OPTIONS 1
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/* activate/use RTL's IF AGC control .. from https://github.com/old-dab/rtlsdr
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* purpose: make AGC more smooth .. and NOT freeze
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@ -379,6 +381,10 @@ int r820t_init(void *dev) {
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devt->r82xx_c.rafael_chip = CHIP_R820T;
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}
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devt->r82xx_c.vco_curr_min = 0xff; /* VCO min/max current for R18/0x12 bits [7:5] in 0 .. 7. use 0xff for default */
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devt->r82xx_c.vco_curr_max = 0xff; /* value is inverted: programmed is 7-value, that 0 is lowest current */
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devt->r82xx_c.vco_algo = 0x00;
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rtlsdr_get_xtal_freq(devt, NULL, &devt->r82xx_c.xtal);
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devt->r82xx_c.max_i2c_msg_len = 8;
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@ -4184,6 +4190,11 @@ const char * rtlsdr_get_opt_help(int longInfo)
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"\t\t 0: use I & Q; 1: use I; 2: use Q; 3: use I below threshold frequency;\n"
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"\t\t 4: use Q below threshold frequency (=RTL-SDR v3)\n"
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"\t\t other values set the threshold frequency\n"
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#if ENABLE_VCO_OPTIONS
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"\t\tvcocmin=<current> set R820T/2 VCO current min: 0..7: higher value is more current\n"
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"\t\tvcocmax=<current> set R820T/2 VCO current max: 0..7\n"
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"\t\tvcoalgo=<algo> set R820T/2 VCO algorithm. 0: default. 1: with vcomax=3.9G. 2: Youssef/Carl\n"
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#endif
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"\t\tTp=<gpio_pin> set GPIO pin for Bias T, default =0 for rtl-sdr.com compatible V3\n"
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"\t\tT=<bias_tee> 1 activates power at antenna one some dongles, e.g. rtl-sdr.com's V3\n"
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#ifdef WITH_UDP_SERVER
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@ -4196,7 +4207,12 @@ const char * rtlsdr_get_opt_help(int longInfo)
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"\t[-O\tset RTL options string seperated with ':', e.g. -O 'bc=30000:agc=0' ]\n"
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"\t\tverbose:f=<freqHz>:bw=<bw_in_kHz>:bc=<if_in_Hz>:sb=<sideband>\n"
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"\t\tagc=<tuner_gain_mode>:gain=<tenth_dB>:ifm=<tuner_if_mode>:dagc=<rtl_agc>\n"
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#if ENABLE_VCO_OPTIONS
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"\t\tds=<direct_sampling>:dm=<ds_mode_thresh>:vcocmin=<c>:vcocmax=<c>:vcoalgo=<a>\n"
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"\t\tT=<bias_tee>\n"
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#else
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"\t\tds=<direct_sampling>:dm=<ds_mode_thresh>:T=<bias_tee>\n"
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#endif
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#ifdef WITH_UDP_SERVER
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"\t\tport=<udp_port default with 1>\n"
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#endif
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@ -4314,6 +4330,47 @@ int rtlsdr_set_opt_string(rtlsdr_dev_t *dev, const char *opts, int verbose)
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dev->direct_sampling_threshold = dm;
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ret = rtlsdr_set_ds_mode(dev, dev->direct_sampling_mode, dev->direct_sampling_threshold);
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}
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#if ENABLE_VCO_OPTIONS
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else if (!strncmp(optPart, "vcocmin=", 8)) {
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int current = atoi(optPart +8);
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if ( 0 <= current && current <= 7 )
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{
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dev->r82xx_c.vco_curr_min = 7 - current;
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ret = 0;
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if (verbose)
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fprintf(stderr, "\nrtlsdr_set_opt_string(): parsed vcocmin config %d\n", current);
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} else if (verbose) {
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fprintf(stderr, "\nrtlsdr_set_opt_string(): error parsing vcocmin config: valid range 0 .. 7\n");
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ret = 1;
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}
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}
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else if (!strncmp(optPart, "vcocmax=", 8)) {
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int current = atoi(optPart +8);
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if ( 0 <= current && current <= 7 )
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{
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dev->r82xx_c.vco_curr_max = 7 - current;
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ret = 0;
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if (verbose)
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fprintf(stderr, "\nrtlsdr_set_opt_string(): parsed vcocmax config %d\n", current);
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} else if (verbose) {
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fprintf(stderr, "\nrtlsdr_set_opt_string(): error parsing vcocmax config: valid range 0 .. 7\n");
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ret = 1;
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}
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}
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else if (!strncmp(optPart, "vcoalgo=", 8)) {
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int algo = atoi(optPart +8);
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if ( 0 <= algo && algo <= 2 )
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{
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dev->r82xx_c.vco_curr_max = algo;
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ret = 0;
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if (verbose)
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fprintf(stderr, "\nrtlsdr_set_opt_string(): parsed vcoalgo config %d\n", algo);
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} else if (verbose) {
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fprintf(stderr, "\nrtlsdr_set_opt_string(): error parsing vcoalgo config: valid range 0 .. 2\n");
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ret = 1;
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}
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}
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#endif
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else if (!strncmp(optPart, "tp=", 3) || !strncmp(optPart, "Tp=", 3) || !strncmp(optPart, "TP=", 3) ) {
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int gpio_pin_no = atoi(optPart +3);
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if (verbose)
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@ -107,6 +107,8 @@ void usage(void)
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"\t[-d device_index or serial (default: 0)]\n"
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"%s"
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"\t[-t enable tuner range benchmark]\n"
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"\t[-f first/begin frequency for tuner range benchmark, default: 0]\n"
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"\t[-e end frequency for tuner range benchmark, default: 3e9 = 3G ]\n"
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#ifndef _WIN32
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"\t[-p[seconds] enable PPM error measurement (default: 10 seconds)]\n"
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#endif
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@ -338,9 +340,9 @@ static int set_center_freq_wait(rtlsdr_dev_t *dev, uint32_t freq, const char * s
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}
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void tuner_benchmark(void)
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void tuner_benchmark(uint32_t beg_freq, uint32_t end_freq)
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{
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uint32_t current = max_step(0);
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uint32_t current = beg_freq; /* max_step(0); */
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uint32_t band_start = 0;
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uint32_t low_bound = 0, high_bound = 0;
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int rc;
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@ -357,16 +359,16 @@ void tuner_benchmark(void)
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*/
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/* handle bands starting at 0Hz */
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rc = set_center_freq_wait(dev, 0, "FIND_START");
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rc = set_center_freq_wait(dev, current, "FIND_START");
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if (rc < 0)
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state = FIND_START;
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else {
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band_start = 0;
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band_start = current;
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report_band_start(band_start);
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state = FIND_END;
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}
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while (current < 3e9 && !do_exit) {
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while (current < end_freq && !do_exit) {
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switch (state) {
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case FIND_START:
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/* scanning for the start of a new band */
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@ -508,10 +510,12 @@ int main(int argc, char **argv)
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int dev_index = 0;
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int dev_given = 0;
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uint32_t out_block_size = DEFAULT_BUF_LENGTH;
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uint32_t tuner_bench_beg_freq = 0;
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uint32_t tuner_bench_end_freq = 0;
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int count;
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int gains[100];
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while ((opt = getopt(argc, argv, "d:s:b:O:tp::Sh")) != -1) {
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while ((opt = getopt(argc, argv, "d:s:b:O:tf:e:p::Sh")) != -1) {
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switch (opt) {
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case 'd':
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dev_index = verbose_device_search(optarg);
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@ -529,6 +533,12 @@ int main(int argc, char **argv)
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case 't':
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test_mode = TUNER_BENCHMARK;
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break;
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case 'f':
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tuner_bench_beg_freq = (uint32_t)atofs(optarg);
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break;
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case 'e':
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tuner_bench_end_freq = (uint32_t)atofs(optarg);
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break;
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case 'p':
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test_mode = PPM_BENCHMARK;
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if (optarg)
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@ -598,7 +608,7 @@ int main(int argc, char **argv)
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}
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if (test_mode == TUNER_BENCHMARK) {
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tuner_benchmark();
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tuner_benchmark(tuner_bench_beg_freq, tuner_bench_end_freq);
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goto exit;
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}
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@ -33,6 +33,9 @@
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#define WITH_ASYM_FILTER 0
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#define PRINT_PLL_ERRORS 0
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#define PRINT_VGA_REG 0
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#define PRINT_INITIAL_REGISTERS 0
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#define PRINT_ACTUAL_VCO_AND_ERR 0
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/* #define VGA_FOR_AGC_MODE 16 */
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#define DEFAULT_IF_VGA_VAL 11
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@ -280,35 +283,35 @@ static const uint8_t r82xx_init_array[] = {
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0xc0, /* Reg 0x08 */
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0x40, /* Reg 0x09 */
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0xdb, /* Reg 0x0a */
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0xdb, /* Reg 0x0a */
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0x6b, /* Reg 0x0b */
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/* Reg 0x0c:
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* for manual gain was: set fixed VGA gain for now (16.3 dB): 0x08
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* with active agc was: set fixed VGA gain for now (26.5 dB): 0x0b */
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0xe0 | DEFAULT_IF_VGA_VAL, /* Reg 0x0c */
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0x53, /* Reg 0x0d */
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0x75, /* Reg 0x0e */
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0x53, /* Reg 0x0d */
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0x75, /* Reg 0x0e */
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0x68, /* Reg 0x0f */
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0x6c, /* Reg 0x10 */
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0xbb, /* Reg 0x11 */
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0x80, /* Reg 0x12 */
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0x6c, /* Reg 0x10 */
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0xbb, /* Reg 0x11 */
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0x80, /* Reg 0x12 */
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VER_NUM & 0x3f, /* Reg 0x13 */
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0x0f, /* Reg 0x14 */
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0x00, /* Reg 0x15 */
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0xc0, /* Reg 0x16 */
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0x0f, /* Reg 0x14 */
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0x00, /* Reg 0x15 */
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0xc0, /* Reg 0x16 */
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0x30, /* Reg 0x17 */
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0x48, /* Reg 0x18 */
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0xec, /* Reg 0x19 */
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0x60, /* Reg 0x1a */
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0x48, /* Reg 0x18 */
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0xec, /* Reg 0x19 */
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0x60, /* Reg 0x1a */
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0x00, /* Reg 0x1b */
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0x24, /* Reg 0x1c */
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0xdd, /* Reg 0x1d */
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0x0e, /* Reg 0x1e */
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0xdd, /* Reg 0x1d */
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0x0e, /* Reg 0x1e */
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0x40 /* Reg 0x1f */
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};
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@ -711,6 +714,128 @@ static int r82xx_set_mux(struct r82xx_priv *priv, uint32_t freq)
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return rc;
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}
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/* function of Youssef (AirSpy) and Carl (RTL-SDR) */
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static int r82xx_set_pll_yc(struct r82xx_priv *priv, uint32_t freq)
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{
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const uint32_t vco_min = 1770000000;
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const uint32_t vco_max = 3900000000;
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uint32_t pll_ref = (priv->cfg->xtal);
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uint32_t pll_ref_2x = (pll_ref * 2);
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int rc;
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uint32_t vco_exact;
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uint32_t vco_frac;
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uint32_t con_frac;
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uint32_t div_num;
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uint32_t n_sdm;
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uint16_t sdm;
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uint8_t ni;
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uint8_t si;
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uint8_t nint;
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uint8_t val_dith;
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uint8_t data[5];
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/* Calculate divider */
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for (div_num = 0; div_num < 5; div_num++)
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{
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vco_exact = freq << (div_num + 1);
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if (vco_exact >= vco_min && vco_exact <= vco_max)
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{
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break;
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}
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}
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vco_exact = freq << (div_num + 1);
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nint = (uint8_t) ((vco_exact + (pll_ref >> 16)) / pll_ref_2x);
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vco_frac = vco_exact - pll_ref_2x * nint;
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nint -= 13;
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ni = (nint >> 2);
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si = nint - (ni << 2);
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/* Set the phase splitter */
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rc = r82xx_write_reg_mask(priv, 0x10, (uint8_t) (div_num << 5), 0xe0);
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if(rc < 0)
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return rc;
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/* Disable Dither */
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val_dith = (priv->disable_dither) ? 0x10 : 0x00;
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rc = r82xx_write_reg_mask(priv, 0x12, val_dith, 0x18);
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if (rc < 0)
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return rc;
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/* Set the rough VCO frequency */
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rc = r82xx_write_reg(priv, 0x14, (uint8_t) (ni + (si << 6)));
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if(rc < 0)
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return rc;
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if (vco_frac == 0)
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{
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/* Disable frac pll */
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rc = r82xx_write_reg_mask(priv, 0x12, 0x08, 0x08);
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if(rc < 0)
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return rc;
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}
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else
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{
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vco_frac += pll_ref >> 16;
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sdm = 0;
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for(n_sdm = 0; n_sdm < 16; n_sdm++)
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{
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con_frac = pll_ref >> n_sdm;
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if (vco_frac >= con_frac)
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{
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sdm |= (uint16_t) (0x8000 >> n_sdm);
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vco_frac -= con_frac;
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if (vco_frac == 0)
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break;
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}
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}
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/*
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actual_freq = (((nint << 16) + sdm) * (uint64_t) pll_ref_2x) >> (div_num + 1 + 16);
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delta = freq - actual_freq
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if (actual_freq != freq)
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{
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fprintf(stderr,"Tunning delta: %d Hz", delta);
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}
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*/
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rc = r82xx_write_reg(priv, 0x15, (uint8_t)(sdm & 0xff));
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if (rc < 0)
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return rc;
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rc = r82xx_write_reg(priv, 0x16, (uint8_t)(sdm >> 8));
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if (rc < 0)
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return rc;
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/* Enable frac pll */
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rc = r82xx_write_reg_mask(priv, 0x12, 0x00, 0x08);
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if (rc < 0)
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return rc;
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}
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/***/
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/* Check if PLL has locked */
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rc = r82xx_read(priv, 0x00, data, 3);
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if (rc < 0)
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return rc;
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if (!(data[2] & 0x40)) {
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#if PRINT_PLL_ERRORS
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fprintf(stderr, "[R82XX] PLL not locked at Tuner LO %u Hz for RF %u Hz!\n",
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freq, priv->rf_freq);
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#endif
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priv->has_lock = 0;
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return -1;
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}
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priv->has_lock = 1;
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return rc;
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}
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static int r82xx_set_pll(struct r82xx_priv *priv, uint32_t freq)
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{
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/* freq == tuner's LO frequency */
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@ -718,7 +843,7 @@ static int r82xx_set_pll(struct r82xx_priv *priv, uint32_t freq)
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uint64_t vco_freq;
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uint64_t vco_div;
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uint32_t vco_min = 1770000; /* kHz */
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uint32_t vco_max = vco_min * 2; /* kHz */
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uint32_t vco_max = (priv->cfg->vco_algo == 0) ? (vco_min * 2) : 3900000; /* kHz */
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uint32_t freq_khz, pll_ref;
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uint32_t sdm = 0;
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uint8_t mix_div = 2;
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@ -727,8 +852,24 @@ static int r82xx_set_pll(struct r82xx_priv *priv, uint32_t freq)
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uint8_t vco_power_ref = 2;
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uint8_t refdiv2 = 0;
|
||||
uint8_t ni, si, nint, vco_fine_tune, val;
|
||||
uint8_t vco_curr_min = (priv->cfg->vco_curr_min == 0xff) ? 0x80 : ( priv->cfg->vco_curr_min << 5 );
|
||||
uint8_t vco_curr_max = (priv->cfg->vco_curr_max == 0xff) ? 0x60 : ( priv->cfg->vco_curr_max << 5 );
|
||||
/* devt->r82xx_c.vco_min = 0xff; * VCO min/max current for R18/0x12 bits [7:5] in 0 .. 7. use 0xff for default */
|
||||
/* devt->r82xx_c.vco_max = 0xff; * value is inverted: programmed is 7-value, that 0 is lowest current */
|
||||
uint8_t data[5];
|
||||
|
||||
if (priv->cfg->vco_algo == 2)
|
||||
{
|
||||
/* r82xx_set_pll_yc() assumes fixed maximum current */
|
||||
if (priv->last_vco_curr != vco_curr_max) {
|
||||
rc = r82xx_write_reg_mask(priv, 0x12, vco_curr_max, 0xe0);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
priv->last_vco_curr = vco_curr_max;
|
||||
}
|
||||
return r82xx_set_pll_yc(priv, freq);
|
||||
}
|
||||
|
||||
/* Frequency in kHz */
|
||||
freq_khz = (freq + 500) / 1000;
|
||||
pll_ref = priv->cfg->xtal;
|
||||
|
|
@ -743,9 +884,12 @@ static int r82xx_set_pll(struct r82xx_priv *priv, uint32_t freq)
|
|||
return rc;
|
||||
|
||||
/* set VCO current = 100 */
|
||||
rc = r82xx_write_reg_mask(priv, 0x12, 0x80, 0xe0);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
if (priv->last_vco_curr != vco_curr_min) {
|
||||
rc = r82xx_write_reg_mask(priv, 0x12, vco_curr_min, 0xe0);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
priv->last_vco_curr = vco_curr_min;
|
||||
}
|
||||
|
||||
/* Calculate divider */
|
||||
while (mix_div <= 64) {
|
||||
|
|
@ -802,10 +946,10 @@ static int r82xx_set_pll(struct r82xx_priv *priv, uint32_t freq)
|
|||
nint = (uint32_t) (vco_div / 65536);
|
||||
sdm = (uint32_t) (vco_div % 65536);
|
||||
|
||||
#if 0
|
||||
#if PRINT_ACTUAL_VCO_AND_ERR
|
||||
{
|
||||
uint64_t actual_vco = (uint64_t)2 * pll_ref * nint + (uint64_t)2 * pll_ref * sdm / 65536;
|
||||
fprintf(stderr, "[R82XX] requested %uHz; selected mix_div=%u vco_freq=%lu nint=%u sdm=%u; actual_vco=%lu; tuning error=%+dHz\n",
|
||||
fprintf(stderr, "[R82XX] requested %u Hz; selected mix_div=%u vco_freq=%lu nint=%u sdm=%u; actual_vco=%lu; tuning error=%+dHz\n",
|
||||
freq, mix_div, vco_freq, nint, sdm, actual_vco, (int32_t) (actual_vco - vco_freq) / mix_div);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -850,14 +994,17 @@ static int r82xx_set_pll(struct r82xx_priv *priv, uint32_t freq)
|
|||
rc = r82xx_read(priv, 0x00, data, 3);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
if (data[2] & 0x40)
|
||||
if ( (data[2] & 0x40) || vco_curr_max == vco_curr_min )
|
||||
break;
|
||||
|
||||
if (!i) {
|
||||
/* Didn't lock. Increase VCO current */
|
||||
rc = r82xx_write_reg_mask(priv, 0x12, 0x60, 0xe0);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
if (priv->last_vco_curr != vco_curr_max) {
|
||||
rc = r82xx_write_reg_mask(priv, 0x12, vco_curr_max, 0xe0);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
priv->last_vco_curr = vco_curr_max;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1752,6 +1899,19 @@ int r82xx_init(struct r82xx_priv *priv)
|
|||
{
|
||||
int rc;
|
||||
|
||||
#if PRINT_INITIAL_REGISTERS
|
||||
#define INIT_NUM_READ_REGS 16
|
||||
uint8_t initial_register_values[INIT_NUM_READ_REGS]; /* see what is 'default' */
|
||||
int k;
|
||||
/* get initial register values - just to see .. */
|
||||
memset( &(initial_register_values[0]), 0, sizeof(initial_register_values) );
|
||||
printf("R820T/2 initial register settings:\n");
|
||||
r82xx_read(priv, 0x00, initial_register_values, sizeof(initial_register_values));
|
||||
for (k=0; k < INIT_NUM_READ_REGS; ++k)
|
||||
printf("register 0x%02x: 0x%02x\n", k, initial_register_values[k]);
|
||||
printf("\n");
|
||||
#endif
|
||||
|
||||
/* TODO: R828D might need r82xx_xtal_check() */
|
||||
priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
|
||||
|
||||
|
|
@ -1764,6 +1924,7 @@ int r82xx_init(struct r82xx_priv *priv)
|
|||
priv->last_LNA_value = 0;
|
||||
priv->last_Mixer_value = 0;
|
||||
priv->last_VGA_value = DEFAULT_IF_VGA_VAL;
|
||||
priv->last_vco_curr = 0xff;
|
||||
|
||||
/* Initialize override registers */
|
||||
memset( &(priv->override_data[0]), 0, NUM_REGS * sizeof(uint8_t) );
|
||||
|
|
@ -1773,6 +1934,8 @@ int r82xx_init(struct r82xx_priv *priv)
|
|||
rc = r82xx_write_arr(priv, 0x05,
|
||||
r82xx_init_array, sizeof(r82xx_init_array));
|
||||
|
||||
priv->last_vco_curr = r82xx_init_array[0x12 - 0x05] & 0xe0;
|
||||
|
||||
rc = r82xx_set_tv_standard(priv, TUNER_DIGITAL_TV, 0);
|
||||
if (rc < 0)
|
||||
goto err;
|
||||
|
|
|
|||
Loading…
Reference in New Issue