mirror of https://github.com/M17-Project/TR-9.git
added 6 testpoints
Wojciech Kaczmarski
GitHub
parent
61f4d3f7d7
commit
ca3b1df06c
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@ -1,5 +1,4 @@
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EESchema Schematic File Version 4
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EESchema Schematic File Version 4
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LIBS:Mainboard-cache
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EELAYER 30 0
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EELAYER 30 0
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EELAYER END
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EELAYER END
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$Descr A4 11693 8268
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$Descr A4 11693 8268
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@ -1433,7 +1432,7 @@ Connection ~ 1550 3000
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Wire Wire Line
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Wire Wire Line
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1550 3000 1550 2950
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1550 3000 1550 2950
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Wire Wire Line
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Wire Wire Line
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1150 4700 1500 4700
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1150 4700 1350 4700
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Wire Wire Line
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Wire Wire Line
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1550 3850 1550 3500
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1550 3850 1550 3500
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Wire Wire Line
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Wire Wire Line
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@ -1482,9 +1481,7 @@ F 3 "~" H 1900 6250 50 0001 C CNN
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1 1900 6250
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1 1900 6250
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0 1 1 0
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0 1 1 0
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$EndComp
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$EndComp
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Wire Wire Line
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Text GLabel 4150 6350 2 50 Output ~ 10
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4100 6350 3850 6350
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Text GLabel 4100 6350 2 50 Output ~ 10
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ADC3_1
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ADC3_1
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Wire Wire Line
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Wire Wire Line
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6300 6150 6300 6350
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6300 6150 6300 6350
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@ -1657,7 +1654,7 @@ Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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2600 5550 2600 5700
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2600 5550 2600 5700
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Wire Wire Line
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Wire Wire Line
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1150 6250 1400 6250
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1150 6250 1300 6250
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Wire Wire Line
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Wire Wire Line
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1700 5950 1900 5950
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1700 5950 1900 5950
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Wire Wire Line
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Wire Wire Line
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@ -1873,4 +1870,54 @@ Wire Wire Line
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2650 1450 2700 1450
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2650 1450 2700 1450
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Wire Wire Line
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Wire Wire Line
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2700 1450 2700 1550
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2700 1450 2700 1550
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$Comp
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L Mainboard-rescue:TestPoint_Probe-Connector TP?
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U 1 1 5E819125
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P 1300 6250
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AR Path="/5DF0E505/5E819125" Ref="TP?" Part="1"
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AR Path="/5DFC2ACA/5E819125" Ref="TP8" Part="1"
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F 0 "TP8" H 1453 6351 50 0000 L CNN
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F 1 "TestPoint_Probe" H 1453 6260 50 0000 L CNN
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F 2 "TestPoint:TestPoint_Pad_D1.0mm" H 1500 6250 50 0001 C CNN
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F 3 "~" H 1500 6250 50 0001 C CNN
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1 1300 6250
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0 -1 -1 0
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$EndComp
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Connection ~ 1300 6250
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Wire Wire Line
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1300 6250 1400 6250
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$Comp
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L Mainboard-rescue:TestPoint_Probe-Connector TP?
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U 1 1 5E826F59
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P 4000 6350
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AR Path="/5DF0E505/5E826F59" Ref="TP?" Part="1"
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AR Path="/5DFC2ACA/5E826F59" Ref="TP10" Part="1"
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F 0 "TP10" H 4150 6650 50 0000 L CNN
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F 1 "TestPoint_Probe" H 4150 6550 50 0000 L CNN
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F 2 "TestPoint:TestPoint_Pad_D1.0mm" H 4200 6350 50 0001 C CNN
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F 3 "~" H 4200 6350 50 0001 C CNN
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1 4000 6350
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1 0 0 -1
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$EndComp
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Connection ~ 4000 6350
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Wire Wire Line
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4000 6350 3850 6350
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Wire Wire Line
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4000 6350 4150 6350
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$Comp
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L Mainboard-rescue:TestPoint_Probe-Connector TP?
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U 1 1 5E8457FD
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P 1350 4700
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AR Path="/5DF0E505/5E8457FD" Ref="TP?" Part="1"
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AR Path="/5DFC2ACA/5E8457FD" Ref="TP9" Part="1"
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F 0 "TP9" H 1503 4801 50 0000 L CNN
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F 1 "TestPoint_Probe" H 1503 4710 50 0000 L CNN
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F 2 "TestPoint:TestPoint_Pad_D1.0mm" H 1550 4700 50 0001 C CNN
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F 3 "~" H 1550 4700 50 0001 C CNN
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1 1350 4700
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0 -1 -1 0
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$EndComp
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Connection ~ 1350 4700
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Wire Wire Line
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1350 4700 1500 4700
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$EndSCHEMATC
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$EndSCHEMATC
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@ -1,5 +1,4 @@
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EESchema Schematic File Version 4
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EESchema Schematic File Version 4
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LIBS:Mainboard-cache
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EELAYER 30 0
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EELAYER 30 0
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EELAYER END
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EELAYER END
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$Descr A4 11693 8268
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$Descr A4 11693 8268
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@ -1254,6 +1254,7 @@ F0 "U" -350 350 50 H V C CNN
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F1 "Memory_Flash_W25Q32JVSS" 300 350 50 H V C CNN
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F1 "Memory_Flash_W25Q32JVSS" 300 350 50 H V C CNN
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F2 "Package_SO:SOIC-8_5.23x5.23mm_P1.27mm" 0 0 50 H I C CNN
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F2 "Package_SO:SOIC-8_5.23x5.23mm_P1.27mm" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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ALIAS W25Q128JVS
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$FPLIST
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$FPLIST
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SOIC*5.23x5.23mm*P1.27mm*
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SOIC*5.23x5.23mm*P1.27mm*
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$ENDFPLIST
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$ENDFPLIST
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Binary file not shown.
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@ -1,4 +1,4 @@
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update=03/03/2020 18:39:45
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update=04/03/2020 08:23:52
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version=1
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version=1
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last_client=kicad
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last_client=kicad
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[general]
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[general]
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@ -1,5 +1,4 @@
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EESchema Schematic File Version 4
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EESchema Schematic File Version 4
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LIBS:Mainboard-cache
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EELAYER 30 0
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EELAYER 30 0
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EELAYER END
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EELAYER END
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$Descr A4 11693 8268
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$Descr A4 11693 8268
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@ -1,5 +1,4 @@
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EESchema Schematic File Version 4
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EESchema Schematic File Version 4
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LIBS:Mainboard-cache
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EELAYER 30 0
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EELAYER 30 0
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EELAYER END
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EELAYER END
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$Descr A4 11693 8268
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$Descr A4 11693 8268
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@ -1,5 +1,4 @@
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EESchema Schematic File Version 4
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EESchema Schematic File Version 4
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LIBS:Mainboard-cache
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EELAYER 30 0
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EELAYER 30 0
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EELAYER END
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EELAYER END
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$Descr A4 11693 8268
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$Descr A4 11693 8268
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -1,5 +1,4 @@
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EESchema Schematic File Version 4
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EESchema Schematic File Version 4
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LIBS:Mainboard-cache
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EELAYER 30 0
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EELAYER 30 0
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EELAYER END
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EELAYER END
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$Descr A4 11693 8268
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$Descr A4 11693 8268
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@ -1,5 +1,4 @@
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EESchema Schematic File Version 4
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EESchema Schematic File Version 4
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LIBS:Mainboard-cache
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EELAYER 30 0
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EELAYER 30 0
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EELAYER END
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EELAYER END
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$Descr A4 11693 8268
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$Descr A4 11693 8268
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@ -87,10 +86,8 @@ F 3 "" H 6650 4350 50 0001 C CNN
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$EndComp
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$EndComp
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Wire Wire Line
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Wire Wire Line
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6450 4150 6750 4150
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6450 4150 6750 4150
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Text GLabel 6850 3950 2 50 Input ~ 10
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Text GLabel 6750 3950 2 50 Input ~ 10
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UART3_RX
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UART3_RX
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Wire Wire Line
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6450 3950 6850 3950
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$Comp
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$Comp
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L Mainboard-rescue:Conn_01x10-Connector_Generic J7
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L Mainboard-rescue:Conn_01x10-Connector_Generic J7
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U 1 1 5E1EAE64
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U 1 1 5E1EAE64
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@ -178,4 +175,6 @@ Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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3900 3750 4000 3750
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3900 3750 4000 3750
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Connection ~ 4000 3750
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Connection ~ 4000 3750
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Wire Wire Line
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6450 3950 6750 3950
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$EndSCHEMATC
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$EndSCHEMATC
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@ -86,10 +86,8 @@ F 3 "" H 6650 4350 50 0001 C CNN
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$EndComp
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$EndComp
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Wire Wire Line
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Wire Wire Line
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6450 4150 6750 4150
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6450 4150 6750 4150
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Text GLabel 6850 3950 2 50 Input ~ 10
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Text GLabel 6750 3950 2 50 Input ~ 10
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UART3_RX
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UART3_RX
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Wire Wire Line
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6450 3950 6850 3950
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$Comp
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$Comp
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L Mainboard-rescue:Conn_01x10-Connector_Generic J7
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L Mainboard-rescue:Conn_01x10-Connector_Generic J7
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U 1 1 5E1EAE64
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U 1 1 5E1EAE64
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@ -177,4 +175,6 @@ Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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3900 3750 4000 3750
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3900 3750 4000 3750
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Connection ~ 4000 3750
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Connection ~ 4000 3750
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Wire Wire Line
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6450 3950 6750 3950
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$EndSCHEMATC
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$EndSCHEMATC
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Loading…
Reference in New Issue