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TR-9
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Wojciech Kaczmarski 2020-09-22 17:11:39 +02:00 committed by GitHub
parent c366804958
commit f5f9e52e28
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 202 additions and 24 deletions
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93
cubemx/Src/main.c
View File

@ -74,6 +74,7 @@
#define P_TYPE_VOICE (0b10<<1)
#define P_TYPE_DATA (0b01<<1)
const uint16_t crc_poly=0x5935;
/* USER CODE END Includes */
/* Private variables ---------------------------------------------------------*/
@ -82,6 +83,7 @@ ADC_HandleTypeDef hadc2;
ADC_HandleTypeDef hadc3;
DMA_HandleTypeDef hdma_adc1;
DMA_HandleTypeDef hdma_adc2;
DMA_HandleTypeDef hdma_adc3;
CRC_HandleTypeDef hcrc;
@ -167,8 +169,11 @@ struct moip_packet
uint8_t udp_frame[MOIP_UDP_SIZE];
//audio
uint16_t fm_demod_in[2*320];
uint16_t audio_samples[320];
volatile uint8_t dac_play=1; //is the DAC playing samples?
volatile uint8_t collect_samples=0; //collect ADC data?
volatile uint8_t buff_num=0; //which buffer is in use?
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
@ -222,7 +227,7 @@ void ypcmem(uint8_t *dst, uint8_t *src, uint16_t nBytes)
}
//uncomment these 2 funcs below if you are not using hardware CRC calculation unit
/*
uint16_t CRC_LUT[256];
void CRC_Init(uint16_t *crc_table, uint16_t poly)
{
uint16_t remainder;
@ -256,7 +261,6 @@ uint16_t CRC_M17(uint16_t* crc_table, const uint8_t* message, uint16_t nBytes)
return(remainder);
}
*/
//-------------------------------------M17-------------------------------------
uint64_t Encode_Callsign(const char *callsign)
@ -323,7 +327,7 @@ void M17_Framer(struct moip_packet *inp, uint8_t *out, uint8_t tr_end)
ypcmem(&out[20], &(inp->nonce), 14);
ypcmem(&out[34], &(inp->fn), 2);
ypcmem(&out[36], &(inp->payload), 16);
crc=0xBEEF;//CRC_M17(crc_lut, out, 52); TODO: fix this
crc=CRC_M17(CRC_LUT, out, 52); //TODO: fix this
ypcmem(&out[52], (uint8_t*)&crc, 2);
ypcmem((uint8_t*)&(inp->crc_udp), (uint8_t*)&crc, 2);
@ -968,6 +972,26 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
{
dac_play=0;
HAL_GPIO_TogglePin(N7_GPIO_Port, N7_Pin);
}
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
{
buff_num++;
buff_num%=2;
HAL_GPIO_WritePin(N8_GPIO_Port, N8_Pin, buff_num);
if(buff_num)
{
HAL_ADC_Start_DMA(&hadc3, &fm_demod_in[320], 320);
dac_play=0;
}
else
{
HAL_ADC_Start_DMA(&hadc3, fm_demod_in, 320);
dac_play=0;
}
}
/* USER CODE END 0 */
@ -1035,6 +1059,7 @@ int main(void)
TFT_Reset();
TFT_Init();
ADF_Init();
CRC_Init(CRC_LUT, crc_poly);
//DAC_OUT2 test
/*HAL_DAC_Start(&hdac, DAC_CHANNEL_2);
@ -1048,6 +1073,7 @@ int main(void)
HAL_Delay(50);
}*/
//SD card
if(f_mount(&SDFatFS, (TCHAR const*)SDPath, 0))
{
TFT_Clear(CL_BLACK);
@ -1105,10 +1131,12 @@ int main(void)
HAL_Delay(1);
//MoIP test
/*MoIP_Connect("192.168.1.186", 17000);
//MoIP_Connect("192.168.1.186", 17000);
/*MoIP_Connect("m17.link", 17000);
HAL_Delay(550);
sprintf(packet.dst, "SP5WWP");
sprintf(packet.dst, "W2FBI");
sprintf(packet.src, "SP5WWP");
sprintf(packet.dst, "KC1AWV");
packet.type=P_TYPE_VOICE;
for(uint16_t p=0; p<100; p++)
@ -1121,11 +1149,46 @@ int main(void)
}*/
//DAC OUT2 (audio) test
for(uint16_t i=0; i<320; i++)
/*for(uint16_t i=0; i<320; i++)
audio_samples[i]=0xFFF*(sin((40.0*i)/320.0*2*3.14159265348)/2.0+0.5);
HAL_DAC_Start_DMA(&hdac, DAC_CHANNEL_1, audio_samples, 320, DAC_ALIGN_12B_R);
AUDIO_Mux(AUDIO_MUX_SPK);
HAL_TIM_Base_Start(&htim6);*/
//ADF7021 test
ADF_WriteReg((uint32_t)0x0003B|((uint32_t)0x3243<<8)); //SWD (0x3B) syncword: 0x3243
HAL_Delay(2-1);
ADF_WriteReg((uint32_t)0x0010C|(uint32_t)1<<8); //DPL (0x10C)
HAL_Delay(2-1);
ADF_WriteReg((uint32_t)0x5770B4); //0x5770B4
HAL_Delay(2-1);
ADF_WriteReg((uint32_t)0x01ED5); //coarse cal ON
HAL_Delay(2-1);
ADF_WriteReg((uint32_t)0x505EBA6|(uint32_t)1<<4); //0x505EBA6
HAL_Delay(10-1);
//((uint32_t)0x007);
//HAL_Delay(2-1);
//ADF_WriteReg((uint32_t)0x0008);
//HAL_Delay(2-1);
ADF_WriteReg((uint32_t)0x9|(uint32_t)40<<4|(uint32_t)70<<11);//|((uint32_t)1<<18)|((uint32_t)2<<20)|((uint32_t)2<<22)); //manual gain - max
HAL_Delay(2-1);
ADF_WriteReg((uint32_t)0x3296556B);
HAL_Delay(2-1);
ADF_WriteReg((uint32_t)0x003BD);
ADF_WriteReg((uint32_t)0x475031);
HAL_Delay(2-1);
//ADF_WriteReg((uint32_t)0x29ECA093); //CDR=40
ADF_WriteReg((uint32_t)(0x29ECA093&(~(0xFF<<10)))|1<<10); //CDR=1 for DAC test
HAL_Delay(2-1);
ADF_SetFreq(460125000, 1); //SR5ND
LNA_Ctrl(LNA_ON);
HAL_TIM_Base_Start(&htim6);
HAL_ADC_Start_DMA(&hadc3, fm_demod_in, 320);
AUDIO_Mux(AUDIO_MUX_SPK);
/* USER CODE END 2 */
@ -1139,9 +1202,14 @@ int main(void)
HAL_Delay(950);*/
if(!dac_play)
{
HAL_DAC_Start_DMA(&hdac, DAC_CHANNEL_1, audio_samples, 320, DAC_ALIGN_12B_R);
if(buff_num)
HAL_DAC_Start_DMA(&hdac, DAC_CHANNEL_1, &fm_demod_in[0], 320, DAC_ALIGN_12B_R);
else
HAL_DAC_Start_DMA(&hdac, DAC_CHANNEL_1, &fm_demod_in[320], 320, DAC_ALIGN_12B_R);
//HAL_DAC_Start_DMA(&hdac, DAC_CHANNEL_1, audio_samples, 320, DAC_ALIGN_12B_R);
dac_play=1;
}
/*HAL_GPIO_WritePin(LED_RED_GPIO_Port, LED_RED_Pin, 0);
HAL_Delay(50);
HAL_GPIO_WritePin(LED_RED_GPIO_Port, LED_RED_Pin, 1);
@ -1326,11 +1394,11 @@ static void MX_ADC3_Init(void)
hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc3.Init.ContinuousConvMode = DISABLE;
hadc3.Init.DiscontinuousConvMode = DISABLE;
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
hadc3.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T6_TRGO;
hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc3.Init.NbrOfConversion = 1;
hadc3.Init.DMAContinuousRequests = DISABLE;
hadc3.Init.DMAContinuousRequests = ENABLE;
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
if (HAL_ADC_Init(&hadc3) != HAL_OK)
{
@ -1865,6 +1933,9 @@ static void MX_DMA_Init(void)
/* DMA2_Stream0_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 9, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
/* DMA2_Stream1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);
/* DMA2_Stream2_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 15, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);

50
cubemx/Src/stm32f7xx_hal_msp.c
View File

@ -52,6 +52,8 @@ extern DMA_HandleTypeDef hdma_adc1;
extern DMA_HandleTypeDef hdma_adc2;
extern DMA_HandleTypeDef hdma_adc3;
extern DMA_HandleTypeDef hdma_dac1;
extern DMA_HandleTypeDef hdma_usart2_tx;
@ -201,6 +203,25 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* ADC3 DMA Init */
/* ADC3 Init */
hdma_adc3.Instance = DMA2_Stream1;
hdma_adc3.Init.Channel = DMA_CHANNEL_2;
hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_adc3.Init.MemInc = DMA_MINC_ENABLE;
hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
hdma_adc3.Init.Mode = DMA_NORMAL;
hdma_adc3.Init.Priority = DMA_PRIORITY_LOW;
hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_adc3) != HAL_OK)
{
_Error_Handler(__FILE__, __LINE__);
}
__HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3);
/* ADC3 interrupt Init */
HAL_NVIC_SetPriority(ADC_IRQn, 15, 0);
HAL_NVIC_EnableIRQ(ADC_IRQn);
@ -285,6 +306,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1);
/* ADC3 DMA DeInit */
HAL_DMA_DeInit(hadc->DMA_Handle);
/* ADC3 interrupt DeInit */
/* USER CODE BEGIN ADC3:ADC_IRQn disable */
/**
@ -409,6 +433,9 @@ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
__HAL_LINKDMA(hdac,DMA_Handle1,hdma_dac1);
/* DAC interrupt Init */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
/* USER CODE BEGIN DAC_MspInit 1 */
/* USER CODE END DAC_MspInit 1 */
@ -435,6 +462,16 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
/* DAC DMA DeInit */
HAL_DMA_DeInit(hdac->DMA_Handle1);
/* DAC interrupt DeInit */
/* USER CODE BEGIN DAC:TIM6_DAC_IRQn disable */
/**
* Uncomment the line below to disable the "TIM6_DAC_IRQn" interrupt
* Be aware, disabling shared interrupt may affect other IPs
*/
/* HAL_NVIC_DisableIRQ(TIM6_DAC_IRQn); */
/* USER CODE END DAC:TIM6_DAC_IRQn disable */
/* USER CODE BEGIN DAC_MspDeInit 1 */
/* USER CODE END DAC_MspDeInit 1 */
@ -789,6 +826,9 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
/* USER CODE END TIM6_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM6_CLK_ENABLE();
/* TIM6 interrupt Init */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
/* USER CODE BEGIN TIM6_MspInit 1 */
/* USER CODE END TIM6_MspInit 1 */
@ -894,6 +934,16 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
/* USER CODE END TIM6_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_TIM6_CLK_DISABLE();
/* TIM6 interrupt DeInit */
/* USER CODE BEGIN TIM6:TIM6_DAC_IRQn disable */
/**
* Uncomment the line below to disable the "TIM6_DAC_IRQn" interrupt
* Be aware, disabling shared interrupt may affect other IPs
*/
/* HAL_NVIC_DisableIRQ(TIM6_DAC_IRQn); */
/* USER CODE END TIM6:TIM6_DAC_IRQn disable */
/* USER CODE BEGIN TIM6_MspDeInit 1 */
/* USER CODE END TIM6_MspDeInit 1 */

32
cubemx/Src/stm32f7xx_it.c
View File

@ -42,11 +42,14 @@
/* External variables --------------------------------------------------------*/
extern DMA_HandleTypeDef hdma_adc1;
extern DMA_HandleTypeDef hdma_adc2;
extern DMA_HandleTypeDef hdma_adc3;
extern ADC_HandleTypeDef hadc1;
extern ADC_HandleTypeDef hadc2;
extern ADC_HandleTypeDef hadc3;
extern DMA_HandleTypeDef hdma_dac1;
extern DAC_HandleTypeDef hdac;
extern TIM_HandleTypeDef htim5;
extern TIM_HandleTypeDef htim6;
extern TIM_HandleTypeDef htim7;
extern DMA_HandleTypeDef hdma_usart2_tx;
extern UART_HandleTypeDef huart2;
@ -302,6 +305,21 @@ void TIM5_IRQHandler(void)
/* USER CODE END TIM5_IRQn 1 */
}
/**
* @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
*/
void TIM6_DAC_IRQHandler(void)
{
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
/* USER CODE END TIM6_DAC_IRQn 0 */
HAL_DAC_IRQHandler(&hdac);
HAL_TIM_IRQHandler(&htim6);
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
/* USER CODE END TIM6_DAC_IRQn 1 */
}
/**
* @brief This function handles TIM7 global interrupt.
*/
@ -330,6 +348,20 @@ void DMA2_Stream0_IRQHandler(void)
/* USER CODE END DMA2_Stream0_IRQn 1 */
}
/**
* @brief This function handles DMA2 stream1 global interrupt.
*/
void DMA2_Stream1_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream1_IRQn 0 */
/* USER CODE END DMA2_Stream1_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_adc3);
/* USER CODE BEGIN DMA2_Stream1_IRQn 1 */
/* USER CODE END DMA2_Stream1_IRQn 1 */
}
/**
* @brief This function handles DMA2 stream2 global interrupt.
*/

51
cubemx/TR-9.ioc
View File

@ -17,10 +17,23 @@ ADC2.NbrOfConversionFlag=1
ADC2.Rank-9\#ChannelRegularConversion=1
ADC2.SamplingTime-9\#ChannelRegularConversion=ADC_SAMPLETIME_480CYCLES
ADC3.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_1
ADC3.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag
ADC3.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV4
ADC3.ContinuousConvMode=DISABLE
ADC3.DMAContinuousRequests=ENABLE
ADC3.DataAlign=ADC_DATAALIGN_RIGHT
ADC3.DiscontinuousConvMode=DISABLE
ADC3.EOCSelection=ADC_EOC_SINGLE_CONV
ADC3.EnableAnalogWatchDog=false
ADC3.ExternalTrigConv=ADC_EXTERNALTRIGCONV_T6_TRGO
ADC3.ExternalTrigConvEdge=ADC_EXTERNALTRIGCONVEDGE_RISING
ADC3.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,ExternalTrigConv,NbrOfConversion,ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,ExternalTrigConvEdge,InjNumberOfConversion,EnableAnalogWatchDog
ADC3.InjNumberOfConversion=0
ADC3.NbrOfConversion=1
ADC3.NbrOfConversionFlag=1
ADC3.Rank-0\#ChannelRegularConversion=1
ADC3.Resolution=ADC_RESOLUTION_12B
ADC3.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
ADC3.ScanConvMode=ADC_SCAN_DISABLE
CRYP.Algorithm=AESCTR
CRYP.DataType=CRYP_DATATYPE_8B
CRYP.IPParameters=Algorithm,DataType,KeySize
@ -48,21 +61,32 @@ Dma.ADC2.1.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
Dma.ADC2.1.PeriphInc=DMA_PINC_DISABLE
Dma.ADC2.1.Priority=DMA_PRIORITY_LOW
Dma.ADC2.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.DAC1.3.Direction=DMA_MEMORY_TO_PERIPH
Dma.DAC1.3.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.DAC1.3.Instance=DMA1_Stream5
Dma.DAC1.3.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
Dma.DAC1.3.MemInc=DMA_MINC_ENABLE
Dma.DAC1.3.Mode=DMA_NORMAL
Dma.DAC1.3.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
Dma.DAC1.3.PeriphInc=DMA_PINC_DISABLE
Dma.DAC1.3.Priority=DMA_PRIORITY_HIGH
Dma.DAC1.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.ADC3.3.Direction=DMA_PERIPH_TO_MEMORY
Dma.ADC3.3.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.ADC3.3.Instance=DMA2_Stream1
Dma.ADC3.3.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
Dma.ADC3.3.MemInc=DMA_MINC_ENABLE
Dma.ADC3.3.Mode=DMA_NORMAL
Dma.ADC3.3.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
Dma.ADC3.3.PeriphInc=DMA_PINC_DISABLE
Dma.ADC3.3.Priority=DMA_PRIORITY_LOW
Dma.ADC3.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.DAC1.4.Direction=DMA_MEMORY_TO_PERIPH
Dma.DAC1.4.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.DAC1.4.Instance=DMA1_Stream5
Dma.DAC1.4.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
Dma.DAC1.4.MemInc=DMA_MINC_ENABLE
Dma.DAC1.4.Mode=DMA_NORMAL
Dma.DAC1.4.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
Dma.DAC1.4.PeriphInc=DMA_PINC_DISABLE
Dma.DAC1.4.Priority=DMA_PRIORITY_HIGH
Dma.DAC1.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.Request0=ADC1
Dma.Request1=ADC2
Dma.Request2=USART2_TX
Dma.Request3=DAC1
Dma.RequestsNb=4
Dma.Request3=ADC3
Dma.Request4=DAC1
Dma.RequestsNb=5
Dma.USART2_TX.2.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART2_TX.2.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART2_TX.2.Instance=DMA1_Stream6
@ -207,6 +231,7 @@ NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.DMA1_Stream5_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.DMA1_Stream6_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.DMA2_Stream0_IRQn=true\:9\:0\:true\:false\:true\:false
NVIC.DMA2_Stream1_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.DMA2_Stream2_IRQn=true\:15\:0\:true\:false\:true\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.EXTI0_IRQn=true\:12\:0\:true\:false\:true\:true