From b5f843fe7ece2b75a783fa785d6c7c6647a7a46d Mon Sep 17 00:00:00 2001
From: Michiiel <94533767+Michiiel@users.noreply.github.com>
Date: Thu, 30 May 2024 15:43:21 +0200
Subject: [PATCH 1109/1135] =?UTF-8?q?fix=20Hsync=20and=20Vsync=20polarity?=
 =?UTF-8?q?=20can't=20change=20from=20negatieve=20to=20positief=20?=
 =?UTF-8?q?=E2=80=A6=20(#6193)?=
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vc4/hdmi: Fix Hsync and Vsync polarity changes

Polarity bits were only ever set and never cleared.
Make sure they can also be cleared.

Signed-off-by: Michiel Vanbiervliet <michiel.vanbiervliet@gmail.com>
---
 drivers/gpu/drm/vc4/vc4_hdmi.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1889,14 +1889,15 @@ static void vc4_hdmi_encoder_post_crtc_e
 	spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 
 	HDMI_WRITE(HDMI_VID_CTL,
-		   HDMI_READ(HDMI_VID_CTL) |
-		   VC4_HD_VID_CTL_ENABLE |
-		   VC4_HD_VID_CTL_CLRRGB |
-		   VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
-		   VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
-		   VC4_HD_VID_CTL_BLANK_INSERT_EN |
-		   (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
-		   (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
+	   (HDMI_READ(HDMI_VID_CTL) &~ 
+	   (VC4_HD_VID_CTL_VSYNC_LOW | VC4_HD_VID_CTL_HSYNC_LOW)) |
+	   VC4_HD_VID_CTL_ENABLE |
+	   VC4_HD_VID_CTL_CLRRGB |
+	   VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
+	   VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
+	   VC4_HD_VID_CTL_BLANK_INSERT_EN |
+	   (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
+	   (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 
 	HDMI_WRITE(HDMI_VID_CTL,
 		   HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
