mirror of https://github.com/openwrt/openwrt.git
realtek: rtl838x: trap slow protocols to the cpu
rteth_838x_set_rx_mode() sets the RMA_CTRL_0 actions to forward, or to
flood with promisc or allmulti. Slow protocol frames
(01-80-C2-00-00-02, e.g. LACP) then reach the CPU only as flooded
frames, and leave the other ports too, which a bridge does not do by
default. b909154ce2 ("realtek: rtl839x: trap slow protocols to the
cpu") traps them on RTL839x.
Do the same on RTL838x: bypass STP and VLAN filtering for them (bits 0
and 9 of RMA_CTRL_1), then always trap them (RMA_02_ACT, bits 3:2 of
RMA_CTRL_0, vendor SDK). OAM PDUs have an action of their own, bits
1:0, and keep it, as do the other RMA addresses.
ZyXEL GS1900-8 A1 (RTL8380M), 5 LACPDUs into lan2, a port of a
VLAN-filtering bridge: on main all 5 reach the CPU and leave lan1 too;
with RMA_02_ACT set to trap by hand on main, all 5 reach the CPU and
none leaves lan1. With this change and the next one the same, and also
with the ports out of a bridge. Not tested: a conduit that is not
promiscuous; eth0 was, and RMA_CTRL_1 was 0x7fff already.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Gennaro Cimmino <gcimmino@rayonra.net>
Link: https://github.com/openwrt/openwrt/pull/26039
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
pull/26039/head
parent
46586cb4d6
commit
1fde9f83dc
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@ -876,6 +876,16 @@ static void rteth_838x_set_rx_mode(struct net_device *dev)
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regmap_write(ctrl->map, RTETH_838X_RMA_CTRL_0, GENMASK(21, 0));
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regmap_write(ctrl->map, RTETH_838X_RMA_CTRL_1, GENMASK(14, 0));
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}
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/*
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* Always trap slow protocols to 01-80-C2-00-00-02 (e.g. LACP, not OAM),
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* past STP and VLAN filtering. Program the bypasses before the trap:
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* bit 0: SLOW_PROTO_BYPASS_STP
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* bit 9: RMA_SLOWPRO_BYPASS_VLAN
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*/
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regmap_set_bits(ctrl->map, RTETH_838X_RMA_CTRL_1, BIT(0) | BIT(9));
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regmap_update_bits(ctrl->map, RTETH_838X_RMA_CTRL_0, GENMASK(3, 2),
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RTETH_838X_RMA_CTRL_0_SLOW_TRAP);
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}
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static void rteth_839x_set_rx_mode(struct net_device *dev)
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@ -26,6 +26,7 @@
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#define RTETH_838X_QM_PKT2CPU_INTPRI_0 (0x5f04)
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#define RTETH_838X_QM_PKT2CPU_INTPRI_CNT 3
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#define RTETH_838X_RMA_CTRL_0 (0x4300)
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#define RTETH_838X_RMA_CTRL_0_SLOW_TRAP (2 << 2)
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#define RTETH_838X_RMA_CTRL_1 (0x4304)
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#define RTETH_838X_TAG1_PROTO_MASK GENMASK(15, 8)
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#define RTETH_838X_TAG1_PROTO 0x04
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