realtek: dsa: rtl930x: drop untagged frames without PVID

e4c5f850ee ("realtek: dsa: drop untagged frames of ports without
PVID") left the other families as they were until tested. RTL930x has
the same bug: a port without PVID in a VLAN-filtering bridge floods its
untagged and priority tagged frames to the other ports of the bridge,
tagged VID 0.

Set vlan_port_aft for RTL930x too. VLAN_PORT_AFT (0x8260 + 4 * port)
has the same four fields as on RTL839x (vendor SDK).
otto_vlan_930x_qinq_setup() writes the register through that field now
instead of a second definition, with the same value. RTL838x and
RTL931x still leave vlan_port_aft unset.

Hasivo S1100W-8XGT-SE (RTL9303), lan2 tagged only in VLAN 3, lan1 an
access port in VLAN 1, one boot each: on main untagged and priority
tagged ARP from the host behind lan2 left lan1 tagged VID 0, 3 of 3
each; now none does. STP, LLDP, LACP and EAPOL frames and VLAN 3 tagged
frames on lan2 still reach the CPU, 5 of 5 each. In an 802.1ad bridge
without PVID, untagged ARP left lan1 with an S-tag VID 0 on main, 3 of
3, and now none does, while S-VLAN pings are answered, 8 of 8. With a
PVID on lan2, and in a bridge without VLAN filtering, the ARP leaves
lan1 untagged; as standalone ports both accept all frames again.

Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Gennaro Cimmino <gcimmino@rayonra.net>
Link: https://github.com/openwrt/openwrt/pull/26026
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
pull/26026/head
Gennaro Cimmino 2026-10-19 20:25:25 +02:00 committed by Markus Stockhausen
parent c2feaf022d
commit 46586cb4d6
2 changed files with 4 additions and 4 deletions

View File

@ -44,6 +44,7 @@
#define RTL930X_MAC_LINK_STS (0xCB10)
#define RTL930X_EEE_CTRL(p) (0x3274 + ((p) << 6))
#define RTL930X_VLAN_PORT_AFT (0x8260)
#define RTL930X_TRK_HASH_CTRL (0x9F80)
#define RTL930X_TRK_CTRL (0x9F88)
@ -630,6 +631,7 @@ const struct rtldsa_config rtldsa_930x_cfg = {
.vlan_profile_get = otto_vlan_930x_profile_get,
.vlan_profile_dump = otto_vlan_930x_profile_dump,
.vlan_profile_setup = otto_vlan_930x_profile_setup,
.vlan_port_aft = RTL930X_VLAN_PORT_AFT,
.vlan_fwd_on_inner = otto_vlan_930x_port_forward_on_inner,
.vlan_qinq_setup = otto_vlan_930x_qinq_setup,
.vlan_port_qinq_set = otto_vlan_930x_port_qinq_set,

View File

@ -109,8 +109,6 @@
#define RTL930X_VLAN_TAG_TPID_CTRL(idx) (0xC7AC + ((idx) << 2))
#define RTL930X_VLAN_PORT_ITAG_TPID_CMP_MSK(port) (0x327C + ((port) << 6))
#define RTL930X_VLAN_PORT_OTAG_TPID_CMP_MSK(port) (0x3280 + ((port) << 6))
#define RTL930X_VLAN_PORT_AFT(port) (0x8260 + ((port) << 2))
#define RTL930X_VLAN_PORT_AFT_ACCEPT_ALL GENMASK(3, 0)
#define RTL930X_VLAN_PORT_EGR_TPID_CTRL(port) (0xCE98 + ((port) << 2))
#define RTL930X_VLAN_PORT_EGR_TPID_OTPID_IDX GENMASK(5, 4)
#define RTL930X_VLAN_PORT_EGR_TPID_OTPID_KEEP BIT(3)
@ -678,8 +676,8 @@ void otto_vlan_930x_qinq_setup(struct otto_dsa_priv *priv)
regmap_write(priv->map, RTL930X_VLAN_PORT_ITAG_TPID_CMP_MSK(port), BIT(0));
regmap_write(priv->map, RTL930X_VLAN_PORT_OTAG_TPID_CMP_MSK(port),
port == cpu_port ? BIT(0) : 0);
regmap_write(priv->map, RTL930X_VLAN_PORT_AFT(port),
RTL930X_VLAN_PORT_AFT_ACCEPT_ALL);
regmap_write(priv->map, priv->r->vlan_port_aft + (port << 2),
RTLDSA_VLAN_PORT_AFT_ALL);
}
regmap_write_bits(priv->map, RTL930X_VLAN_PORT_FWD + (cpu_port << 2), GENMASK(3, 0),