mirror of https://github.com/openwrt/openwrt.git
realtek: Add support for Zyxel XGS1210-12 Switch
The Zyxel XGS1210-12 Switch is a 10 + 2 port multi-GBit switch with 8 x 1000BaseT, 2 x 10/100/1000/2500BaseT Ethernet ports and 2 SFP+ module slot. Hardware: - RTL9302B SoC - Macronix MX25L12833F (16MB flash) - Nanja NT5CC64M16GP-1 (128MB DDR3 SDRAM) - RTL8231 GPIO extender to control the port LEDs - RTL8218D 8x Gigabit PHY - RTL8226 2x 10m/100m/1/2.5 Gigabit PHY - SFP+ 2x 10GBit slot Power is supplied via a 12V 1.5A standard barrel connector. At the right side behind the grid is UART serial connector. A Serial header can be connected to from the outside of the switch trough the airvents with a standard 2.54mm header. Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial connection is via 115200 baud, 8N1. A reset button is accessble through a hole in the front panel At the time of this commit, all ethernet ports work under OpenWrt, including the various NBaseT modes, SFP+ slots are supported with i2c bus. Installation -------------- * Connect serial as per the layout above. Connection parameters: 115200 8N1. * Navigate to 'Management' in the OEM web interface and click on 'Firmware upgrade' to the left. * Upload the OpenWrt initramfs image, and wait till the switch reboots. * Connect to the device through serial and change the U-boot boot command. > fw_setenv bootcmd 'rtk network on; boota' * Reboot, scp the sysupgrade image to /tmp, verify the checksum and flash it: > sysupgrade openwrt-realtek-rtl930x-Zyxel_xgs1210-12-squashfs-sysupgrade.bin * Upon reboot, you have a functional OpenWrt installation. Leave the bootcmd value as is - without 'rtk network on' the switch will fail to initialise the network. Debug ------------ * Connect serial as per the layout above. Connection parameters: 115200 8N1. * A tftp server is requiered, tftpd-hpa works well. * Power the device, at U-Boot start rapidly hit Esc key to stop autoboot * Enable network: > rtk network on * Change ip address (default is 192.168.1.1): > setenv ipaddr 192.168.1.6 * Download initramfs: > tftpboot 0x84f00000 192.168.1.111:openwrt-realtek-rtl930x-Zyxel_xgs1210-12-initramfs-kernel.bin * Boot loaded file: > bootm 0x84f00000 This prodecudre also apply to the sock firmware with the file XGS1210-12_V2.00(ABTY.1)C0.bix. More information can be found on the page of XGS1250-12 as they share the same base. Signed-off-by: Nicolas BERTRAND <nicolasbertrand89@gmail.com> [fixed white space error] Signed-off-by: Paul Spooren <mail@aparcar.org>pull/19021/merge
Nicolas BERTRAND
Paul Spooren
parent
39b9b491bb
commit
6af9476b8a
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@ -0,0 +1,371 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl930x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "zyxel,xgs1210-12", "realtek,rtl838x-soc";
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model = "Zyxel XGS1210-12 Switch";
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aliases {
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led-boot = &led_pwr_sys;
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led-failsafe = &led_pwr_sys;
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led-running = &led_pwr_sys;
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led-upgrade = &led_pwr_sys;
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};
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keys {
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compatible = "gpio-keys";
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mode {
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label = "reset";
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gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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/* i2c of the SFP cage: port 11 & port 12 */
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i2c0: i2c-rtl9300@1b00036c {
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compatible = "realtek,rtl9300-i2c";
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reg = <0x1b00036c 0x3c>;
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#address-cells = <1>;
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#size-cells = <0>;
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sda-pin = <9>;
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scl-pin = <8>;
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clock-frequency = <100000>;
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};
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i2cmux {
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compatible = "realtek,rtl9302-i2c-mux", "realtek,i2c-mux-rtl9300";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-parent = <&i2c0>;
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/* i2c of the left SFP+ cage as seen from the front: port 11 */
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i2c0_0: i2c@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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sda-pin = <9>;
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scl-pin = <8>;
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};
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/* i2c of the right SFP+ cage as seen from the front: port 12 */
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i2c0_1: i2c@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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sda-pin = <10>;
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scl-pin = <8>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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led_pwr_sys: led-0 {
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label = "green:power";
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_POWER;
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gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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};
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};
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sfp0: sfp-p11 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0_0>;
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los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
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};
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sfp1: sfp-p12 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0_1>;
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los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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};
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led_set: led_set {
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compatible = "realtek,rtl9300-leds";
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active-low;
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// LED set 0:
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// Amber: 100M/10M
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// Yellow: 1G
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led_set0 = <0x0a20 0x0b80>;
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// LED set 1:
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// Blue: 2.5G
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// Green: 2.5G
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// Yellow: 1G
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// Amber: 100M/10M
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// (Blue + Green = Cyan)
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led_set1 = <0x0b80 0x0a20 0x0a08 0x0a08>;
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// LED set 2:
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// Blue: 10G/5G/2.5G
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// Yellow: 5G/2.5G/1G
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// (Blue + Yellow = Purple)
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led_set2 = <0x0a2a 0x0a0b>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0xe0000>;
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read-only;
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};
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partition@e0000 {
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label = "u-boot-env";
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reg = <0xe0000 0x10000>;
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};
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partition@f0000 {
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label = "u-boot-env2";
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reg = <0xf0000 0x10000>;
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read-only;
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};
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partition@100000 {
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label = "jffs2-cfg";
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reg = <0x100000 0x100000>;
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};
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partition@200000 {
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label = "jffs2-log";
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reg = <0x200000 0x100000>;
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};
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partition@b300000 {
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label = "firmware";
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reg = <0x300000 0xce0000>;
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compatible = "openwrt,uimage", "denx,uimage";
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openwrt,ih-magic = <0x93001210>;
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};
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partition@fe0000 {
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label = "log";
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reg = <0xfe0000 0x20000>;
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read-only;
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};
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};
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* External RTL8218D PHY */
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phy0: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 0>;
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sds = < 2 >;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 2>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 3>;
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 4>;
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 5>;
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};
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phy6: ethernet-phy@6 {
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reg = <6>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 6>;
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};
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phy7: ethernet-phy@7 {
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reg = <7>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 7>;
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};
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/* External RTL8226 PHYs */
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phy24: ethernet-phy@24 {
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reg = <24>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 8>;
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sds = < 6 >;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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phy25: ethernet-phy@25 {
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reg = <25>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <2 9>;
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sds = < 7 >;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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/* SFP0 Ports */
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phy26: ethernet-phy@26 {
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compatible = "ethernet-phy-ieee802.3-c22";
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phy-is-integrated;
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reg = <26>;
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sds = < 8 >;
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};
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/* SFP1 Ports */
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phy27: ethernet-phy@27 {
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compatible = "ethernet-phy-ieee802.3-c22";
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phy-is-integrated;
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reg = <27>;
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sds = < 9 >;
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};
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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phy-handle = <&phy0>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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phy-handle = <&phy1>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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phy-handle = <&phy2>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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phy-handle = <&phy3>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@4 {
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reg = <4>;
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label = "lan5";
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phy-handle = <&phy4>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@5 {
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reg = <5>;
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label = "lan6";
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phy-handle = <&phy5>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@6 {
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reg = <6>;
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label = "lan7";
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phy-handle = <&phy6>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@7 {
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reg = <7>;
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label = "lan8";
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phy-handle = <&phy7>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@24 {
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reg = <24>;
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label = "lan9";
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phy-mode = "hsgmii";
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phy-handle = <&phy24>;
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led-set = <1>;
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};
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port@25 {
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reg = <25>;
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label = "lan10";
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phy-mode = "hsgmii";
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phy-handle = <&phy25>;
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led-set = <1>;
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};
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port@26 {
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reg = <26>;
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label = "lan11";
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phy-mode = "1000base-x"; //"10gbase-r";
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pseudo-phy-handle = <&phy26>;
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sfp = <&sfp0>;
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led-set = <2>;
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managed = "in-band-status";
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};
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port@27 {
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reg = <27>;
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label = "lan12";
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phy-mode = "1000base-x";
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pseudo-phy-handle = <&phy27>;
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sfp = <&sfp1>;
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led-set = <2>;
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managed = "in-band-status";
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};
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <10000>;
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full-duplex;
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};
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};
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};
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};
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@ -31,6 +31,22 @@ define Device/xikestor_sks8300-8x
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endef
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TARGET_DEVICES += xikestor_sks8300-8x
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define Device/zyxel_xgs1210-12
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SOC := rtl9302
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UIMAGE_MAGIC := 0x93001210
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ZYXEL_VERS := ABTY
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DEVICE_VENDOR := Zyxel
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DEVICE_MODEL := XGS1210-12
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IMAGE_SIZE := 13312k
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KERNEL_INITRAMFS := \
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kernel-bin | \
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append-dtb | \
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gzip | \
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zyxel-vers | \
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uImage gzip
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endef
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TARGET_DEVICES += zyxel_xgs1210-12
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define Device/zyxel_xgs1250-12
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SOC := rtl9302
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UIMAGE_MAGIC := 0x93001250
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