From 934bad3fb9c9ea30c65f57f72924b023934e5ebd Mon Sep 17 00:00:00 2001
From: Jonathan Naylor <naylorjs@yahoo.com>
Date: Tue, 8 Nov 2016 07:41:31 +0000
Subject: [PATCH] More work on the Teensy raw IO.

---
 IOTeensy.cpp | 40 +++++++++++++++++++++++++++++++---------
 1 file changed, 31 insertions(+), 9 deletions(-)

diff --git a/IOTeensy.cpp b/IOTeensy.cpp
index 4655cae..bb58f20 100644
--- a/IOTeensy.cpp
+++ b/IOTeensy.cpp
@@ -48,7 +48,7 @@
 const uint16_t DC_OFFSET = 2048U;
 
 extern "C" {
-  void ADC_Handler()
+  void adc0_isr()
   {
     io.interrupt();
   }
@@ -71,25 +71,47 @@ void CIO::initInt()
 #endif
 }
 
+#define PDB_CH0C1_TOS 0x0100
+#define PDB_CH0C1_EN  0x01
+
 void CIO::startInt()
 {
+  // Initialise ADC0 conversion to be triggered by the PDB
+  ADC0_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | ADC_CFG1_MODE(1) |
+              ADC_CFG1_ADLSMP;                                        // Single-ended 12 bits, long sample time
+  ADC0_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2);                   // Select channels ADxxxb
+  ADC0_SC2  = ADC_SC2_REFSEL(1) | ADC_SC2_ADTRG;                      // Voltage ref internal, hardware trigger
+  ADC0_SC3  = ADC_SC3_AVGE | ADC_SC3_AVGS(0);                         // Enable averaging, 4 samples
+  ADC0_SC1A = ADC_SC1_AIEN | 5;                                       // Enable ADC interrupt, use A0
+  NVIC_ENABLE_IRQ(IRQ_ADC0);
+
+  // Setup PDB for ADC0 at 24 kHz
+  SIM_SCGC6 |= SIM_SCGC6_PDB;                                         // Enable PDB clock
+#if F_BUS == 60000000
+  // 60 MHz for the Teensy 3.5/3.6
+  PDB0_MOD   = 2500;                                                  // Timer period for 60 MHz bus
+#else
+  // 48 MHz for the Teensy 3.1/3.2
+  PDB0_MOD   = 2000;                                                  // Timer period for 48 MHz bus
+#endif
+  PDB0_IDLY  = 0;                                                     // Interrupt delay
+  PDB0_CH0C1 = PDB_CH0C1_TOS | PDB_CH0C1_EN;                          // Enable pre-trigger
+  PDB0_SC    = PDB_SC_TRGSEL(15) | PDB_SC_PDBEN | PDB_SC_PDBIE |
+               PDB_SC_CONT | PDB_SC_PRESCALER(7) | PDB_SC_MULT(1) |
+               PDB_SC_LDOK;
+  PDB0_SC   |= PDB_SC_SWTRIG;                                         // Software trigger (reset and restart counter)
+
+#if defined(SEND_RSSI_DATA)
   // Initialise ADC1 conversion to be triggered by the PDB
 
   // Setup interrupt on ADC1 conversion finished
 
   // Setup PDB for ADC1 at 24 kHz
-
-#if defined(SEND_RSSI_DATA)
-  // Initialise ADC2 conversion to be triggered by the PDB
-
-  // Setup interrupt on ADC2 conversion finished
-
-  // Setup PDB for ADC2 at 24 kHz
 #endif
 
   // Initialise the DAC
   SIM_SCGC2 |= SIM_SCGC2_DAC0;
-  DAC0_C0    = DAC_C0_DACEN;                   // 1.2V VDDA is DACREF_2
+  DAC0_C0    = DAC_C0_DACEN | DAC_C0_DACRFS;           // 1.2V VDDA is DACREF_2
 
   digitalWrite(PIN_PTT, m_pttInvert ? HIGH : LOW);
   digitalWrite(PIN_COSLED, LOW);