mirror of https://github.com/markqvist/MMDVM.git
External TCXO support for STM32F4 and Nucleo 446 board support
Andy CA6JAU
parent
eacabfb184
commit
b8febb517f
79
IOSTM.cpp
79
IOSTM.cpp
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@ -141,13 +141,72 @@ EXT_CLK PA15 input
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#define PIN_RSSI GPIO_Pin_7
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#define PIN_RSSI_CH ADC_Channel_7
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#else
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#error "Either STM32F4_DISCOVERY or STM32F4_PI need to be defined"
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#endif
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#elif defined(STM32F4_NUCLEO)
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/*
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Pin definitions for STM32F4 Nucleo boards:
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PTT PB13 output
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COSLED PB14 output
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LED PA5 output
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COS PB15 input
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DSTAR PB10 output
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DMR PB4 output
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YSF PB5 output
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P25 PB3 output
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RX PA0 analog input
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RSSI PA1 analog input
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TX PA4 analog output
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EXT_CLK PA15 input
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*/
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#define PIN_COS GPIO_Pin_15
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#define PORT_COS GPIOB
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#define RCC_Per_COS RCC_AHB1Periph_GPIOB
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#define PIN_PTT GPIO_Pin_13
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#define PORT_PTT GPIOB
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#define RCC_Per_PTT RCC_AHB1Periph_GPIOB
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#define PIN_COSLED GPIO_Pin_14
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#define PORT_COSLED GPIOB
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#define RCC_Per_COSLED RCC_AHB1Periph_GPIOB
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#define PIN_LED GPIO_Pin_5
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#define PORT_LED GPIOA
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#define RCC_Per_LED RCC_AHB1Periph_GPIOA
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#define PIN_P25 GPIO_Pin_3
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#define PORT_P25 GPIOB
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#define RCC_Per_P25 RCC_AHB1Periph_GPIOB
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#define PIN_DSTAR GPIO_Pin_10
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#define PORT_DSTAR GPIOB
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#define RCC_Per_DSTAR RCC_AHB1Periph_GPIOB
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#define PIN_DMR GPIO_Pin_4
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#define PORT_DMR GPIOB
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#define RCC_Per_DMR RCC_AHB1Periph_GPIOB
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#define PIN_YSF GPIO_Pin_5
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#define PORT_YSF GPIOB
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#define RCC_Per_YSF RCC_AHB1Periph_GPIOB
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#define PIN_RX GPIO_Pin_0
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#define PIN_RX_CH ADC_Channel_0
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#define PIN_RSSI GPIO_Pin_1
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#define PIN_RSSI_CH ADC_Channel_1
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#else
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#error "Either STM32F4_DISCOVERY, STM32F4_PI or STM32F4_NUCLEO need to be defined"
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#endif
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const uint16_t DC_OFFSET = 2048U;
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// Sampling frequency
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#define SAMP_FREQ 24000
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extern "C" {
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@ -312,6 +371,7 @@ void CIO::startInt()
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DAC_Cmd(DAC_Channel_1, ENABLE);
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// Init the timer
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
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#if defined(EXTERNAL_OSC)
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// Configure GPIO PA15 as external TIM2 clock source
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@ -321,14 +381,12 @@ void CIO::startInt()
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GPIO_Init(GPIOA, &GPIO_InitStruct);
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#endif
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
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TIM_TimeBaseInitTypeDef timerInitStructure;
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TIM_TimeBaseStructInit (&timerInitStructure);
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// TIM2 frequency
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// TIM2 output frequency
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#if defined(EXTERNAL_OSC)
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timerInitStructure.TIM_Prescaler = (uint16_t) ((EXTERNAL_OSC/SAMP_FREQ) - 1);
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timerInitStructure.TIM_Prescaler = (uint16_t) ((EXTERNAL_OSC/(2*SAMP_FREQ)) - 1);
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#else
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timerInitStructure.TIM_Prescaler = (uint16_t) ((SystemCoreClock/(4*SAMP_FREQ)) - 1);
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#endif
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@ -339,12 +397,17 @@ void CIO::startInt()
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timerInitStructure.TIM_RepetitionCounter = 0;
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TIM_TimeBaseInit(TIM2, &timerInitStructure);
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// Enable external clock
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#if defined(EXTERNAL_OSC)
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// Enable external clock (PA15)
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TIM_ETRClockMode2Config(TIM2, TIM_ExtTRGPSC_OFF, TIM_ExtTRGPolarity_NonInverted, 0x00);
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#else
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// Enable internal clock
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TIM_InternalClockConfig(TIM2);
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#endif
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// Enable TIM2
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TIM_Cmd(TIM2, ENABLE);
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// Enable TIM2 interrupt
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TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
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NVIC_InitTypeDef nvicStructure;
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12
Makefile
12
Makefile
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@ -87,7 +87,10 @@ MCFLAGS=-mcpu=cortex-m4 -mthumb -mlittle-endian \
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# STM32F4 Discovery board:
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DEFS_DIS=-DUSE_STDPERIPH_DRIVER -DSTM32F4XX -DSTM32F40_41xxx -DSTM32F4_DISCOVERY -DHSE_VALUE=$(OSC)
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# Pi board:
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DEFS_PI=-DUSE_STDPERIPH_DRIVER -DSTM32F4XX -DSTM32F446xx -DSTM32F4_PI -DHSE_VALUE=$(OSC)
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DEFS_PI=-DUSE_STDPERIPH_DRIVER -DSTM32F4XX -DSTM32F446xx -DSTM32F4_PI -DARDUINO_MODE_PINS -DSEND_RSSI_DATA -DSERIAL_REPEATER -DHSE_VALUE=$(OSC)
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# STM32F4 Nucleo 446 board:
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DEFS_NUCLEO=-DUSE_STDPERIPH_DRIVER -DSTM32F4XX -DSTM32F446xx -DSTM32F4_NUCLEO -DHSE_VALUE=$(OSC)
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CFLAGS=-c $(MCFLAGS) $(INCLUDES)
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CXXFLAGS=-c $(MCFLAGS) $(INCLUDES)
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@ -96,7 +99,7 @@ LDSCRIPT=stm32f4xx_link.ld
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LDFLAGS =-T $(LDSCRIPT) $(MCFLAGS) --specs=nosys.specs $(INCLUDES_LIBS) $(LINK_LIBS)
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# Build Rules
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.PHONY: all release dis pi debug clean
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.PHONY: all release dis pi nucleo debug clean
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# Default target: STM32F4 Discovery board
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all: dis
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@ -106,6 +109,11 @@ pi: CXXFLAGS+=$(DEFS_PI) -Os -fno-exceptions -ffunction-sections -fdata-sections
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pi: LDFLAGS+=-Os --specs=nano.specs
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pi: release
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nucleo: CFLAGS+=$(DEFS_NUCLEO) -Os -ffunction-sections -fdata-sections -fno-builtin -Wno-implicit -DCUSTOM_NEW -DNO_EXCEPTIONS
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nucleo: CXXFLAGS+=$(DEFS_NUCLEO) -Os -fno-exceptions -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -DCUSTOM_NEW -DNO_EXCEPTIONS
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nucleo: LDFLAGS+=-Os --specs=nano.specs
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nucleo: release
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dis: CFLAGS+=$(DEFS_DIS) -Os -ffunction-sections -fdata-sections -fno-builtin -Wno-implicit -DCUSTOM_NEW -DNO_EXCEPTIONS
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dis: CXXFLAGS+=$(DEFS_DIS) -Os -fno-exceptions -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -DCUSTOM_NEW -DNO_EXCEPTIONS
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dis: LDFLAGS+=-Os --specs=nano.specs
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255
SerialSTM.cpp
255
SerialSTM.cpp
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@ -22,35 +22,39 @@
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#include "SerialPort.h"
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#if defined(STM32F4XX) || defined(STM32F4)
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/*
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Pin definitions:
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volatile uint32_t intcount1, intcount3, intcount5;
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- Host communication:
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USART1 - TXD PA9 - RXD PA10 (Pi board)
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USART2 - TXD PA2 - RXD PA3 (Nucleo board)
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USART3 - TXD PC10 - RXD PC11 (Discovery board)
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- Serial repeater:
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UART5 - TXD PC12 - RXD PD2
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*/
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#if defined(STM32F4XX) || defined(STM32F4)
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#define TX_SERIAL_FIFO_SIZE 256U
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#define RX_SERIAL_FIFO_SIZE 256U
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volatile uint8_t TXSerialfifo1[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo1[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead1, TXSerialfifotail1;
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volatile uint16_t RXSerialfifohead1, RXSerialfifotail1;
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volatile uint8_t TXSerialfifo3[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo3[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead3, TXSerialfifotail3;
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volatile uint16_t RXSerialfifohead3, RXSerialfifotail3;
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volatile uint8_t TXSerialfifo5[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo5[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead5, TXSerialfifotail5;
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volatile uint16_t RXSerialfifohead5, RXSerialfifotail5;
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extern "C" {
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void USART1_IRQHandler();
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void USART2_IRQHandler();
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void USART3_IRQHandler();
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void UART5_IRQHandler();
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}
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/* ************* USART1 ***************** */
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#if defined(STM32F4_PI)
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volatile uint32_t intcount1;
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volatile uint8_t TXSerialfifo1[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo1[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead1, TXSerialfifotail1;
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volatile uint16_t RXSerialfifohead1, RXSerialfifotail1;
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// Init queues
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void TXSerialfifoinit1()
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@ -229,7 +233,204 @@ void WriteUSART1(const uint8_t* data, uint16_t length)
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USART_ITConfig(USART1, USART_IT_TXE, ENABLE);
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}
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#endif
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/* ************* USART2 ***************** */
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#if defined(STM32F4_NUCLEO)
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volatile uint32_t intcount2;
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volatile uint8_t TXSerialfifo2[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo2[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead2, TXSerialfifotail2;
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volatile uint16_t RXSerialfifohead2, RXSerialfifotail2;
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// Init queues
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void TXSerialfifoinit2()
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{
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TXSerialfifohead2 = 0U;
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TXSerialfifotail2 = 0U;
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}
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void RXSerialfifoinit2()
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{
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RXSerialfifohead2 = 0U;
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RXSerialfifotail2 = 0U;
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}
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// How full is queue
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// TODO decide if how full or how empty is preferred info to return
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uint16_t TXSerialfifolevel2()
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{
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uint32_t tail = TXSerialfifotail2;
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uint32_t head = TXSerialfifohead2;
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if (tail > head)
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return TX_SERIAL_FIFO_SIZE + head - tail;
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else
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return head - tail;
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}
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uint16_t RXSerialfifolevel2()
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{
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uint32_t tail = RXSerialfifotail2;
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uint32_t head = RXSerialfifohead2;
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if (tail > head)
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return RX_SERIAL_FIFO_SIZE + head - tail;
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else
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return head - tail;
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}
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// Flushes the transmit shift register
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// warning: this call is blocking
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void TXSerialFlush2()
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{
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// wait until the TXE shows the shift register is empty
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while (USART_GetITStatus(USART2, USART_FLAG_TXE))
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;
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}
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uint8_t TXSerialfifoput2(uint8_t next)
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{
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if (TXSerialfifolevel2() < TX_SERIAL_FIFO_SIZE) {
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TXSerialfifo2[TXSerialfifohead2] = next;
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TXSerialfifohead2++;
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if (TXSerialfifohead2 >= TX_SERIAL_FIFO_SIZE)
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TXSerialfifohead2 = 0U;
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// make sure transmit interrupts are enabled as long as there is data to send
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USART_ITConfig(USART2, USART_IT_TXE, ENABLE);
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return 1U;
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} else {
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return 0U; // signal an overflow occurred by returning a zero count
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}
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}
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void USART2_IRQHandler()
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{
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uint8_t c;
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if (USART_GetITStatus(USART2, USART_IT_RXNE)) {
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c = (uint8_t) USART_ReceiveData(USART2);
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if (RXSerialfifolevel2() < RX_SERIAL_FIFO_SIZE) {
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RXSerialfifo2[RXSerialfifohead2] = c;
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RXSerialfifohead2++;
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if (RXSerialfifohead2 >= RX_SERIAL_FIFO_SIZE)
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RXSerialfifohead2 = 0U;
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} else {
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// TODO - do something if rx fifo is full?
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}
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USART_ClearITPendingBit(USART2, USART_IT_RXNE);
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intcount2++;
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}
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if (USART_GetITStatus(USART2, USART_IT_TXE)) {
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c = 0U;
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if (TXSerialfifohead2 != TXSerialfifotail2) { // if the fifo is not empty
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c = TXSerialfifo2[TXSerialfifotail2];
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TXSerialfifotail2++;
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if (TXSerialfifotail2 >= TX_SERIAL_FIFO_SIZE)
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TXSerialfifotail2 = 0U;
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USART_SendData(USART2, c);
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} else { // if there's no more data to transmit then turn off TX interrupts
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USART_ITConfig(USART2, USART_IT_TXE, DISABLE);
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}
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USART_ClearITPendingBit(USART2, USART_IT_TXE);
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}
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}
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void InitUSART2(int speed)
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{
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// USART2 - TXD PA2 - RXD PA3
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GPIO_InitTypeDef GPIO_InitStructure;
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USART_InitTypeDef USART_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_USART2);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_USART2);
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// USART IRQ init
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NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
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NVIC_Init(&NVIC_InitStructure);
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// Configure USART as alternate function
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GPIO_StructInit(&GPIO_InitStructure);
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3; // Tx | Rx
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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// Configure USART baud rate
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USART_StructInit(&USART_InitStructure);
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USART_InitStructure.USART_BaudRate = speed;
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USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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USART_InitStructure.USART_StopBits = USART_StopBits_1;
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USART_InitStructure.USART_Parity = USART_Parity_No;
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USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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USART_Init(USART2, &USART_InitStructure);
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USART_Cmd(USART2, ENABLE);
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USART_ITConfig(USART2, USART_IT_RXNE, ENABLE);
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// initialize the fifos
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TXSerialfifoinit2();
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RXSerialfifoinit2();
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}
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uint8_t AvailUSART2(void)
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{
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if (RXSerialfifolevel2() > 0U)
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return 1U;
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else
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return 0U;
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}
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uint8_t ReadUSART2(void)
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{
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uint8_t data_c = RXSerialfifo2[RXSerialfifotail2];
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RXSerialfifotail2++;
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if (RXSerialfifotail2 >= RX_SERIAL_FIFO_SIZE)
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RXSerialfifotail2 = 0U;
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return data_c;
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}
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void WriteUSART2(const uint8_t* data, uint16_t length)
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{
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for (uint16_t i = 0U; i < length; i++)
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TXSerialfifoput2(data[i]);
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USART_ITConfig(USART2, USART_IT_TXE, ENABLE);
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}
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#endif
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/* ************* USART3 ***************** */
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#if defined(STM32F4_DISCOVERY) || defined(STM32F4_PI)
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volatile uint32_t intcount3;
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volatile uint8_t TXSerialfifo3[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo3[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead3, TXSerialfifotail3;
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volatile uint16_t RXSerialfifohead3, RXSerialfifotail3;
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// Init queues
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void TXSerialfifoinit3()
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@ -408,8 +609,16 @@ void WriteUSART3(const uint8_t* data, uint16_t length)
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USART_ITConfig(USART3, USART_IT_TXE, ENABLE);
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}
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#endif
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/* ************* UART5 ***************** */
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volatile uint32_t intcount5;
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volatile uint8_t TXSerialfifo5[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo5[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead5, TXSerialfifotail5;
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volatile uint16_t RXSerialfifohead5, RXSerialfifotail5;
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// Init queues
|
||||
void TXSerialfifoinit5()
|
||||
{
|
||||
|
|
@ -515,7 +724,7 @@ void UART5_IRQHandler()
|
|||
|
||||
void InitUART5(int speed)
|
||||
{
|
||||
// USART5 - TXD PC12 - RXD PD2
|
||||
// UART5 - TXD PC12 - RXD PD2
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
|
@ -601,6 +810,8 @@ void CSerialPort::beginInt(uint8_t n, int speed)
|
|||
InitUSART3(speed);
|
||||
#elif defined(STM32F4_PI)
|
||||
InitUSART1(speed);
|
||||
#elif defined(STM32F4_NUCLEO)
|
||||
InitUSART2(speed);
|
||||
#endif
|
||||
break;
|
||||
case 3U:
|
||||
|
|
@ -619,6 +830,8 @@ int CSerialPort::availableInt(uint8_t n)
|
|||
return AvailUSART3();
|
||||
#elif defined(STM32F4_PI)
|
||||
return AvailUSART1();
|
||||
#elif defined(STM32F4_NUCLEO)
|
||||
return AvailUSART2();
|
||||
#endif
|
||||
case 3U:
|
||||
return AvailUART5();
|
||||
|
|
@ -635,6 +848,8 @@ uint8_t CSerialPort::readInt(uint8_t n)
|
|||
return ReadUSART3();
|
||||
#elif defined(STM32F4_PI)
|
||||
return ReadUSART1();
|
||||
#elif defined(STM32F4_NUCLEO)
|
||||
return ReadUSART2();
|
||||
#endif
|
||||
case 3U:
|
||||
return ReadUART5();
|
||||
|
|
@ -655,6 +870,10 @@ void CSerialPort::writeInt(uint8_t n, const uint8_t* data, uint16_t length, bool
|
|||
WriteUSART1(data, length);
|
||||
if (flush)
|
||||
TXSerialFlush1();
|
||||
#elif defined(STM32F4_NUCLEO)
|
||||
WriteUSART2(data, length);
|
||||
if (flush)
|
||||
TXSerialFlush2();
|
||||
#endif
|
||||
break;
|
||||
case 3U:
|
||||
|
|
|
|||
Loading…
Reference in New Issue