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Clean up the DMR Idle RX.

48kHz
Jonathan Naylor 2016-04-04 19:22:04 +01:00
parent b155e72c54
commit bbf8b0dbbc
1 changed files with 9 additions and 8 deletions
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17
DMRIdleRX.cpp
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@ -33,12 +33,17 @@ const uint8_t BIT_MASK_TABLE[] = {0x80U, 0x40U, 0x20U, 0x10U, 0x08U, 0x04U, 0x02
#define WRITE_BIT1(p,i,b) p[(i)>>3] = (b) ? (p[(i)>>3] | BIT_MASK_TABLE[(i)&7]) : (p[(i)>>3] & ~BIT_MASK_TABLE[(i)&7])
const uint16_t NOENDPTR = 9999U;
const uint8_t CONTROL_IDLE = 0x80U;
const uint8_t CONTROL_DATA = 0x40U;
CDMRIdleRX::CDMRIdleRX() :
m_bitBuffer(),
m_buffer(),
m_bitPtr(0U),
m_dataPtr(0U),
m_endPtr(999U),
m_endPtr(NOENDPTR),
m_maxCorr(0),
m_centre(0),
m_threshold(0),
@ -53,7 +58,7 @@ void CDMRIdleRX::reset()
m_maxCorr = 0;
m_threshold = 0;
m_centre = 0;
m_endPtr = 999U;
m_endPtr = NOENDPTR;
}
void CDMRIdleRX::samples(const q15_t* samples, uint8_t length)
@ -140,15 +145,11 @@ void CDMRIdleRX::processSample(q15_t sample)
slotType.decode(frame + 1U, colorCode, dataType);
if (colorCode == m_colorCode && dataType == DT_CSBK) {
frame[0U] = 0x80U | 0x40U | DT_CSBK; // Idle RX, Data Sync, CSBK
frame[0U] = CONTROL_IDLE | CONTROL_DATA | DT_CSBK;
serial.writeDMRData(false, frame, DMR_FRAME_LENGTH_BYTES + 1U);
#if defined(WANT_DEBUG)
} else {
DEBUG5("DMRIdleRX: invalid color code or data type", colorCode, m_colorCode, dataType, DT_CSBK);
#endif
}
m_endPtr = 999U;
m_endPtr = NOENDPTR;
m_maxCorr = 0U;
}