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Fix Teensy SIM_SOPT7 loading.

48kHz
Jonathan Naylor 2016-11-16 09:11:55 +00:00 committed by GitHub
parent cd6593a33b
commit c69933b48d
1 changed files with 14 additions and 8 deletions
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22
IOTeensy.cpp
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@ -85,8 +85,8 @@ void CIO::startInt()
// Initialise ADC0
SIM_SCGC6 |= SIM_SCGC6_ADC0;
ADC0_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | ADC_CFG1_MODE(1) |
ADC_CFG1_ADLSMP; // Single-ended 12 bits, long sample time
ADC0_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time
ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP;
ADC0_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb
ADC0_SC2 = ADC_SC2_REFSEL(1) | ADC_SC2_ADTRG; // Voltage ref internal, hardware trigger
ADC0_SC3 = ADC_SC3_CAL | ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples
@ -94,7 +94,8 @@ void CIO::startInt()
while ((ADC0_SC3 & ADC_SC3_CAL) == ADC_SC3_CAL) // Wait for calibration
;
uint16_t sum0 = ADC0_CLPS + ADC0_CLP4 + ADC0_CLP3 + ADC0_CLP2 + ADC0_CLP1 + ADC0_CLP0; // Plus side gain
uint16_t sum0 = ADC0_CLPS + ADC0_CLP4 + ADC0_CLP3 + // Plus side gain
ADC0_CLP2 + ADC0_CLP1 + ADC0_CLP0;
sum0 = (sum0 / 2U) | 0x8000U;
ADC0_PG = sum0;
@ -104,8 +105,8 @@ void CIO::startInt()
#if defined(SEND_RSSI_DATA)
// Initialise ADC1
SIM_SCGC3 |= SIM_SCGC3_ADC1;
ADC1_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | ADC_CFG1_MODE(1) |
ADC_CFG1_ADLSMP; // Single-ended 12 bits, long sample time
ADC1_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time
ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP;
ADC1_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb
ADC1_SC2 = ADC_SC2_REFSEL(1) | ADC_SC2_ADTRG; // Voltage ref internal, hardware trigger
ADC1_SC3 = ADC_SC3_CAL | ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples
@ -113,7 +114,8 @@ void CIO::startInt()
while ((ADC1_SC3 & ADC_SC3_CAL) == ADC_SC3_CAL) // Wait for calibration
;
uint16_t sum1 = ADC1_CLPS + ADC1_CLP4 + ADC1_CLP3 + ADC1_CLP2 + ADC1_CLP1 + ADC1_CLP0; // Plus side gain
uint16_t sum1 = ADC1_CLPS + ADC1_CLP4 + ADC1_CLP3 + // Plus side gain
ADC1_CLP2 + ADC1_CLP1 + ADC1_CLP0;
sum1 = (sum1 / 2U) | 0x8000U;
ADC1_PG = sum1;
@ -132,10 +134,14 @@ void CIO::startInt()
CORE_PIN13_CONFIG = PORT_PCR_MUX(3);
// Set ADC0 to trigger from the LPTMR
SIM_SOPT7 = SIM_SOPT7_ADC0ALTTRGEN | SIM_SOPT7_ADC0TRGSEL(14);
SIM_SOPT7 |= SIM_SOPT7_ADC0ALTTRGEN |
!SIM_SOPT7_ADC0PRETRGSEL |
SIM_SOPT7_ADC0TRGSEL(14);
#if defined(SEND_RSSI_DATA)
// Set ADC1 to trigger from the LPTMR
SIM_SOPT7 |= SIM_SOPT7_ADC1ALTTRGEN | SIM_SOPT7_ADC1TRGSEL(14);
SIM_SOPT7 |= SIM_SOPT7_ADC1ALTTRGEN |
!SIM_SOPT7_ADC1PRETRGSEL |
SIM_SOPT7_ADC1TRGSEL(14);
#endif
NVIC_ENABLE_IRQ(IRQ_LPTMR);
#else