mirror of https://github.com/markqvist/MMDVM.git
Added STM32F1 and mmdvm_pog board support to IO module using CMSIS driver
Wojciech Krutnik
parent
5bc21fa192
commit
fd56870d22
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@ -0,0 +1,378 @@
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/*
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* Copyright (C) 2016 by Jim McLaughlin KI6ZUM
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* Copyright (C) 2016, 2017 by Andy Uribe CA6JAU
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* Copyright (C) 2017 by Jonathan Naylor G4KLX
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* Copyright (C) 2017 by Wojciech Krutnik N0CALL
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "Config.h"
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#include "Globals.h"
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#include "IO.h"
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#if defined(STM32F1)
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#if defined(STM32F1_POG)
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/*
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Pin definitions for STM32F1 POG Board:
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PTT PB12 output
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COSLED PB5 output
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LED PB4 output
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COS PB13 input/PD
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DSTAR PB7 output
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DMR PB6 output
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YSF PB8 output
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P25 PB9 output
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RX PB0 analog input (ADC1_8)
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RSSI PB1 analog input (ADC2_9)
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TX PA4 analog output (DAC_OUT1)
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EXT_CLK PA15 input (AF: TIM2_CH1_ETR)
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USART2_TXD PA2 output (AF)
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USART2_RXD PA3 input (AF)
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*/
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#define PIN_PTT 12
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#define PORT_PTT GPIOB
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#define BB_PTT *((bitband_t)BITBAND_PERIPH(&PORT_PTT->ODR, PIN_PTT))
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#define PIN_COSLED 5
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#define PORT_COSLED GPIOB
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#define BB_COSLED *((bitband_t)BITBAND_PERIPH(&PORT_COSLED->ODR, PIN_COSLED))
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#define PIN_LED 4
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#define PORT_LED GPIOB
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#define BB_LED *((bitband_t)BITBAND_PERIPH(&PORT_LED->ODR, PIN_LED))
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#define PIN_COS 13
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#define PORT_COS GPIOB
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#define BB_COS *((bitband_t)BITBAND_PERIPH(&PORT_COS->IDR, PIN_COS))
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#define PIN_DSTAR 7
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#define PORT_DSTAR GPIOB
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#define BB_DSTAR *((bitband_t)BITBAND_PERIPH(&PORT_DSTAR->ODR, PIN_DSTAR))
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#define PIN_DMR 6
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#define PORT_DMR GPIOB
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#define BB_DMR *((bitband_t)BITBAND_PERIPH(&PORT_DMR->ODR, PIN_DMR))
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#define PIN_YSF 8
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#define PORT_YSF GPIOB
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#define BB_YSF *((bitband_t)BITBAND_PERIPH(&PORT_YSF->ODR, PIN_YSF))
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#define PIN_P25 9
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#define PORT_P25 GPIOB
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#define BB_P25 *((bitband_t)BITBAND_PERIPH(&PORT_P25->ODR, PIN_P25))
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#define PIN_RX 0
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#define PIN_RX_ADC_CH 8
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#define PORT_RX GPIOB
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#define PIN_RSSI 1
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#define PIN_RSSI_ADC_CH 9
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#define PORT_RSSI GPIOB
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#define PIN_TX 4
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#define PIN_TX_DAC_CH 1
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#define PORT_TX GPIOA
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#define PIN_EXT_CLK 15
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#define SRC_EXT_CLK 15
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#define PORT_EXT_CLK GPIOA
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#define PIN_USART2_TXD 2
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#define PORT_USART2_TXD GPIOA
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#define PIN_USART2_RXD 3
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#define PORT_USART2_RXD GPIOA
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#else // defined(STM32F1_POG)
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#error "Either STM32F1_POG, or sth need to be defined"
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#endif // defined(STM32F1_POG)
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const uint16_t DC_OFFSET = 2048U;
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// Sampling frequency
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#define SAMP_FREQ 24000
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extern "C" {
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void TIM2_IRQHandler() {
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if ((TIM2->SR & TIM_SR_UIF) == TIM_SR_UIF) {
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TIM2->SR = ~TIM_SR_UIF; // clear UI flag
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io.interrupt();
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}
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}
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}
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void delay(uint32_t cnt)
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{
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while(cnt--)
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asm("nop");
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}
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// source: http://www.freddiechopin.info/
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void GPIOConfigPin(GPIO_TypeDef *port_ptr, uint32_t pin, uint32_t mode_cnf_value)
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{
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volatile uint32_t *cr_ptr;
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uint32_t cr_value;
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cr_ptr = &port_ptr->CRL; // configuration of pins [0,7] is in CRL
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if (pin >= 8) // is pin in [8; 15]?
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{ // configuration of pins [8,15] is in CRH
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cr_ptr++; // advance to next struct element CRL -> CRH
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pin -= 8; // crop the pin number
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}
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cr_value = *cr_ptr; // localize the CRL / CRH value
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cr_value &= ~(0xF << (pin * 4)); // clear the MODE and CNF fields (now that pin is an analog input)
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cr_value |= (mode_cnf_value << (pin * 4)); // save new MODE and CNF value for desired pin
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*cr_ptr = cr_value; // save localized value to CRL / CRL
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}
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static inline void GPIOInit()
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{
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RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN
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| RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN
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| RCC_APB2ENR_AFIOEN; // enable all GPIOs
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// set all ports to input with pull-down
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GPIOA->CRL = 0x88888888;
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GPIOA->CRH = 0x88888888;
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GPIOA->ODR = 0;
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GPIOB->CRL = 0x88888888;
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GPIOB->CRH = 0x88888888;
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GPIOB->ODR = 0;
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GPIOC->CRL = 0x88888888;
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GPIOC->CRH = 0x88888888;
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GPIOC->ODR = 0;
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GPIOD->CRL = 0x88888888;
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GPIOD->CRH = 0x88888888;
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GPIOD->ODR = 0;
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// configure ports
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GPIOConfigPin(PORT_PTT, PIN_PTT, GPIO_CRL_MODE0_1);
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GPIOConfigPin(PORT_COSLED, PIN_COSLED, GPIO_CRL_MODE0_1);
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GPIOConfigPin(PORT_LED, PIN_LED, GPIO_CRL_MODE0_1);
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GPIOConfigPin(PORT_COS, PIN_COS, GPIO_CRL_CNF0_1);
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GPIOConfigPin(PORT_DSTAR, PIN_DSTAR, GPIO_CRL_MODE0_1);
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GPIOConfigPin(PORT_DMR, PIN_DMR, GPIO_CRL_MODE0_1);
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GPIOConfigPin(PORT_YSF, PIN_YSF, GPIO_CRL_MODE0_1);
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GPIOConfigPin(PORT_P25, PIN_P25, GPIO_CRL_MODE0_1);
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GPIOConfigPin(PORT_RX, PIN_RX, 0);
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#if defined(SEND_RSSI_DATA)
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GPIOConfigPin(PORT_RSSI, PIN_RSSI, 0);
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#endif
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GPIOConfigPin(PORT_TX, PIN_TX, 0);
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#if defined(EXTERNAL_OSC)
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#if defined(STM32F1_POG)
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GPIOConfigPin(PORT_EXT_CLK, PIN_EXT_CLK, GPIO_CRL_CNF0_0);
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AFIO->MAPR = (AFIO->MAPR & ~AFIO_MAPR_TIM2_REMAP) | AFIO_MAPR_TIM2_REMAP_0;
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#endif
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#endif
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GPIOConfigPin(PORT_USART2_TXD, PIN_USART2_TXD, GPIO_CRL_MODE0_1|GPIO_CRL_CNF0_1);
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GPIOConfigPin(PORT_USART2_RXD, PIN_USART2_RXD, GPIO_CRL_CNF0_0);
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AFIO->MAPR = (AFIO->MAPR & ~AFIO_MAPR_SWJ_CFG) | AFIO_MAPR_SWJ_CFG_1;
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}
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static inline void ADCInit()
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{
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RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_ADCPRE_Msk)
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| RCC_CFGR_ADCPRE_DIV6; // ADC clock divided by 6 (72MHz/6 = 12MHz)
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RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
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#if defined(SEND_RSSI_DATA)
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RCC->APB2ENR |= RCC_APB2ENR_ADC2EN;
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#endif
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// Init ADCs in dual mode (RSSI)
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#if defined(SEND_RSSI_DATA)
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ADC1->CR1 = ADC_CR1_DUALMOD_1|ADC_CR1_DUALMOD_2; // Regular simultaneous mode
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#endif
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// Set sampling time to 7.5 cycles
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if (PIN_RX_ADC_CH < 10) {
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ADC1->SMPR2 = ADC_SMPR2_SMP0_0 << (3*PIN_RX_ADC_CH);
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} else {
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ADC1->SMPR1 = ADC_SMPR1_SMP10_0 << (3*PIN_RX_ADC_CH);
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}
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#if defined(SEND_RSSI_DATA)
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if (PIN_RSSI_ADC_CH < 10) {
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ADC2->SMPR2 = ADC_SMPR2_SMP0_0 << (3*PIN_RSSI_ADC_CH);
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} else {
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ADC2->SMPR1 = ADC_SMPR1_SMP10_0 << (3*PIN_RSSI_ADC_CH);
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}
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#endif
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// Set conversion channel (single conversion)
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ADC1->SQR3 = PIN_RX_ADC_CH;
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#if defined(SEND_RSSI_DATA)
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ADC2->SQR3 = PIN_RSSI_ADC_CH;
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#endif
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// Enable ADC
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ADC1->CR2 |= ADC_CR2_ADON;
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#if defined(SEND_RSSI_DATA)
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// Enable ADC2
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ADC2->CR2 |= ADC_CR2_ADON;
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#endif
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// Start calibration
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delay(6*2);
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ADC1->CR2 |= ADC_CR2_CAL;
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while((ADC1->CR2 & ADC_CR2_CAL) == ADC_CR2_CAL)
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;
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#if defined(SEND_RSSI_DATA)
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ADC2->CR2 |= ADC_CR2_CAL;
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while((ADC2->CR2 & ADC_CR2_CAL) == ADC_CR2_CAL)
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;
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#endif
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// Trigger first conversion
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ADC1->CR2 |= ADC_CR2_ADON;
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}
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static inline void DACInit()
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{
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RCC->APB1ENR |= RCC_APB1ENR_DACEN;
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DAC->CR = DAC_CR_EN1;
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}
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static inline void TimerInit()
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{
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RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
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#if defined(EXTERNAL_OSC)
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// Enable external clock, prescaler /4
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TIM2->SMCR = TIM_SMCR_ECE | TIM_SMCR_ETPS_1;
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#endif
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// TIM2 output frequency
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TIM2->PSC = 0;
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#if defined(EXTERNAL_OSC)
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// TimerCount = ExternalOsc
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// /4 (external clock prescaler)
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// /SAMP_FREQ
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TIM2->ARR = (uint16_t) ((EXTERNAL_OSC/(4*SAMP_FREQ)) - 1);
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#else
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TIM2->ARR = (uint16_t) ((SystemCoreClock/(SAMP_FREQ)) - 1);
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#endif
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// Enable TIse 1%-tolerance comM2 interrupt
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TIM2->DIER = TIM_DIER_UIE;
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NVIC_EnableIRQ(TIM2_IRQn);
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// Enable TIM2
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TIM2->CR1 |= TIM_CR1_CEN;
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}
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void CIO::initInt()
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{
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GPIOInit();
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ADCInit();
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DACInit();
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#if defined(STM32F1_POG)
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FancyLEDEffect();
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#endif
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}
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void CIO::startInt()
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{
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TimerInit();
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BB_COSLED = 0;
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BB_LED = 1;
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}
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void CIO::interrupt()
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{
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uint8_t control = MARK_NONE;
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uint16_t sample = DC_OFFSET;
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uint16_t rawRSSI = 0U;
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bitband_t eoc = (bitband_t)BITBAND_PERIPH(&ADC1->SR, ADC_SR_EOS_Pos);
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bitband_t adon = (bitband_t)BITBAND_PERIPH(&ADC1->CR2, ADC_CR2_ADON_Pos);
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if (*eoc) {
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// trigger next conversion
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*adon = 1;
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m_txBuffer.get(sample, control);
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DAC->DHR12R1 = sample; // Send the value to the DAC
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// Read value from ADC1 and ADC2
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sample = ADC1->DR; // read conversion result; EOC is cleared by this read
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m_rxBuffer.put(sample, control);
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#if defined(SEND_RSSI_DATA)
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rawRSSI = ADC2->DR;
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m_rssiBuffer.put(rawRSSI);
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#endif
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m_watchdog++;
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}
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}
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bool CIO::getCOSInt()
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{
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return BB_COS;
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}
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void CIO::setLEDInt(bool on)
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{
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BB_LED = !!on;
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}
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void CIO::setPTTInt(bool on)
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{
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BB_PTT = !!on;
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}
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void CIO::setCOSInt(bool on)
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{
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BB_COSLED = !!on;
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}
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void CIO::setDStarInt(bool on)
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{
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BB_DSTAR = !!on;
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}
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void CIO::setDMRInt(bool on)
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{
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BB_DMR = !!on;
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}
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void CIO::setYSFInt(bool on)
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{
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BB_YSF = !!on;
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}
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void CIO::setP25Int(bool on)
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{
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BB_P25 = !!on;
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}
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#endif
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@ -0,0 +1,50 @@
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/*
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* source: http://mightydevices.com/?p=144
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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||||
*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#if !defined(STM32UTILS_H)
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#define STM32UTILS_H
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#include <stdint.h>
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/* ram function */
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#define RAMFUNC __attribute__ ((long_call, section (".data")))
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/* eeprom data */
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/* for placing variables in eeprom memory */
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#define EEMEM __attribute__((section(".eeprom")))
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/* bitband type */
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typedef volatile uint32_t * const bitband_t;
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/* base address for bit banding */
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#define BITBAND_SRAM_REF (0x20000000)
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/* base address for bit banding */
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#define BITBAND_SRAM_BASE (0x22000000)
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/* base address for bit banding */
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#define BITBAND_PERIPH_REF (0x40000000)
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/* base address for bit banding */
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#define BITBAND_PERIPH_BASE (0x42000000)
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/* sram bit band */
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#define BITBAND_SRAM(address, bit) ((void*)(BITBAND_SRAM_BASE + \
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(((uint32_t)address) - BITBAND_SRAM_REF) * 32 + (bit) * 4))
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/* periph bit band */
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#define BITBAND_PERIPH(address, bit) ((void *)(BITBAND_PERIPH_BASE + \
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(((uint32_t)address) - BITBAND_PERIPH_REF) * 32 + (bit) * 4))
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#endif
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