mirror of https://github.com/markqvist/MMDVM.git
228 lines
8.1 KiB
C
228 lines
8.1 KiB
C
/**
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******************************************************************************
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* @file system_stm32f1xx.c
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* @author MCD Application Team, Wojciech Krutnik
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* @version V2.2.2
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* @date 26-June-2015
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
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*
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* 1. This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f1xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* 2. After each device reset the HSI (8 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32f1xx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* 3. This file configures the system clock and flash as follows:
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*=============================================================================
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* Supported STM32F1xx device
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*-----------------------------------------------------------------------------
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* System Clock source | PLL
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*-----------------------------------------------------------------------------
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* SYSCLK | 72MHz
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*-----------------------------------------------------------------------------
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* HCLK | 72Mhz
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*-----------------------------------------------------------------------------
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* PCLK1 | 36MHz
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*-----------------------------------------------------------------------------
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* PCLK2 | 72MHz
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 2
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 1
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*-----------------------------------------------------------------------------
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* PLLSRC | HSE/1
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*-----------------------------------------------------------------------------
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* PLLMUL | 9
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*-----------------------------------------------------------------------------
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* HSE | 8MHz
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*-----------------------------------------------------------------------------
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* Flash Latency(WS) | 2
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*-----------------------------------------------------------------------------
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* Prefetch Buffer | ON
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#if defined(STM32F105xC)
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f1xx_system
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* @{
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*/
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/** @addtogroup STM32F1xx_System_Private_Includes
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* @{
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*/
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#include "stm32f1xx.h"
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/**
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* @}
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*/
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/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F1xx_System_Private_Defines
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* @{
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
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This value can be provided and adapted by the user application. */
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#endif /* HSE_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
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This value can be provided and adapted by the user application. */
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#endif /* HSI_VALUE */
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/**
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* @}
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*/
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/** @addtogroup STM32f1xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F1xx_System_Private_Variables
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* @{
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*/
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uint32_t SystemCoreClock = 48000000;
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/**
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* @}
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*/
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/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
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* @{
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*/
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static void SetSysClock(void);
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/**
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* @}
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*/
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/** @addtogroup STM32F1xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system.
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* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* Enable Prefetch Buffer, 2 wait states */
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FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_1;
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/* Configure the System clock frequency, AHB/APBx prescalers */
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SetSysClock();
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}
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/**
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* @brief Configures the System clock frequency and AHB/APBx prescalers
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* settings.
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* @param None
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* @retval None
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*/
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static void SetSysClock(void)
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{
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/* Enable HSE and Clock Security System */
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RCC->CR |= RCC_CR_CSSON | RCC_CR_HSEON;
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/* Wait for HSE startup */
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while((RCC->CR & RCC_CR_HSERDY) == 0)
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;
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/* Enable PLL with 9x multiplier and HSE clock source
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* APB1 prescaler /2 */
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RCC->CFGR = (RCC->CFGR & (~RCC_CFGR_PLLMULL)) | RCC_CFGR_PLLMULL9
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| RCC_CFGR_PLLSRC;
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RCC->CR |= RCC_CR_PLLON;
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while((RCC->CR & RCC_CR_PLLRDY) == 0)
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;
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/* HCLK = SYSCLK */
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RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_HPRE) | RCC_CFGR_HPRE_DIV1;
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/* PCLK1 = HCLK/2; PCLK2 = HCLK */
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RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_PPRE1|RCC_CFGR_PPRE2))
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| RCC_CFGR_PPRE1_DIV2;
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/* Switch SYSCLK to PLL */
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
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;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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