158 lines
4.1 KiB
C
158 lines
4.1 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2011 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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* \brief ADC hardware-specific implementation
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*
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* \author Daniele Basile <asterix@develer.com>
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*/
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#include "adc_sam3.h"
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#include "cfg/cfg_adc.h"
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#include <cfg/macros.h>
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#include <cfg/compiler.h>
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// Define log settings for cfg/log.h.
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#define LOG_LEVEL ADC_LOG_LEVEL
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#define LOG_FORMAT ADC_LOG_FORMAT
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#include <cfg/log.h>
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#include <drv/adc.h>
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#include <drv/irq_cm3.h>
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#include <cpu/irq.h>
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#include <mware/event.h>
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#include <io/cm3.h>
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/* We use event to signal the end of conversion */
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static Event data_ready;
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/* The last converted data */
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static uint32_t data;
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/**
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* ADC ISR.
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*
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* The interrupt is connected to ready data, so when the
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* adc ends the conversion we generate an event and then
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* we return the converted value.
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*
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* \note to clear the Ready data bit and End of conversion
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* bit we should read the Last Converted Data register, otherwise
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* the ready data interrupt loop on this call.
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*/
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static DECLARE_ISR(adc_conversion_end_irq)
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{
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data = 0;
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if (ADC_ISR & BV(ADC_DRDY))
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{
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data = ADC_LDATA;
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event_do(&data_ready);
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}
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}
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/**
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* Select mux channel \a ch.
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*/
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void adc_hw_select_ch(uint8_t ch)
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{
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/* Disable all channels */
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ADC_CHDR = ADC_CH_MASK;
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/* Enable select channel */
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ADC_CHER = BV(ch);
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}
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/**
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* Start an ADC convertion.
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*/
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uint16_t adc_hw_read(void)
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{
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ADC_CR = BV(ADC_START);
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event_wait(&data_ready);
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return(data);
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}
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/**
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* Init ADC hardware.
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*/
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void adc_hw_init(void)
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{
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/* Make sure that interrupt are enabled */
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IRQ_ASSERT_ENABLED();
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/* Initialize the dataready event */
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event_initGeneric(&data_ready);
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/* Clock ADC peripheral */
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pmc_periphEnable(ADC_ID);
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/* Reset adc controller */
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ADC_CR = ADC_SWRST;
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/*
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* Set adc mode register:
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* - Disable hardware trigger and enable software trigger.
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* - Select normal mode.
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*/
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ADC_MR = 0;
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/* Set ADC_BITS bit convertion resolution. */
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#if ADC_BITS == 12
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ADC_MR &= ~BV(ADC_LOWRES);
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#elif ADC_BITS == 10
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ADC_MR |= BV(ADC_LOWRES);
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#else
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#error No select bit resolution is supported to this CPU
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#endif
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/* Setup ADC */
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LOG_INFO("Computed ADC_CLOCK %ld\n", ADC_CLOCK);
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ADC_MR |= ((ADC_PRESCALER << ADC_PRESCALER_SHIFT) & ADC_PRESCALER_MASK);
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LOG_INFO("prescaler[%ld]\n", ADC_PRESCALER);
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ADC_MR |= ((CONFIG_ADC_SUT << ADC_STARTUP_SHIFT) & ADC_STARTUP_MASK);
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LOG_INFO("starup[%d]\n", CONFIG_ADC_SUT);
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ADC_MR |= ((CONFIG_ADC_STTLING << ADC_SETTLING_SHIFT) & ADC_SETTLING_MASK);
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LOG_INFO("sttime[%d]\n", CONFIG_ADC_STTLING);
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ADC_MR |= ((CONFIG_ADC_TRACKTIM << ADC_TRACKTIM_SHIFT) & ADC_TRACKTIM_MASK);
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LOG_INFO("tracking[%d]\n", CONFIG_ADC_TRACKTIM);
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ADC_MR |= ((CONFIG_ADC_TRANSFER << ADC_TRANSFER_SHIFT) & ADC_TRANSFER_MASK);
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LOG_INFO("tranfer[%d]\n", CONFIG_ADC_TRANSFER);
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/* Register and enable irq for adc. */
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sysirq_setHandler(INT_ADC, adc_conversion_end_irq);
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ADC_IER = BV(ADC_DRDY);
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}
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