152 lines
4.0 KiB
C
152 lines
4.0 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2010 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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* \brief STM32 Clocking driver.
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*
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* \author Andrea Righi <arighi@develer.com>
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*/
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#include "clock_stm32.h"
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#include <cfg/compiler.h>
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#include <cfg/debug.h>
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#include <io/stm32.h>
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struct RCC *RCC;
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INLINE int rcc_get_flag_status(uint32_t flag)
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{
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uint32_t id;
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reg32_t reg;
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/* Get the RCC register index */
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id = flag >> 5;
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/* The flag to check is in CR register */
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if (id == 1)
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reg = RCC->CR;
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/* The flag to check is in BDCR register */
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else if (id == 2)
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reg = RCC->BDCR;
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/* The flag to check is in CSR register */
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else
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reg = RCC->CSR;
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/* Get the flag position */
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id = flag & FLAG_MASK;
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return reg & (1 << id);
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}
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INLINE uint16_t pll_clock(void)
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{
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unsigned int div, mul;
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/* Hopefully this is evaluate at compile time... */
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for (div = 2; div; div--)
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for (mul = 2; mul <= 16; mul++)
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if (CPU_FREQ <= (PLL_VCO / div * mul))
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break;
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return mul << 8 | div;
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}
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INLINE void rcc_pll_config(void)
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{
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reg32_t reg = RCC->CFGR & CFGR_PLL_MASK;
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/* Evaluate clock parameters */
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uint16_t clock = pll_clock();
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uint32_t pll_mul = ((clock >> 8) - 2) << 18;
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uint32_t pll_div = ((clock & 0xff) << 1 | 1) << 16;
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/* Set the PLL configuration bits */
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reg |= pll_div | pll_mul;
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/* Store the new value */
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RCC->CFGR = reg;
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/* Enable PLL */
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*CR_PLLON_BB = 1;
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}
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INLINE void rcc_set_clock_source(uint32_t source)
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{
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reg32_t reg;
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reg = RCC->CFGR & CFGR_SW_MASK;
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reg |= source;
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RCC->CFGR = reg;
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}
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void clock_init(void)
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{
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/* Initialize global RCC structure */
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RCC = (struct RCC *)RCC_BASE;
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/* Enable the internal oscillator */
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*CR_HSION_BB = 1;
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while (!rcc_get_flag_status(RCC_FLAG_HSIRDY));
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/* Clock the system from internal HSI RC (8 MHz) */
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rcc_set_clock_source(RCC_SYSCLK_HSI);
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/* Enable external oscillator */
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RCC->CR &= CR_HSEON_RESET;
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RCC->CR &= CR_HSEBYP_RESET;
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RCC->CR |= CR_HSEON_SET;
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while (!rcc_get_flag_status(RCC_FLAG_HSERDY));
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/* Initialize PLL according to CPU_FREQ */
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rcc_pll_config();
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while(!rcc_get_flag_status(RCC_FLAG_PLLRDY));
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/* Configure USB clock (48MHz) */
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*CFGR_USBPRE_BB = RCC_USBCLK_PLLCLK_1DIV5;
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/* Configure ADC clock: PCLK2 (9MHz) */
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RCC->CFGR &= CFGR_ADCPRE_RESET_MASK;
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RCC->CFGR |= RCC_PCLK2_DIV8;
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/* Configure system clock dividers: PCLK2 (72MHz) */
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RCC->CFGR &= CFGR_PPRE2_RESET_MASK;
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RCC->CFGR |= RCC_HCLK_DIV1 << 3;
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/* Configure system clock dividers: PCLK1 (36MHz) */
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RCC->CFGR &= CFGR_PPRE1_RESET_MASK;
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RCC->CFGR |= RCC_HCLK_DIV2;
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/* Configure system clock dividers: HCLK */
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RCC->CFGR &= CFGR_HPRE_RESET_MASK;
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RCC->CFGR |= RCC_SYSCLK_DIV1;
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/* Set 1 wait state for the flash memory */
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*(reg32_t *)FLASH_BASE = 0x12;
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/* Clock the system from the PLL */
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rcc_set_clock_source(RCC_SYSCLK_PLLCLK);
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}
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