354 lines
8.3 KiB
C
354 lines
8.3 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2010 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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* \brief STM32F103xx I2C driver.
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*
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* \author Daniele Basile <asterix@develer.com>
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*/
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#include "cfg/cfg_i2c.h"
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#define LOG_LEVEL I2C_LOG_LEVEL
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#define LOG_FORMAT I2C_LOG_FORMAT
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#include <cfg/log.h>
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#include <cfg/debug.h>
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#include <cfg/macros.h> // BV()
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#include <cfg/module.h>
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#include <cpu/power.h>
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#include <drv/gpio_stm32.h>
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#include <drv/irq_cm3.h>
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#include <drv/clock_stm32.h>
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#include <drv/i2c.h>
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#include <drv/timer.h>
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#include <io/stm32.h>
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struct I2cHardware
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{
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struct stm32_i2c *base;
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uint32_t clk_i2c_en;
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uint32_t pin_mask;
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uint8_t cache[2];
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bool cached;
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};
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#define WAIT_BTF(base) \
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do { \
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while (!(base->SR1 & BV(SR1_BTF))) \
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cpu_relax(); \
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} while (0)
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#define WAIT_RXNE(base) \
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do { \
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while (!(base->SR1 & BV(SR1_RXNE))) \
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cpu_relax(); \
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} while (0)
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INLINE uint32_t get_status(struct stm32_i2c *base)
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{
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return ((base->SR1 | (base->SR2 << 16)) & 0x00FFFFFF);
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}
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/*
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* This fuction read the status registers of the i2c device
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* and waint until the selec event happen. If occur one error
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* the funtions return false.
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*/
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INLINE bool wait_event(I2c *i2c, uint32_t event)
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{
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while (true)
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{
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uint32_t stat = get_status(i2c->hw->base);
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if (stat == event)
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break;
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if (stat & SR1_ERR_MASK)
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{
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i2c->hw->base->SR1 &= ~SR1_ERR_MASK;
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return false;
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}
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cpu_relax();
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}
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return true;
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}
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INLINE void start_w(struct I2c *i2c, uint16_t slave_addr)
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{
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/*
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* Loop on the select write sequence: when the eeprom is busy
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* writing previously sent data it will reply to the SLA_W
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* control byte with a NACK. In this case, we must
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* keep trying until the eeprom responds with an ACK.
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*/
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ticks_t start = timer_clock();
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while (true)
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{
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i2c->hw->base->CR1 |= CR1_ACK_SET | CR1_START_SET;
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if(!wait_event(i2c, I2C_EVENT_MASTER_MODE_SELECT))
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{
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LOG_ERR("ARBIT lost\n");
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i2c->errors |= I2C_ARB_LOST;
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break;
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}
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i2c->hw->base->DR = slave_addr & OAR1_ADD0_RESET;
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if(wait_event(i2c, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
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break;
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if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
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{
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LOG_ERR("Timeout on I2C START\n");
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i2c->errors |= I2C_START_TIMEOUT;
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i2c->hw->base->CR1 |= CR1_STOP_SET;
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break;
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}
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}
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}
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INLINE bool start_and_addr(struct I2c *i2c, uint16_t slave_addr)
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{
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i2c->hw->base->CR1 |= CR1_START_SET;
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if(!wait_event(i2c, I2C_EVENT_MASTER_MODE_SELECT))
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{
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LOG_ERR("ARBIT lost\n");
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i2c->errors |= I2C_ARB_LOST;
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i2c->hw->base->CR1 |= CR1_STOP_SET;
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return false;
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}
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i2c->hw->base->DR = (slave_addr | OAR1_ADD0_SET);
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if (i2c->xfer_size == 2)
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i2c->hw->base->CR1 |= CR1_ACK_SET | CR1_POS_SET;
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if(!wait_event(i2c, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
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{
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LOG_ERR("SLAR NACK:%08lx\n", get_status(i2c->hw->base));
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i2c->errors |= I2C_NO_ACK;
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i2c->hw->base->CR1 |= CR1_STOP_SET;
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return false;
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}
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return true;
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}
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INLINE void start_r(struct I2c *i2c, uint16_t slave_addr)
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{
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if (!start_and_addr(i2c, slave_addr))
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return;
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/*
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* Due to the hardware receive bytes from slave in automatically mode
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* we should manage contextually all cases that we want to read one, two or more
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* than two bytes. To comply this behaviour to our api we shoul bufferd some byte
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* to hide all special case that needs to use this device.
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*/
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if (i2c->xfer_size == 1)
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{
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i2c->hw->base->CR1 &= CR1_ACK_RESET;
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cpu_flags_t irq;
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IRQ_SAVE_DISABLE(irq);
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(void)i2c->hw->base->SR2;
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if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
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i2c->hw->base->CR1 |= CR1_STOP_SET;
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IRQ_RESTORE(irq);
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WAIT_RXNE(i2c->hw->base);
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i2c->hw->cache[0] = i2c->hw->base->DR;
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i2c->hw->cached = true;
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if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
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while (i2c->hw->base->CR1 & CR1_STOP_SET);
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i2c->hw->base->CR1 |= CR1_ACK_SET;
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}
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else if (i2c->xfer_size == 2)
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{
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cpu_flags_t irq;
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IRQ_SAVE_DISABLE(irq);
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(void)i2c->hw->base->SR2;
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i2c->hw->base->CR1 &= CR1_ACK_RESET;
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IRQ_RESTORE(irq);
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WAIT_BTF(i2c->hw->base);
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IRQ_SAVE_DISABLE(irq);
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if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
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i2c->hw->base->CR1 |= CR1_STOP_SET;
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/*
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* We store read bytes like a fifo..
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*/
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i2c->hw->cache[1] = i2c->hw->base->DR;
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i2c->hw->cache[0] = i2c->hw->base->DR;
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i2c->hw->cached = true;
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IRQ_RESTORE(irq);
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i2c->hw->base->CR1 &= CR1_POS_RESET;
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i2c->hw->base->CR1 |= CR1_ACK_SET;
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}
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}
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static void i2c_stm32_start(struct I2c *i2c, uint16_t slave_addr)
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{
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i2c->hw->cached = false;
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if (I2C_TEST_START(i2c->flags) == I2C_START_W)
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start_w(i2c, slave_addr);
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else /* (I2C_TEST_START(i2c->flags) == I2C_START_R) */
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start_r(i2c, slave_addr);
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}
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static void i2c_stm32_putc(I2c *i2c, const uint8_t data)
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{
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i2c->hw->base->DR = data;
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WAIT_BTF(i2c->hw->base);
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/* Generate the stop if we finish to send all programmed bytes */
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if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
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{
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wait_event(i2c, I2C_EVENT_MASTER_BYTE_TRANSMITTED);
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i2c->hw->base->CR1 |= CR1_STOP_SET;
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}
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}
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static uint8_t i2c_stm32_getc(I2c *i2c)
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{
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if (i2c->hw->cached)
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{
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ASSERT(i2c->xfer_size <= 2);
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return i2c->hw->cache[i2c->xfer_size - 1];
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}
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else
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{
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WAIT_BTF(i2c->hw->base);
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if (i2c->xfer_size == 3)
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{
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i2c->hw->base->CR1 &= CR1_ACK_RESET;
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cpu_flags_t irq;
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IRQ_SAVE_DISABLE(irq);
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uint8_t data = i2c->hw->base->DR;
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if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
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i2c->hw->base->CR1 |= CR1_STOP_SET;
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i2c->hw->cache[1] = i2c->hw->base->DR;
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IRQ_RESTORE(irq);
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WAIT_RXNE(i2c->hw->base);
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i2c->hw->cache[0] = i2c->hw->base->DR;
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i2c->hw->cached = true;
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if (I2C_TEST_STOP(i2c->flags) == I2C_STOP)
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while (i2c->hw->base->CR1 & CR1_STOP_SET);
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return data;
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}
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else
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return i2c->hw->base->DR;
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}
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}
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static const I2cVT i2c_stm32_vt =
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{
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.start = i2c_stm32_start,
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.getc = i2c_stm32_getc,
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.putc = i2c_stm32_putc,
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.write = i2c_genericWrite,
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.read = i2c_genericRead,
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};
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static struct I2cHardware i2c_stm32_hw[] =
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{
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{ /* I2C1 */
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.base = (struct stm32_i2c *)I2C1_BASE,
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.clk_i2c_en = RCC_APB1_I2C1,
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.pin_mask = (GPIO_I2C1_SCL_PIN | GPIO_I2C1_SDA_PIN),
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},
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{ /* I2C2 */
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.base = (struct stm32_i2c *)I2C2_BASE,
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.clk_i2c_en = RCC_APB1_I2C2,
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.pin_mask = (GPIO_I2C2_SCL_PIN | GPIO_I2C2_SDA_PIN),
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},
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};
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/**
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* Initialize I2C module.
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*/
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void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
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{
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i2c->hw = &i2c_stm32_hw[dev];
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i2c->vt = &i2c_stm32_vt;
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RCC->APB2ENR |= RCC_APB2_GPIOB;
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RCC->APB1ENR |= i2c->hw->clk_i2c_en;
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/* Set gpio to use I2C driver */
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stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, i2c->hw->pin_mask,
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GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
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/* Clear all needed registers */
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i2c->hw->base->CR1 = 0;
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i2c->hw->base->CR2 = 0;
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i2c->hw->base->CCR = 0;
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i2c->hw->base->TRISE = 0;
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i2c->hw->base->OAR1 = 0;
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/* Set PCLK1 frequency accornding to the master clock settings. See stm32_clock.c */
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i2c->hw->base->CR2 |= CR2_FREQ_36MHZ;
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/* Configure spi in standard mode */
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ASSERT2(clock >= 100000, "fast mode not supported");
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i2c->hw->base->CCR |= (uint16_t)((CR2_FREQ_36MHZ * 1000000) / (clock << 1));
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i2c->hw->base->TRISE |= (CR2_FREQ_36MHZ + 1);
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i2c->hw->base->CR1 |= CR1_PE_SET;
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}
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