119 lines
3.8 KiB
C
119 lines
3.8 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2010 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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* \brief LM3S debug support (implementation).
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*
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* \author Andrea Righi <arighi@develer.com>
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*/
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#include <cfg/cfg_debug.h>
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#include <cfg/macros.h> /* for BV() */
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#include <drv/clock_lm3s.h> /* lm3s_busyWait() */
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#include <drv/gpio_lm3s.h>
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#include <drv/ser_lm3s.h>
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#include "kdebug_lm3s.h"
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#if CONFIG_KDEBUG_PORT == 0
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#define UART_BASE UART0_BASE
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#define UART_GPIO_BASE GPIO_PORTA_BASE
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#define UART_PINS (BV(1) | BV(0))
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#define UART_REG_SYSCTL SYSCTL_RCGC2_GPIOA
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#elif CONFIG_KDEBUG_PORT == 1
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#define UART_BASE UART1_BASE
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#define UART_GPIO_BASE GPIO_PORTD_BASE
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#define UART_PINS (BV(3) | BV(2))
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#define UART_REG_SYSCTL SYSCTL_RCGC2_GPIOD
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#elif CONFIG_KDEBUG_PORT == 2
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#define UART_BASE UART2_BASE
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#define UART_GPIO_BASE GPIO_PORTG_BASE
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#define UART_PINS (BV(1) | BV(0))
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#define UART_REG_SYSCTL SYSCTL_RCGC2_GPIOG
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#else
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#error "UART port not supported in this board"
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#endif
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#define KDBG_WAIT_READY() while (!lm3s_uartReady(UART_BASE)) {}
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#define KDBG_WAIT_TXDONE() while (!lm3s_uartTxDone(UART_BASE)) {}
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#define KDBG_WRITE_CHAR(c) do { lm3s_uartPutCharNonBlocking(UART_BASE, c); } while(0)
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/* Debug unit is used only for debug purposes so does not generate interrupts. */
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#define KDBG_MASK_IRQ(old) do { (void)old; } while(0)
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/* Debug unit is used only for debug purposes so does not generate interrupts. */
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#define KDBG_RESTORE_IRQ(old) do { (void)old; } while(0)
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typedef uint32_t kdbg_irqsave_t;
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INLINE void uart_hw_config(void)
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{
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unsigned long div, baud = CONFIG_KDEBUG_BAUDRATE;
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bool hi_speed = false;
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if (baud * 16 > CPU_FREQ)
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{
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hi_speed = true;
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baud /= 2;
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}
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div = (CPU_FREQ * 8 / baud + 1) / 2;
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lm3s_uartDisable(UART_BASE);
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if (hi_speed)
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HWREG(UART_BASE + UART_O_CTL) |= UART_CTL_HSE;
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else
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HWREG(UART_BASE + UART_O_CTL) &= ~UART_CTL_HSE;
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/* Set the baud rate */
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HWREG(UART_BASE + UART_O_IBRD) = div / 64;
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HWREG(UART_BASE + UART_O_FBRD) = div % 64;
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/* Set word lenght and parity */
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HWREG(UART_BASE + UART_O_LCRH) = UART_LCRH_WLEN_8;
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lm3s_uartClear(UART_BASE);
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lm3s_uartEnable(UART_BASE);
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}
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INLINE void kdbg_hw_init(void)
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{
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uint32_t reg_clock = 1 << CONFIG_KDEBUG_PORT;
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/* Enable the peripheral clock */
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SYSCTL_RCGC1_R |= reg_clock;
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SYSCTL_RCGC2_R |= UART_REG_SYSCTL;
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lm3s_busyWait(512);
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/* Configure GPIO pins to work as UART pins */
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lm3s_gpioPinConfig(UART_GPIO_BASE, UART_PINS,
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GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
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/* Low-level UART configuration */
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uart_hw_config();
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}
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