273 lines
6.7 KiB
C
273 lines
6.7 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2011 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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* \brief NAND driver hardware implementation for SAM3's static memory controller.
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*
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* \author Stefano Fedrigo <aleph@develer.com>
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*/
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#include <drv/nand.h>
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#include <cfg/log.h>
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#include <io/sam3.h>
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#include <drv/timer.h>
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#include <cpu/power.h> // cpu_relax()
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/*
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* PIO definitions.
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*/
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#define NAND_PIN_CE BV(6)
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#define NAND_PIN_RB BV(2)
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#define NAND_PINS_PORTA (NAND_PIN_CE | NAND_PIN_RB)
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#define NAND_PERIPH_PORTA PIO_PERIPH_B
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#define NAND_PIN_OE BV(19)
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#define NAND_PIN_WE BV(20)
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#define NAND_PIN_IO 0x0000FFFF
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#define NAND_PINS_PORTC (NAND_PIN_OE | NAND_PIN_WE | NAND_PIN_IO)
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#define NAND_PERIPH_PORTC PIO_PERIPH_A
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#define NAND_PIN_CLE BV(9)
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#define NAND_PIN_ALE BV(8)
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#define NAND_PINS_PORTD (NAND_PIN_CLE | NAND_PIN_ALE)
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#define NAND_PERIPH_PORTD PIO_PERIPH_A
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/*
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* Wait for edge transition of READY/BUSY NAND
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* signal.
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* Return true for edge detection, false in case of timeout.
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*/
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bool nand_waitReadyBusy(UNUSED_ARG(Nand *, chip), time_t timeout)
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{
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time_t start = timer_clock();
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while (!(SMC_SR & SMC_SR_RB_EDGE0))
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{
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cpu_relax();
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if (timer_clock() - start > timeout)
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{
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LOG_INFO("nand: R/B timeout\n");
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return false;
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}
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}
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return true;
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}
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/*
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* Wait for transfer to complete until timeout.
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* If transfer completes return true, false in case of timeout.
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*/
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bool nand_waitTransferComplete(UNUSED_ARG(Nand *, chip), time_t timeout)
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{
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time_t start = timer_clock();
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while (!(SMC_SR & SMC_SR_XFRDONE))
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{
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cpu_relax();
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if (timer_clock() - start > timeout)
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{
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LOG_INFO("nand: xfer complete timeout\n");
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return false;
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}
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}
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return true;
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}
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/*
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* Send command to NAND and wait for completion.
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*/
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void nand_sendCommand(Nand *chip,
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uint32_t cmd1, uint32_t cmd2,
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int num_cycles, uint32_t cycle0, uint32_t cycle1234)
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{
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reg32_t *cmd_addr;
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uint32_t cmd_val;
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while (HWREG(NFC_CMD_BASE_ADDR + NFC_CMD_NFCCMD) & 0x8000000);
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if (num_cycles == 5)
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SMC_ADDR = cycle0;
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cmd_val = NFC_CMD_NFCCMD
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| ((chip->chip_select << NFC_CMD_CSID_SHIFT) & NFC_CMD_CSID_MASK)
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| ((num_cycles << NFC_CMD_ACYCLE_SHIFT) & NFC_CMD_ACYCLE_MASK)
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| cmd1 << 2
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| cmd2 << 10;
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// Check for commands transferring data
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if (cmd1 == NAND_CMD_WRITE_1 || cmd1 == NAND_CMD_READ_1 || cmd1 == NAND_CMD_READID)
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cmd_val |= NFC_CMD_NFCEN;
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// Check for commands writing data
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if (cmd1 == NAND_CMD_WRITE_1)
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cmd_val |= NFC_CMD_NFCWR;
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// Check for two command cycles
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if (cmd2)
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cmd_val |= NFC_CMD_VCMD2;
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cmd_addr = (reg32_t *)(NFC_CMD_BASE_ADDR + cmd_val);
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*cmd_addr = cycle1234;
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while (!(SMC_SR & SMC_SR_CMDDONE));
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}
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/*
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* Get NAND chip status register.
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*
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* NOTE: this is global between different chip selects, so returns
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* the status register of the last used NAND chip.
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*/
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uint8_t nand_getChipStatus(UNUSED_ARG(Nand *, chip))
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{
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return (uint8_t)HWREG(NFC_CMD_BASE_ADDR);
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}
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/*
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* Return pointer to buffer where data are read to or written from
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* by nand_sendCommand().
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*/
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void *nand_dataBuffer(UNUSED_ARG(Nand *, chip))
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{
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return (void *)NFC_SRAM_BASE_ADDR;
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}
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/*
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* Extract ECC data from ECC_PRx registers.
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*/
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bool nand_checkEcc(UNUSED_ARG(Nand *, chip))
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{
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uint32_t sr1 = SMC_ECC_SR1;
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if (sr1)
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{
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LOG_INFO("ECC error, ECC_SR1=0x%lx\n", sr1);
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return false;
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}
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else
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return true;
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}
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/*
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* Compute ECC on data in a buffer.
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*
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* \param chip nand context
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* \param buf buffer containing data
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* \param size size of data buffer
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* \param ecc pointer to buffer where computed ECC is stored
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* \param ecc_size max size for ecc buffer
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*/
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void nand_computeEcc(UNUSED_ARG(Nand *, chip),
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UNUSED_ARG(const void *, buf), UNUSED_ARG(size_t, size), uint32_t *ecc, size_t ecc_size)
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{
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size_t i;
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for (i = 0; i < ecc_size; i++)
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ecc[i] = *((reg32_t *)(SMC_BASE + SMC_ECC_PR0_OFF) + i);
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}
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/*
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* Low-level hardware driver initialization.
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*/
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void nand_hwInit(UNUSED_ARG(Nand *, chip))
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{
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// FIXME: Parameters specific for MT29F8G08AAD
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// PIO init
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pmc_periphEnable(PIOA_ID);
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pmc_periphEnable(PIOC_ID);
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pmc_periphEnable(PIOD_ID);
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PIO_PERIPH_SEL(PIOA_BASE, NAND_PINS_PORTA, NAND_PERIPH_PORTA);
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PIOA_PDR = NAND_PINS_PORTA;
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PIOA_PUER = NAND_PINS_PORTA;
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PIO_PERIPH_SEL(PIOC_BASE, NAND_PINS_PORTC, NAND_PERIPH_PORTC);
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PIOC_PDR = NAND_PINS_PORTC;
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PIOC_PUER = NAND_PINS_PORTC;
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PIO_PERIPH_SEL(PIOD_BASE, NAND_PINS_PORTD, NAND_PERIPH_PORTD);
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PIOD_PDR = NAND_PINS_PORTD;
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PIOD_PUER = NAND_PINS_PORTD;
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pmc_periphEnable(SMC_SDRAMC_ID);
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// SMC init
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SMC_SETUP0 = SMC_SETUP_NWE_SETUP(0)
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| SMC_SETUP_NCS_WR_SETUP(0)
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| SMC_SETUP_NRD_SETUP(0)
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| SMC_SETUP_NCS_RD_SETUP(0);
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SMC_PULSE0 = SMC_PULSE_NWE_PULSE(2)
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| SMC_PULSE_NCS_WR_PULSE(3)
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| SMC_PULSE_NRD_PULSE(2)
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| SMC_PULSE_NCS_RD_PULSE(3);
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SMC_CYCLE0 = SMC_CYCLE_NWE_CYCLE(3)
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| SMC_CYCLE_NRD_CYCLE(3);
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SMC_TIMINGS0 = SMC_TIMINGS_TCLR(1)
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| SMC_TIMINGS_TADL(6)
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| SMC_TIMINGS_TAR(4)
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| SMC_TIMINGS_TRR(2)
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| SMC_TIMINGS_TWB(9)
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| SMC_TIMINGS_RBNSEL(7)
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| SMC_TIMINGS_NFSEL;
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SMC_MODE0 = SMC_MODE_READ_MODE
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| SMC_MODE_WRITE_MODE;
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SMC_CFG = SMC_CFG_PAGESIZE_PS2048_64
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| SMC_CFG_EDGECTRL
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| SMC_CFG_DTOMUL_X1048576
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| SMC_CFG_DTOCYC(0xF)
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| SMC_CFG_WSPARE
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| SMC_CFG_RSPARE;
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// Disable SMC interrupts, reset and enable NFC controller
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SMC_IDR = ~0;
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SMC_CTRL = 0;
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SMC_CTRL = SMC_CTRL_NFCEN;
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// Enable ECC, 1 ECC per 256 bytes
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SMC_ECC_CTRL = SMC_ECC_CTRL_SWRST;
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SMC_ECC_MD = SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 | SMC_ECC_MD_TYPCORREC_C256B;
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}
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