Add support for UART2 (STLink UART). Add `WOLFBOOT_ROOT` for proper detection of signing/keytools (requires PR https://github.com/wolfSSL/wolfBoot/pull/103)
David Garske
Dimitar Tomov
parent
012a05864f
commit
0b533d218f
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@ -12,16 +12,39 @@ LC_TIME="C"
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LC_ALL=
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APPSRC:=./src
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WOLFBOOT:=../wolfBoot
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WOLFBOOT_ROOT:=../wolfBoot
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WOLFSSL_ROOT:=../wolfBoot/lib/wolfssl
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WOLFTPM_ROOT:=../wolfBoot/lib/wolfTPM
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ECCKEY:=$(WOLFBOOT)/ecc256.der
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ECCKEY:=$(WOLFBOOT_ROOT)/ecc256.der
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DEBUG?=1
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include $(WOLFBOOT)/tools/config.mk
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include $(WOLFBOOT_ROOT)/tools/config.mk
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export WOLFBOOT_ROOT
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ifneq ("$(wildcard $(WOLFBOOT_ROOT)/tools/keytools/keygen)","")
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KEYGEN_TOOL:=$(WOLFBOOT_ROOT)/tools/keytools/keygen
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else
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ifneq ("$(wildcard $(WOLFBOOT_ROOT)/tools/keytools/keygen.exe)","")
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KEYGEN_TOOL:=$(WOLFBOOT_ROOT)/tools/keytools/keygen.exe
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else
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KEYGEN_TOOL:=python3 $(WOLFBOOT_ROOT)/tools/keytools/keygen.py
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endif
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endif
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ifneq ("$(wildcard $(WOLFBOOT_ROOT)/tools/keytools/sign)","")
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SIGN_TOOL:=$(WOLFBOOT_ROOT)/tools/keytools/sign
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else
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ifneq ("$(wildcard $(WOLFBOOT_ROOT)/tools/keytools/sign.exe)","")
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SIGN_TOOL:=$(WOLFBOOT_ROOT)/tools/keytools/sign.exe
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else
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SIGN_TOOL:=python3 $(WOLFBOOT_ROOT)/tools/keytools/sign.py
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endif
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endif
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CFLAGS:=-g -ggdb -Wall -Wstack-usage=1024 -ffreestanding -Wno-unused -DPLATFORM_$(TARGET) \
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-I$(WOLFBOOT)/include -I$(WOLFBOOT) -I$(WOLFSSL_ROOT) -I$(WOLFTPM_ROOT) \
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-I$(WOLFBOOT_ROOT)/include -I$(WOLFBOOT_ROOT) -I$(WOLFSSL_ROOT) -I$(WOLFTPM_ROOT) \
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-DWOLFBOOT_MEASURED_PCR_A -nostartfiles
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CFLAGS+=-DWOLFBOOT_HASH_SHA256
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CFLAGS+=-DWOLFSSL_USER_SETTINGS
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@ -32,9 +55,9 @@ APP_OBJS:= \
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$(APPSRC)/led.o \
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$(APPSRC)/system.o \
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$(APPSRC)/timer.o \
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$(WOLFBOOT)/hal/$(TARGET).o \
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$(WOLFBOOT)/src/libwolfboot.o \
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$(WOLFBOOT)/hal/spi/spi_drv_stm32.o \
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$(WOLFBOOT_ROOT)/hal/$(TARGET).o \
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$(WOLFBOOT_ROOT)/src/libwolfboot.o \
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$(WOLFBOOT_ROOT)/hal/spi/spi_drv_stm32.o \
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$(APPSRC)/startup_arm.o
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# Add objects for wolfCrypt support required by wolfTPM
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@ -62,7 +85,7 @@ endif
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vpath %.c $(dir $(WOLFSSL_ROOT)/src)
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vpath %.c $(dir $(WOLFSSL_ROOT)/wolfcrypt/src)
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vpath %.c $(dir $(WOLFBOOT))/lib/wolfTPM/wolftpm)
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vpath %.c $(dir $(WOLFBOOT_ROOT))/lib/wolfTPM/wolftpm)
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ENTRY_POINT=`cat .entry-point-address`
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LSCRIPT:=$(APPSRC)/target-app.ld
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@ -71,15 +94,15 @@ LDFLAGS:=$(CFLAGS) -T $(LSCRIPT) -Wl,-gc-sections -Wl,-Map=image.map
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wolfboot-example: wolfboot_align.bin image.bin
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python3 $(WOLFBOOT)/tools/keytools/sign.py --ecc256 image.bin $(ECCKEY) 1
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$(SIGN_TOOL) --ecc256 image.bin $(ECCKEY) 1
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cat wolfboot-align.bin image_v1_signed.bin >factory.bin
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wolfboot-align.bin:LSCRIPT:=$(WOLFBOOT)/target.ld
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wolfboot-align.bin:LSCRIPT:=$(WOLFBOOT_ROOT)/target.ld
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wolfboot_align.bin:CFLAGS+=-DWOLFBOOT_HASH_SHA256
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wolfboot_align.bin: wolfboot_target
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make -C $(WOLFBOOT) align
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cp $(WOLFBOOT)/wolfboot-align.bin .
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cp $(WOLFBOOT)/wolfboot.elf .
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make -C $(WOLFBOOT_ROOT) align
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cp $(WOLFBOOT_ROOT)/wolfboot-align.bin .
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cp $(WOLFBOOT_ROOT)/wolfboot.elf .
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image.bin: wolfboot_target image.elf
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$(OBJCOPY) -O binary image.elf $@
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@ -90,8 +113,8 @@ image.elf: wolfboot_target $(APP_OBJS) $(LSCRIPT)
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$(Q)$(LD) $(LDFLAGS) $(APP_OBJS) -o $@
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wolfboot_target: FORCE
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cp -f measured.wolfboot.config $(WOLFBOOT)/.config
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make -C $(WOLFBOOT) include/target.h
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cp -f measured.wolfboot.config $(WOLFBOOT_ROOT)/.config
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make -C $(WOLFBOOT_ROOT) include/target.h
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%.o:%.c
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@echo "\t[CC-$(ARCH)] $@"
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@ -102,7 +125,7 @@ wolfboot_target: FORCE
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$(Q)$(CC) $(CFLAGS) -c -o $@ $^
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clean:
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make -C $(WOLFBOOT) clean
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make -C $(WOLFBOOT_ROOT) clean
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@rm -f *.bin *.elf $(OBJS) wolfboot.map *.bin *.hex src/*.o tags *.map
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$(LSCRIPT): $(LSCRIPT_TEMPLATE) FORCE
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@ -54,7 +54,9 @@ Hardware connections must be made between the TPM2.0 module and the STM32F4 boar
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| 3V | +3V | Pin 1 |
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| GND | Ground | Pin 6 |
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UART1 on the STM32F4 is used. The UART Pinout can be found below:
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UART1 on the STM32F4 is used by default. The default baud rate is 115200.
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The UART Pinout can be found below:
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| STM32F4 | Pin function |
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|----------|:------------:|
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@ -62,7 +64,10 @@ UART1 on the STM32F4 is used. The UART Pinout can be found below:
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| PB7 | UART RX |
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| GND | Ground |
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Make sure the Ground connection between your USB-UART converter is connected to the STM32F4 board, otherwise UART levels will float and communication will be corrupted.
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Note: The ST-Link USB UDC is UART 2 on PA3 (TX) / PA2 (RX). This can be changed in app_stm32f4.c using APP_UART.
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Note: Make sure the Ground connection between your USB-UART converter is connected to the STM32F4 board, otherwise UART levels will float and communication will be corrupted.
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## Compiling
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@ -38,12 +38,16 @@
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static WOLFTPM2_DEV wolftpm_dev;
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#define UART1 (0x40011000)
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#define UART2 (0x40014400)
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#define UART1_SR (*(volatile uint32_t *)(UART1))
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#define UART1_DR (*(volatile uint32_t *)(UART1 + 0x04))
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#define UART1_BRR (*(volatile uint32_t *)(UART1 + 0x08))
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#define UART1_CR1 (*(volatile uint32_t *)(UART1 + 0x0c))
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#define UART1_CR2 (*(volatile uint32_t *)(UART1 + 0x10))
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#ifndef APP_UART
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#define APP_UART UART1
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#endif
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#define UART_SR (*(volatile uint32_t *)(APP_UART))
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#define UART_DR (*(volatile uint32_t *)(APP_UART + 0x04))
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#define UART_BRR (*(volatile uint32_t *)(APP_UART + 0x08))
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#define UART_CR1 (*(volatile uint32_t *)(APP_UART + 0x0c))
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#define UART_CR2 (*(volatile uint32_t *)(APP_UART + 0x10))
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#define UART_CR1_UART_ENABLE (1 << 13)
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#define UART_CR1_SYMBOL_LEN (1 << 12)
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@ -58,18 +62,32 @@ static WOLFTPM2_DEV wolftpm_dev;
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#define CLOCK_SPEED (168000000)
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(0x40023844))
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(0x40023844))
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#define UART1_APB2_CLOCK_ER (1 << 4)
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#define UART2_APB2_CLOCK_ER (1 << 17)
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#define AHB1_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
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#define AHB1_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
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#define GPIOA_AHB1_CLOCK_ER (1 << 0)
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#define GPIOB_AHB1_CLOCK_ER (1 << 1)
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#ifndef GPIOA_BASE
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#define GPIOA_BASE 0x48000000
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#endif
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#define GPIOA_MODE (*(volatile uint32_t *)(GPIOA_BASE + 0x00))
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#define GPIOA_AFL (*(volatile uint32_t *)(GPIOA_BASE + 0x20))
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#define GPIOA_AFH (*(volatile uint32_t *)(GPIOA_BASE + 0x24))
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#ifndef GPIOB_BASE
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#define GPIOB_BASE 0x48000400
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#endif
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#define GPIOB_MODE (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
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#define GPIOB_AFL (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
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#define GPIOB_AFH (*(volatile uint32_t *)(GPIOB_BASE + 0x24))
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#define UART1_PIN_AF 7
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#define UART1_RX_PIN 7
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#define UART1_TX_PIN 6
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#define UART_PIN_AF 7
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#define UART1_RX_PIN 7 /* PB7 */
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#define UART1_TX_PIN 6 /* PB6 */
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#define UART2_RX_PIN 3 /* PA3 */
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#define UART2_TX_PIN 2 /* PA2 */
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#define MSGSIZE 16
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#define PAGESIZE (256)
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@ -90,9 +108,9 @@ void uart_write(const char c)
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{
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uint32_t reg;
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do {
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reg = UART1_SR;
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reg = UART_SR;
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} while ((reg & UART_SR_TX_EMPTY) == 0);
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UART1_DR = c;
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UART_DR = c;
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}
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void uart_write_hex(const char c)
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@ -104,6 +122,7 @@ void uart_write_hex(const char c)
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static void uart_pins_setup(void)
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{
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uint32_t reg;
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#if APP_UART == UART1
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AHB1_CLOCK_ER |= GPIOB_AHB1_CLOCK_ER;
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/* Set mode = AF */
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reg = GPIOB_MODE & ~ (0x03 << (UART1_RX_PIN * 2));
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@ -113,9 +132,25 @@ static void uart_pins_setup(void)
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/* Alternate function: use low pins (6 and 7) */
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reg = GPIOB_AFL & ~(0xf << ((UART1_TX_PIN) * 4));
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GPIOB_AFL = reg | (UART1_PIN_AF << ((UART1_TX_PIN) * 4));
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GPIOB_AFL = reg | (UART_PIN_AF << ((UART1_TX_PIN) * 4));
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reg = GPIOB_AFL & ~(0xf << ((UART1_RX_PIN) * 4));
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GPIOB_AFL = reg | (UART1_PIN_AF << ((UART1_RX_PIN) * 4));
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GPIOB_AFL = reg | (UART_PIN_AF << ((UART1_RX_PIN) * 4));
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#elif APP_UART == UART2
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AHB1_CLOCK_ER |= GPIOA_AHB1_CLOCK_ER;
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/* Set mode = AF */
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reg = GPIOA_MODE & ~ (0x03 << (UART2_RX_PIN * 2));
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GPIOA_MODE = reg | (2 << (UART2_RX_PIN * 2));
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reg = GPIOA_MODE & ~ (0x03 << (UART2_TX_PIN * 2));
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GPIOA_MODE = reg | (2 << (UART2_TX_PIN * 2));
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/* Alternate function: use low pins (6 and 7) */
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reg = GPIOA_AFL & ~(0xf << ((UART2_TX_PIN) * 4));
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GPIOA_AFL = reg | (UART_PIN_AF << ((UART2_TX_PIN) * 4));
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reg = GPIOA_AFL & ~(0xf << ((UART2_RX_PIN) * 4));
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GPIOA_AFL = reg | (UART_PIN_AF << ((UART2_RX_PIN) * 4));
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#else
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#error Please configure the UART pins
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#endif
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}
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int uart_setup(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
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@ -124,40 +159,44 @@ int uart_setup(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
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/* Enable pins and configure for AF7 */
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uart_pins_setup();
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/* Turn on the device */
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#if APP_UART == UART1
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APB2_CLOCK_ER |= UART1_APB2_CLOCK_ER;
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#elif APP_UART == UART2
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APB2_CLOCK_ER |= UART2_APB2_CLOCK_ER;
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#endif
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/* Configure for TX + RX */
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UART1_CR1 |= (UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE);
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UART_CR1 |= (UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE);
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/* Configure clock */
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UART1_BRR = CLOCK_SPEED / bitrate;
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UART_BRR = CLOCK_SPEED / bitrate;
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/* Configure data bits */
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if (data == 8)
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UART1_CR1 &= ~UART_CR1_SYMBOL_LEN;
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UART_CR1 &= ~UART_CR1_SYMBOL_LEN;
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else
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UART1_CR1 |= UART_CR1_SYMBOL_LEN;
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UART_CR1 |= UART_CR1_SYMBOL_LEN;
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/* Configure parity */
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switch (parity) {
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case 'O':
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UART1_CR1 |= UART_CR1_PARITY_ODD;
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UART_CR1 |= UART_CR1_PARITY_ODD;
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/* fall through to enable parity */
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case 'E':
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UART1_CR1 |= UART_CR1_PARITY_ENABLED;
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UART_CR1 |= UART_CR1_PARITY_ENABLED;
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break;
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default:
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UART1_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
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UART_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
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}
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/* Set stop bits */
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reg = UART1_CR2 & ~UART_CR2_STOPBITS;
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reg = UART_CR2 & ~UART_CR2_STOPBITS;
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if (stop > 1)
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UART1_CR2 = reg & (2 << 12);
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UART_CR2 = reg & (2 << 12);
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else
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UART1_CR2 = reg;
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UART_CR2 = reg;
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/* Turn on uart */
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UART1_CR1 |= UART_CR1_UART_ENABLE;
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UART_CR1 |= UART_CR1_UART_ENABLE;
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return 0;
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}
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@ -167,9 +206,9 @@ char uart_read(void)
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char c;
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volatile uint32_t reg;
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do {
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reg = UART1_SR;
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reg = UART_SR;
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} while ((reg & UART_SR_RX_NOTEMPTY) == 0);
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c = (char)(UART1_DR & 0xff);
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c = (char)(UART_DR & 0xff);
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return c;
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}
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