Add source code of the test-app
Signed-off-by: Dimitar Tomov <dimi@wolfssl.com>pull/4/head
Dimitar Tomov
parent
39fdbeb9fb
commit
d8d200db69
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@ -0,0 +1,45 @@
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MEMORY
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{
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FLASH (rx) : ORIGIN = ##WOLFBOOT_TEST_APP_ADDRESS##, LENGTH = ##WOLFBOOT_TEST_APP_SIZE##
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 16K /* Run in lowmem */
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}
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SECTIONS
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{
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.text :
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{
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_start_text = .;
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KEEP(*(.isr_vector))
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*(.init)
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*(.fini)
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*(.text*)
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*(.rodata*)
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. = ALIGN(4);
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_end_text = .;
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} > FLASH
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_stored_data = .;
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.data : AT (_stored_data)
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{
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_start_data = .;
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KEEP(*(.data*))
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. = ALIGN(4);
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KEEP(*(.ramcode))
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. = ALIGN(4);
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_end_data = .;
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} > RAM
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.bss :
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{
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_start_bss = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_end_bss = .;
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_end = .;
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} > RAM
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}
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PROVIDE(_start_heap = _end);
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PROVIDE(_end_stack = ORIGIN(RAM) + LENGTH(RAM));
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@ -0,0 +1,298 @@
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/* stm32f4.c
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*
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* Test bare-metal blinking led application
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*
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* Copyright (C) 2020 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include "system.h"
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#include "timer.h"
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#include "led.h"
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#include "hal.h"
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#include "wolfboot/wolfboot.h"
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#include "spi_flash.h"
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#ifdef PLATFORM_stm32f4
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#define UART1 (0x40011000)
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#define UART1_SR (*(volatile uint32_t *)(UART1))
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#define UART1_DR (*(volatile uint32_t *)(UART1 + 0x04))
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#define UART1_BRR (*(volatile uint32_t *)(UART1 + 0x08))
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#define UART1_CR1 (*(volatile uint32_t *)(UART1 + 0x0c))
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#define UART1_CR2 (*(volatile uint32_t *)(UART1 + 0x10))
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#define UART_CR1_UART_ENABLE (1 << 13)
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#define UART_CR1_SYMBOL_LEN (1 << 12)
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#define UART_CR1_PARITY_ENABLED (1 << 10)
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#define UART_CR1_PARITY_ODD (1 << 9)
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#define UART_CR1_TX_ENABLE (1 << 3)
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#define UART_CR1_RX_ENABLE (1 << 2)
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#define UART_CR2_STOPBITS (3 << 12)
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#define UART_SR_TX_EMPTY (1 << 7)
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#define UART_SR_RX_NOTEMPTY (1 << 5)
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#define CLOCK_SPEED (168000000)
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(0x40023844))
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#define UART1_APB2_CLOCK_ER (1 << 4)
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#define AHB1_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
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#define GPIOB_AHB1_CLOCK_ER (1 << 1)
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#define GPIOB_BASE 0x40020400
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#define GPIOB_MODE (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
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#define GPIOB_AFL (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
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#define GPIOB_AFH (*(volatile uint32_t *)(GPIOB_BASE + 0x24))
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#define UART1_PIN_AF 7
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#define UART1_RX_PIN 7
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#define UART1_TX_PIN 6
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#define MSGSIZE 16
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#define PAGESIZE (256)
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static uint8_t page[PAGESIZE];
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static const char ERR='!';
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static const char START='*';
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static const char UPDATE='U';
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static const char ACK='#';
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static uint8_t msg[MSGSIZE];
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void uart_write(const char c)
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{
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uint32_t reg;
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do {
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reg = UART1_SR;
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} while ((reg & UART_SR_TX_EMPTY) == 0);
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UART1_DR = c;
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}
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static void uart_pins_setup(void)
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{
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uint32_t reg;
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AHB1_CLOCK_ER |= GPIOB_AHB1_CLOCK_ER;
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/* Set mode = AF */
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reg = GPIOB_MODE & ~ (0x03 << (UART1_RX_PIN * 2));
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GPIOB_MODE = reg | (2 << (UART1_RX_PIN * 2));
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reg = GPIOB_MODE & ~ (0x03 << (UART1_TX_PIN * 2));
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GPIOB_MODE = reg | (2 << (UART1_TX_PIN * 2));
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/* Alternate function: use low pins (6 and 7) */
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reg = GPIOB_AFL & ~(0xf << ((UART1_TX_PIN) * 4));
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GPIOB_AFL = reg | (UART1_PIN_AF << ((UART1_TX_PIN) * 4));
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reg = GPIOB_AFL & ~(0xf << ((UART1_RX_PIN) * 4));
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GPIOB_AFL = reg | (UART1_PIN_AF << ((UART1_RX_PIN) * 4));
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}
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int uart_setup(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
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{
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uint32_t reg;
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/* Enable pins and configure for AF7 */
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uart_pins_setup();
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/* Turn on the device */
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APB2_CLOCK_ER |= UART1_APB2_CLOCK_ER;
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/* Configure for TX + RX */
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UART1_CR1 |= (UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE);
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/* Configure clock */
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UART1_BRR = CLOCK_SPEED / bitrate;
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/* Configure data bits */
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if (data == 8)
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UART1_CR1 &= ~UART_CR1_SYMBOL_LEN;
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else
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UART1_CR1 |= UART_CR1_SYMBOL_LEN;
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/* Configure parity */
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switch (parity) {
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case 'O':
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UART1_CR1 |= UART_CR1_PARITY_ODD;
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/* fall through to enable parity */
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case 'E':
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UART1_CR1 |= UART_CR1_PARITY_ENABLED;
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break;
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default:
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UART1_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
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}
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/* Set stop bits */
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reg = UART1_CR2 & ~UART_CR2_STOPBITS;
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if (stop > 1)
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UART1_CR2 = reg & (2 << 12);
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else
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UART1_CR2 = reg;
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/* Turn on uart */
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UART1_CR1 |= UART_CR1_UART_ENABLE;
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return 0;
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}
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char uart_read(void)
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{
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char c;
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volatile uint32_t reg;
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do {
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reg = UART1_SR;
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} while ((reg & UART_SR_RX_NOTEMPTY) == 0);
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c = (char)(UART1_DR & 0xff);
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return c;
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}
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static void ack(uint32_t _off)
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{
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uint8_t *off = (uint8_t *)(&_off);
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int i;
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uart_write(ACK);
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for (i = 0; i < 4; i++) {
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uart_write(off[i]);
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}
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}
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static int check(uint8_t *pkt, int size)
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{
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int i;
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uint16_t c = 0;
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uint16_t c_rx = *((uint16_t *)(pkt + 2));
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uint16_t *p = (uint16_t *)(pkt + 4);
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for (i = 0; i < ((size - 4) >> 1); i++)
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c += p[i];
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if (c == c_rx)
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return 0;
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return -1;
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}
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volatile uint32_t time_elapsed = 0;
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void main(void) {
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uint32_t tlen = 0;
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volatile uint32_t recv_seq;
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uint32_t r_total = 0;
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uint32_t tot_len = 0;
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uint32_t next_seq = 0;
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uint32_t version = 0;
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uint8_t *v_array = (uint8_t *)&version;
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int i;
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memset(page, 0xFF, PAGESIZE);
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boot_led_on();
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flash_set_waitstates();
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clock_config();
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led_pwm_setup();
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pwm_init(CPU_FREQ, 0);
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/* Dim the led by altering the PWM duty-cicle
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* in isr_tim2 (timer.c)
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*
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* Every 50ms, the duty cycle of the PWM connected
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* to the blue led increases/decreases making a pulse
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* effect.
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*/
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timer_init(CPU_FREQ, 1, 50);
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uart_setup(115200, 8, 'N', 1);
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memset(page, 0xFF, PAGESIZE);
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asm volatile ("cpsie i");
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while(time_elapsed == 0)
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WFI();
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hal_flash_unlock();
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version = wolfBoot_current_firmware_version();
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if ((version & 0x01) == 0)
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wolfBoot_success();
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#ifdef EXT_ENCRYPTED
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wolfBoot_set_encrypt_key("0123456789abcdef0123456789abcdef", 32);
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#endif
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uart_write(START);
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for (i = 3; i >= 0; i--) {
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uart_write(v_array[i]);
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}
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while (1) {
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r_total = 0;
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do {
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while(r_total < 2) {
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msg[r_total++] = uart_read();
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if ((r_total == 2) && ((msg[0] != 0xA5) || msg[1] != 0x5A)) {
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r_total = 0;
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continue;
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}
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}
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msg[r_total++] = uart_read();
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if ((tot_len == 0) && r_total == 2 + sizeof(uint32_t))
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break;
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if ((r_total > 8) && (tot_len <= ((r_total - 8) + next_seq)))
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break;
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} while (r_total < MSGSIZE);
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if (tot_len == 0) {
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tlen = msg[2] + (msg[3] << 8) + (msg[4] << 16) + (msg[5] << 24);
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if (tlen > WOLFBOOT_PARTITION_SIZE - 8) {
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uart_write(ERR);
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uart_write(ERR);
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uart_write(ERR);
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uart_write(ERR);
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uart_write(START);
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recv_seq = 0;
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tot_len = 0;
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continue;
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}
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tot_len = tlen;
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ack(0);
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continue;
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}
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if (check(msg, r_total) < 0) {
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ack(next_seq);
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continue;
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}
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recv_seq = msg[4] + (msg[5] << 8) + (msg[6] << 16) + (msg[7] << 24);
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if (recv_seq == next_seq)
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{
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int psize = r_total - 8;
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int page_idx = recv_seq % PAGESIZE;
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memcpy(&page[recv_seq % PAGESIZE], msg + 8, psize);
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page_idx += psize;
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if ((page_idx == PAGESIZE) || (next_seq + psize >= tot_len)) {
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uint32_t dst = (WOLFBOOT_PARTITION_UPDATE_ADDRESS + recv_seq + psize) - page_idx;
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if ((dst % WOLFBOOT_SECTOR_SIZE) == 0) {
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hal_flash_erase(dst, WOLFBOOT_SECTOR_SIZE);
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}
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hal_flash_write(dst, page, PAGESIZE);
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memset(page, 0xFF, PAGESIZE);
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}
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next_seq += psize;
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}
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ack(next_seq);
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if (next_seq >= tot_len) {
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/* Update complete */
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spi_flash_probe();
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wolfBoot_update_trigger();
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spi_release();
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hal_flash_lock();
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break;
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}
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}
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/* Wait for reboot */
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while(1)
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;
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}
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#endif /** PLATFORM_stm32f4 **/
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@ -0,0 +1,180 @@
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/* led.c
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*
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* Test bare-metal blinking led application
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*
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* Copyright (C) 2020 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
|
||||
*
|
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* wolfBoot is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*
|
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include "wolfboot/wolfboot.h"
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#ifdef PLATFORM_stm32f4
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#define AHB1_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
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#define GPIOD_AHB1_CLOCK_ER (1 << 3)
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#define GPIOD_BASE 0x40020c00
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#define GPIOD_MODE (*(volatile uint32_t *)(GPIOD_BASE + 0x00))
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#define GPIOD_OTYPE (*(volatile uint32_t *)(GPIOD_BASE + 0x04))
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#define GPIOD_OSPD (*(volatile uint32_t *)(GPIOD_BASE + 0x08))
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#define GPIOD_PUPD (*(volatile uint32_t *)(GPIOD_BASE + 0x0c))
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#define GPIOD_ODR (*(volatile uint32_t *)(GPIOD_BASE + 0x14))
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#define GPIOD_BSRR (*(volatile uint32_t *)(GPIOD_BASE + 0x18))
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#define GPIOD_AFL (*(volatile uint32_t *)(GPIOD_BASE + 0x20))
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#define GPIOD_AFH (*(volatile uint32_t *)(GPIOD_BASE + 0x24))
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#define LED_PIN (15)
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#define LED_BOOT_PIN (14)
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#define GPIO_OSPEED_100MHZ (0x03)
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void led_pwm_setup(void)
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{
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uint32_t reg;
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AHB1_CLOCK_ER |= GPIOD_AHB1_CLOCK_ER;
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reg = GPIOD_MODE & ~ (0x03 << (LED_PIN * 2));
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GPIOD_MODE = reg | (2 << (LED_PIN * 2));
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reg = GPIOD_OSPD & ~(0x03 << (LED_PIN * 2));
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GPIOD_OSPD = reg | (0x03 << (LED_PIN * 2));
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reg = GPIOD_PUPD & ~(0x03 << (LED_PIN * 2));
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GPIOD_PUPD = reg | (0x02 << (LED_PIN * 2));
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/* Alternate function: use high pin */
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reg = GPIOD_AFH & ~(0xf << ((LED_PIN - 8) * 4));
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GPIOD_AFH = reg | (0x2 << ((LED_PIN - 8) * 4));
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}
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void boot_led_on(void)
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{
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uint32_t reg;
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uint32_t pin = LED_BOOT_PIN;// - 2 * (wolfBoot_current_firmware_version() & 0x01);
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AHB1_CLOCK_ER |= GPIOD_AHB1_CLOCK_ER;
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reg = GPIOD_MODE & ~(0x03 << (pin * 2));
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GPIOD_MODE = reg | (1 << (pin * 2));
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reg = GPIOD_PUPD & ~(0x03 << (pin * 2));
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GPIOD_PUPD = reg | (1 << (pin * 2));
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GPIOD_BSRR |= (1 << pin);
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}
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#endif /* PLATFORM_stm32f4 */
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#ifdef PLATFORM_stm32l0
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#define LED_BOOT_PIN (5)
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#define RCC_IOPENR (*(volatile uint32_t *)(0x4002102C))
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#define IOPAEN (1 << 0)
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#define GPIOA_BASE 0x50000000
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#define GPIOA_MODE (*(volatile uint32_t *)(GPIOA_BASE + 0x00))
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#define GPIOA_OTYPE (*(volatile uint32_t *)(GPIOA_BASE + 0x04))
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#define GPIOA_OSPD (*(volatile uint32_t *)(GPIOA_BASE + 0x08))
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#define GPIOA_PUPD (*(volatile uint32_t *)(GPIOA_BASE + 0x0c))
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#define GPIOA_ODR (*(volatile uint32_t *)(GPIOA_BASE + 0x14))
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#define GPIOA_BSRR (*(volatile uint32_t *)(GPIOA_BASE + 0x18))
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#define GPIOA_AFL (*(volatile uint32_t *)(GPIOA_BASE + 0x20))
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#define GPIOA_AFH (*(volatile uint32_t *)(GPIOA_BASE + 0x24))
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void boot_led_on(void)
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{
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uint32_t reg;
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uint32_t pin = LED_BOOT_PIN;
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RCC_IOPENR |= IOPAEN;
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reg = GPIOA_MODE & ~(0x03 << (pin * 2));
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||||
GPIOA_MODE = reg | (1 << (pin * 2));
|
||||
reg = GPIOA_PUPD & ~(0x03 << (pin * 2));
|
||||
GPIOA_PUPD = reg | (1 << (pin * 2));
|
||||
GPIOA_BSRR |= (1 << pin);
|
||||
}
|
||||
|
||||
|
||||
#endif /* PLATFORM_stm32l0 */
|
||||
|
||||
#ifdef PLATFORM_stm32g0
|
||||
#include <stdint.h>
|
||||
#include "wolfboot/wolfboot.h"
|
||||
|
||||
|
||||
/*GPIOA5*/
|
||||
#define RCC_IOPENR (*(volatile uint32_t *)(0x40021034)) // 40021034
|
||||
#define RCC_IOPENR_GPIOAEN (1 << 0)
|
||||
|
||||
#define GPIOA_BASE 0x50000000
|
||||
#define GPIOA_MODE (*(volatile uint32_t *)(GPIOA_BASE + 0x00))
|
||||
#define GPIOA_OTYPE (*(volatile uint32_t *)(GPIOA_BASE + 0x04))
|
||||
#define GPIOA_OSPD (*(volatile uint32_t *)(GPIOA_BASE + 0x08))
|
||||
#define GPIOA_PUPD (*(volatile uint32_t *)(GPIOA_BASE + 0x0c))
|
||||
#define GPIOA_ODR (*(volatile uint32_t *)(GPIOA_BASE + 0x14))
|
||||
#define GPIOA_BSRR (*(volatile uint32_t *)(GPIOA_BASE + 0x18))
|
||||
#define GPIOA_AFL (*(volatile uint32_t *)(GPIOA_BASE + 0x20))
|
||||
#define GPIOA_AFH (*(volatile uint32_t *)(GPIOA_BASE + 0x24))
|
||||
#define LED_PIN (5)
|
||||
#define LED_BOOT_PIN (5)
|
||||
#define GPIO_OSPEED_100MHZ (0x03)
|
||||
|
||||
void boot_led_on(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
uint32_t pin = LED_BOOT_PIN;
|
||||
RCC_IOPENR |= RCC_IOPENR_GPIOAEN;
|
||||
reg = GPIOA_MODE & ~(0x03 << (pin * 2));
|
||||
GPIOA_MODE = reg | (1 << (pin * 2)); // general purpose output mode
|
||||
reg = GPIOA_PUPD & ~(0x03 << (pin * 2));
|
||||
GPIOA_PUPD = reg | (1 << (pin * 2)); // pull-up
|
||||
GPIOA_BSRR |= (1 << pin); // set pin
|
||||
}
|
||||
|
||||
#endif /** PLATFORM_stm32g0 **/
|
||||
|
||||
#ifdef PLATFORM_stm32wb
|
||||
#define LED_BOOT_PIN (0)
|
||||
#define RCC_AHB2_CLOCK_ER (*(volatile uint32_t *)(0x5800004C))
|
||||
#define GPIOB_AHB2_CLOCK_ER (1 << 1)
|
||||
|
||||
#define GPIOB_BASE 0x48000400
|
||||
#define GPIOB_MODE (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
|
||||
#define GPIOB_OTYPE (*(volatile uint32_t *)(GPIOB_BASE + 0x04))
|
||||
#define GPIOB_OSPD (*(volatile uint32_t *)(GPIOB_BASE + 0x08))
|
||||
#define GPIOB_PUPD (*(volatile uint32_t *)(GPIOB_BASE + 0x0c))
|
||||
#define GPIOB_ODR (*(volatile uint32_t *)(GPIOB_BASE + 0x14))
|
||||
#define GPIOB_BSRR (*(volatile uint32_t *)(GPIOB_BASE + 0x18))
|
||||
#define GPIOB_AFL (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
|
||||
#define GPIOB_AFH (*(volatile uint32_t *)(GPIOB_BASE + 0x24))
|
||||
|
||||
|
||||
void boot_led_on(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
uint32_t pin = LED_BOOT_PIN;
|
||||
RCC_AHB2_CLOCK_ER |= GPIOB_AHB2_CLOCK_ER;
|
||||
reg = GPIOB_MODE & ~(0x03 << (pin * 2));
|
||||
GPIOB_MODE = reg | (1 << (pin * 2));
|
||||
reg = GPIOB_PUPD & ~(0x03 << (pin * 2));
|
||||
GPIOB_PUPD = reg | (1 << (pin * 2));
|
||||
GPIOB_BSRR |= (1 << pin);
|
||||
}
|
||||
|
||||
void boot_led_off(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
uint32_t pin = LED_BOOT_PIN;
|
||||
GPIOB_BSRR |= (1 << (pin + 16));
|
||||
}
|
||||
|
||||
|
||||
#endif /* PLATFORM_stm32wb */
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* led.h
|
||||
*
|
||||
* Test bare-metal blinking led application
|
||||
*
|
||||
* Copyright (C) 2020 wolfSSL Inc.
|
||||
*
|
||||
* This file is part of wolfBoot.
|
||||
*
|
||||
* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* wolfBoot is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
|
||||
*/
|
||||
|
||||
#ifndef GPIO_H_INCLUDED
|
||||
#define GPIO_H_INCLUDED
|
||||
|
||||
int led_setup(void);
|
||||
void led_on(void);
|
||||
void led_off(void);
|
||||
void led_toggle(void);
|
||||
void led_pwm_setup(void);
|
||||
void boot_led_on(void);
|
||||
void boot_led_off(void);
|
||||
|
||||
#endif /* !GPIO_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,337 @@
|
|||
/* startup_arm.c
|
||||
*
|
||||
* Test bare-metal blinking led application
|
||||
*
|
||||
* Copyright (C) 2020 wolfSSL Inc.
|
||||
*
|
||||
* This file is part of wolfBoot.
|
||||
*
|
||||
* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* wolfBoot is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
|
||||
*/
|
||||
|
||||
extern unsigned int _stored_data;
|
||||
extern unsigned int _start_data;
|
||||
extern unsigned int _end_data;
|
||||
extern unsigned int _start_bss;
|
||||
extern unsigned int _end_bss;
|
||||
extern unsigned int _end_stack;
|
||||
extern unsigned int _start_heap;
|
||||
|
||||
static int zeroed_variable_in_bss;
|
||||
static int initialized_variable_in_data = 42;
|
||||
|
||||
extern void isr_tim2(void);
|
||||
|
||||
#define STACK_PAINTING
|
||||
|
||||
static volatile unsigned int avail_mem = 0;
|
||||
static unsigned int sp;
|
||||
|
||||
extern void main(void);
|
||||
|
||||
void isr_reset(void) {
|
||||
register unsigned int *src, *dst;
|
||||
src = (unsigned int *) &_stored_data;
|
||||
dst = (unsigned int *) &_start_data;
|
||||
while (dst < (unsigned int *)&_end_data) {
|
||||
*dst = *src;
|
||||
dst++;
|
||||
src++;
|
||||
}
|
||||
|
||||
dst = &_start_bss;
|
||||
while (dst < (unsigned int *)&_end_bss) {
|
||||
*dst = 0U;
|
||||
dst++;
|
||||
}
|
||||
|
||||
avail_mem = &_end_stack - &_start_heap;
|
||||
#ifdef STACK_PAINTING
|
||||
{
|
||||
asm volatile("mrs %0, msp" : "=r"(sp));
|
||||
dst = ((unsigned int *)(&_end_stack)) - (8192 / sizeof(unsigned int)); ;
|
||||
while ((unsigned int)dst < sp) {
|
||||
*dst = 0xDEADC0DE;
|
||||
dst++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
main();
|
||||
}
|
||||
|
||||
void isr_fault(void)
|
||||
{
|
||||
/* Panic. */
|
||||
while(1) ;;
|
||||
|
||||
}
|
||||
|
||||
void isr_memfault(void)
|
||||
{
|
||||
/* Panic. */
|
||||
while(1) ;;
|
||||
}
|
||||
|
||||
void isr_busfault(void)
|
||||
{
|
||||
/* Panic. */
|
||||
while(1) ;;
|
||||
}
|
||||
|
||||
void isr_usagefault(void)
|
||||
{
|
||||
/* Panic. */
|
||||
while(1) ;;
|
||||
}
|
||||
|
||||
|
||||
void isr_empty(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
__attribute__ ((section(".isr_vector")))
|
||||
void (* const IV[])(void) =
|
||||
{
|
||||
(void (*)(void))(&_end_stack),
|
||||
isr_reset, // Reset
|
||||
isr_fault, // NMI
|
||||
isr_fault, // HardFault
|
||||
isr_memfault, // MemFault
|
||||
isr_busfault, // BusFault
|
||||
isr_usagefault, // UsageFault
|
||||
0, // SecureFault
|
||||
0, // reserved
|
||||
0, // reserved
|
||||
0, // reserved
|
||||
isr_empty, // SVC
|
||||
isr_empty, // DebugMonitor
|
||||
0, // reserved
|
||||
isr_empty, // PendSV
|
||||
isr_empty, // SysTick
|
||||
|
||||
/* Device specific IRQs for LM3S */
|
||||
|
||||
#ifdef LM3S
|
||||
isr_empty, // GPIO Port A
|
||||
isr_empty, // GPIO Port B
|
||||
isr_empty, // GPIO Port C
|
||||
isr_empty, // GPIO Port D
|
||||
isr_empty, // GPIO Port E
|
||||
isr_empty, // UART0 Rx and Tx
|
||||
isr_empty, // UART1 Rx and Tx
|
||||
isr_empty, // SSI0 Rx and Tx
|
||||
isr_empty, // I2C0 Master and Slave
|
||||
isr_empty, // PWM Fault
|
||||
isr_empty, // PWM Generator 0
|
||||
isr_empty, // PWM Generator 1
|
||||
isr_empty, // PWM Generator 2
|
||||
isr_empty, // Quadrature Encoder 0
|
||||
isr_empty, // ADC Sequence 0
|
||||
isr_empty, // ADC Sequence 1
|
||||
isr_empty, // ADC Sequence 2
|
||||
isr_empty, // ADC Sequence 3
|
||||
isr_empty, // Watchdog timer
|
||||
isr_empty, // Timer 0 subtimer A
|
||||
isr_empty, // Timer 0 subtimer B
|
||||
isr_empty, // Timer 1 subtimer A
|
||||
isr_empty, // Timer 1 subtimer B
|
||||
isr_empty, // Timer 2 subtimer A
|
||||
isr_empty, // Timer 3 subtimer B
|
||||
isr_empty, // Analog Comparator 0
|
||||
isr_empty, // Analog Comparator 1
|
||||
isr_empty, // Analog Comparator 2
|
||||
isr_empty, // System Control (PLL, OSC, BO)
|
||||
isr_empty, // FLASH Control
|
||||
isr_empty, // GPIO Port F
|
||||
isr_empty, // GPIO Port G
|
||||
isr_empty, // GPIO Port H
|
||||
isr_empty, // UART2 Rx and Tx
|
||||
isr_empty, // SSI1 Rx and Tx
|
||||
isr_empty, // Timer 3 subtimer A
|
||||
isr_empty, // Timer 3 subtimer B
|
||||
isr_empty, // I2C1 Master and Slave
|
||||
isr_empty, // Quadrature Encoder 1
|
||||
isr_empty, // CAN0
|
||||
isr_empty, // CAN1
|
||||
isr_empty, // CAN2
|
||||
isr_empty, // Ethernet
|
||||
isr_empty, // Hibernate
|
||||
#elif PLATFORM_stm32l5
|
||||
isr_empty, // WWDG_IRQHandler
|
||||
isr_empty, // PVD_PVM_IRQHandler
|
||||
isr_empty, // RTC_IRQHandler
|
||||
isr_empty, // RTC_S_IRQHandler
|
||||
isr_empty, // TAMP_IRQHandler
|
||||
isr_empty, // TAMP_S_IRQHandler
|
||||
isr_empty, // FLASH_IRQHandler
|
||||
isr_empty, // FLASH_S_IRQHandler
|
||||
isr_empty, // GTZC_IRQHandler
|
||||
isr_empty, // RCC_IRQHandler
|
||||
isr_empty, // RCC_S_IRQHandler
|
||||
isr_empty, // EXTI0_IRQHandler
|
||||
isr_empty, // EXTI1_IRQHandler
|
||||
isr_empty, // EXTI2_IRQHandler
|
||||
isr_empty, // EXTI3_IRQHandler
|
||||
isr_empty, // EXTI4_IRQHandler
|
||||
isr_empty, // EXTI5_IRQHandler
|
||||
isr_empty, // EXTI6_IRQHandler
|
||||
isr_empty, // EXTI7_IRQHandler
|
||||
isr_empty, // EXTI8_IRQHandler
|
||||
isr_empty, // EXTI9_IRQHandler
|
||||
isr_empty, // EXTI10_IRQHandler
|
||||
isr_empty, // EXTI11_IRQHandler
|
||||
isr_empty, // EXTI12_IRQHandler
|
||||
isr_empty, // EXTI13_IRQHandler
|
||||
isr_empty, // EXTI14_IRQHandler
|
||||
isr_empty, // EXTI15_IRQHandler
|
||||
isr_empty, // DMAMUX1_IRQHandler
|
||||
isr_empty, // DMAMUX1_S_IRQHandler
|
||||
isr_empty, // DMA1_Channel1_IRQHandler
|
||||
isr_empty, // DMA1_Channel2_IRQHandler
|
||||
isr_empty, // DMA1_Channel3_IRQHandler
|
||||
isr_empty, // DMA1_Channel4_IRQHandler
|
||||
isr_empty, // DMA1_Channel5_IRQHandler
|
||||
isr_empty, // DMA1_Channel6_IRQHandler
|
||||
isr_empty, // DMA1_Channel7_IRQHandler
|
||||
isr_empty, // DMA1_Channel8_IRQHandler
|
||||
isr_empty, // ADC1_2_IRQHandler
|
||||
isr_empty, // DAC_IRQHandler
|
||||
isr_empty, // FDCAN1_IT0_IRQHandler
|
||||
isr_empty, // FDCAN1_IT1_IRQHandler
|
||||
isr_empty, // TIM1_BRK_IRQHandler
|
||||
isr_empty, // TIM1_UP_IRQHandler
|
||||
isr_empty, // TIM1_TRG_COM_IRQHandler
|
||||
isr_empty, // TIM1_CC_IRQHandler
|
||||
isr_empty, // TIM2_IRQHandler
|
||||
isr_empty, // TIM3_IRQHandler
|
||||
isr_empty, // TIM4_IRQHandler
|
||||
isr_empty, // TIM5_IRQHandler
|
||||
isr_empty, // TIM6_IRQHandler
|
||||
isr_empty, // TIM7_IRQHandler
|
||||
isr_empty, // TIM8_BRK_IRQHandler
|
||||
isr_empty, // TIM8_UP_IRQHandler
|
||||
isr_empty, // TIM8_TRG_COM_IRQHandler
|
||||
isr_empty, // TIM8_CC_IRQHandler
|
||||
isr_empty, // I2C1_EV_IRQHandler
|
||||
isr_empty, // I2C1_ER_IRQHandler
|
||||
isr_empty, // I2C2_EV_IRQHandler
|
||||
isr_empty, // I2C2_ER_IRQHandler
|
||||
isr_empty, // SPI1_IRQHandler
|
||||
isr_empty, // SPI2_IRQHandler
|
||||
isr_empty, // USART1_IRQHandler
|
||||
isr_empty, // USART2_IRQHandler
|
||||
isr_empty, // USART3_IRQHandler
|
||||
isr_empty, // UART4_IRQHandler
|
||||
isr_empty, // UART5_IRQHandler
|
||||
isr_empty, // LPUART1_IRQHandler
|
||||
isr_empty, // LPTIM1_IRQHandler
|
||||
isr_empty, // LPTIM2_IRQHandler
|
||||
isr_empty, // TIM15_IRQHandler
|
||||
isr_empty, // TIM16_IRQHandler
|
||||
isr_empty, // TIM17_IRQHandler
|
||||
isr_empty, // COMP_IRQHandler
|
||||
isr_empty, // USB_FS_IRQHandler
|
||||
isr_empty, // CRS_IRQHandler
|
||||
isr_empty, // FMC_IRQHandler
|
||||
isr_empty, // OCTOSPI1_IRQHandler
|
||||
isr_empty, // 0
|
||||
isr_empty, // SDMMC1_IRQHandler
|
||||
isr_empty, // 0
|
||||
isr_empty, // DMA2_Channel1_IRQHandler
|
||||
isr_empty, // DMA2_Channel2_IRQHandler
|
||||
isr_empty, // DMA2_Channel3_IRQHandler
|
||||
isr_empty, // DMA2_Channel4_IRQHandler
|
||||
isr_empty, // DMA2_Channel5_IRQHandler
|
||||
isr_empty, // DMA2_Channel6_IRQHandler
|
||||
isr_empty, // DMA2_Channel7_IRQHandler
|
||||
isr_empty, // DMA2_Channel8_IRQHandler
|
||||
isr_empty, // I2C3_EV_IRQHandler
|
||||
isr_empty, // I2C3_ER_IRQHandler
|
||||
isr_empty, // SAI1_IRQHandler
|
||||
isr_empty, // SAI2_IRQHandler
|
||||
isr_empty, // TSC_IRQHandler
|
||||
isr_empty, // AES_IRQHandler
|
||||
isr_empty, // RNG_IRQHandler
|
||||
isr_empty, // FPU_IRQHandler
|
||||
isr_empty, // HASH_IRQHandler
|
||||
isr_empty, // PKA_IRQHandler
|
||||
isr_empty, // LPTIM3_IRQHandler
|
||||
isr_empty, // SPI3_IRQHandler
|
||||
isr_empty, // I2C4_ER_IRQHandler
|
||||
isr_empty, // I2C4_EV_IRQHandler
|
||||
isr_empty, // DFSDM1_FLT0_IRQHandler
|
||||
isr_empty, // DFSDM1_FLT1_IRQHandler
|
||||
isr_empty, // DFSDM1_FLT2_IRQHandler
|
||||
isr_empty, // DFSDM1_FLT3_IRQHandler
|
||||
isr_empty, // UCPD1_IRQHandler
|
||||
isr_empty, // ICACHE_IRQHandler
|
||||
isr_empty, // OTFDEC1_IRQHandler
|
||||
#else /* For STM32F4 */
|
||||
isr_empty, // NVIC_WWDG_IRQ 0
|
||||
isr_empty, // PVD_IRQ 1
|
||||
isr_empty, // TAMP_STAMP_IRQ 2
|
||||
isr_empty, // RTC_WKUP_IRQ 3
|
||||
isr_empty, // FLASH_IRQ 4
|
||||
isr_empty, // RCC_IRQ 5
|
||||
isr_empty, // EXTI0_IRQ 6
|
||||
isr_empty, // EXTI1_IRQ 7
|
||||
isr_empty, // EXTI2_IRQ 8
|
||||
isr_empty, // EXTI3_IRQ 9
|
||||
isr_empty, // EXTI4_IRQ 10
|
||||
isr_empty, // DMA1_STREAM0_IRQ 11
|
||||
isr_empty, // DMA1_STREAM1_IRQ 12
|
||||
isr_empty, // DMA1_STREAM2_IRQ 13
|
||||
isr_empty, // DMA1_STREAM3_IRQ 14
|
||||
isr_empty, // DMA1_STREAM4_IRQ 15
|
||||
isr_empty, // DMA1_STREAM5_IRQ 16
|
||||
isr_empty, // DMA1_STREAM6_IRQ 17
|
||||
isr_empty, // ADC_IRQ 18
|
||||
isr_empty, // CAN1_TX_IRQ 19
|
||||
isr_empty, // CAN1_RX0_IRQ 20
|
||||
isr_empty, // CAN1_RX1_IRQ 21
|
||||
isr_empty, // CAN1_SCE_IRQ 22
|
||||
isr_empty, // EXTI9_5_IRQ 23
|
||||
isr_empty, // TIM1_BRK_TIM9_IRQ 24
|
||||
isr_empty, // TIM1_UP_TIM10_IRQ 25
|
||||
isr_empty, // TIM1_TRG_COM_TIM11_IRQ 26
|
||||
isr_empty, // TIM1_CC_IRQ 27
|
||||
isr_tim2, // TIM2_IRQ 28
|
||||
isr_empty, // TIM3_IRQ 29
|
||||
isr_empty, // TIM4_IRQ 30
|
||||
isr_empty, // I2C1_EV_IRQ 31
|
||||
isr_empty, // I2C1_ER_IRQ 32
|
||||
isr_empty, // I2C2_EV_IRQ 33
|
||||
isr_empty, // I2C2_ER_IRQ 34
|
||||
isr_empty, // SPI1_IRQ 35
|
||||
isr_empty, // SPI2_IRQ 36
|
||||
isr_empty, // USART1_IRQ 37
|
||||
isr_empty, // USART2_IRQ 38
|
||||
isr_empty, // USART3_IRQ 39
|
||||
isr_empty, // EXTI15_10_IRQ 40
|
||||
isr_empty, // RTC_ALARM_IRQ 41
|
||||
isr_empty, // USB_FS_WKUP_IRQ 42
|
||||
isr_empty, // TIM8_BRK_TIM12_IRQ 43
|
||||
isr_empty, // TIM8_UP_TIM13_IRQ 44
|
||||
isr_empty, // TIM8_TRG_COM_TIM14_IRQ 45
|
||||
isr_empty, // TIM8_CC_IRQ 46
|
||||
isr_empty, // DMA1_STREAM7_IRQ 47
|
||||
|
||||
#endif
|
||||
};
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
/* system.c
|
||||
*
|
||||
* Test bare-metal blinking led application
|
||||
*
|
||||
* Copyright (C) 2020 wolfSSL Inc.
|
||||
*
|
||||
* This file is part of wolfBoot.
|
||||
*
|
||||
* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* wolfBoot is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
|
||||
*/
|
||||
#if defined(PLATFORM_stm32f4) || defined(PLATFORM_stm32f7)
|
||||
#include <stdint.h>
|
||||
#include "system.h"
|
||||
|
||||
/*** FLASH ***/
|
||||
#define FLASH_BASE (0x40023C00)
|
||||
#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
|
||||
#define FLASH_ACR_ENABLE_DATA_CACHE (1 << 10)
|
||||
#define FLASH_ACR_ENABLE_INST_CACHE (1 << 9)
|
||||
|
||||
/*** RCC ***/
|
||||
|
||||
#define RCC_BASE (0x40023800)
|
||||
#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00))
|
||||
#define RCC_PLLCFGR (*(volatile uint32_t *)(RCC_BASE + 0x04))
|
||||
#define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08))
|
||||
#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00))
|
||||
|
||||
#define RCC_CR_PLLRDY (1 << 25)
|
||||
#define RCC_CR_PLLON (1 << 24)
|
||||
#define RCC_CR_HSERDY (1 << 17)
|
||||
#define RCC_CR_HSEON (1 << 16)
|
||||
#define RCC_CR_HSIRDY (1 << 1)
|
||||
#define RCC_CR_HSION (1 << 0)
|
||||
|
||||
#define RCC_CFGR_SW_HSI 0x0
|
||||
#define RCC_CFGR_SW_HSE 0x1
|
||||
#define RCC_CFGR_SW_PLL 0x2
|
||||
|
||||
|
||||
#define RCC_PLLCFGR_PLLSRC (1 << 22)
|
||||
|
||||
#define RCC_PRESCALER_DIV_NONE 0
|
||||
#define RCC_PRESCALER_DIV_2 8
|
||||
#define RCC_PRESCALER_DIV_4 9
|
||||
|
||||
|
||||
/* STM32F4-Discovery, 168 MHz */
|
||||
#ifdef PLATFORM_stm32f4
|
||||
# define PLLM 8
|
||||
# define PLLN 336
|
||||
# define PLLP 2
|
||||
# define PLLQ 7
|
||||
# define PLLR 0
|
||||
# define TARGET_FLASH_WAITSTATES 5
|
||||
#endif
|
||||
|
||||
/* STM32F7-Discovery, 216 MHz */
|
||||
#ifdef PLATFORM_stm32f7
|
||||
# define PLLM 25
|
||||
# define PLLN 432
|
||||
# define PLLP 2
|
||||
# define PLLQ 9
|
||||
# define PLLR 0
|
||||
# define TARGET_FLASH_WAITSTATES 7
|
||||
#endif
|
||||
|
||||
void flash_set_waitstates(void)
|
||||
{
|
||||
FLASH_ACR |= TARGET_FLASH_WAITSTATES | FLASH_ACR_ENABLE_DATA_CACHE | FLASH_ACR_ENABLE_INST_CACHE;
|
||||
}
|
||||
|
||||
|
||||
void clock_config(void)
|
||||
{
|
||||
uint32_t reg32;
|
||||
/* Enable internal high-speed oscillator. */
|
||||
RCC_CR |= RCC_CR_HSION;
|
||||
DMB();
|
||||
while ((RCC_CR & RCC_CR_HSIRDY) == 0) {};
|
||||
|
||||
/* Select HSI as SYSCLK source. */
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 1) | (1 << 0));
|
||||
RCC_CFGR = (reg32 | RCC_CFGR_SW_HSI);
|
||||
DMB();
|
||||
|
||||
/* Enable external high-speed oscillator 8MHz. */
|
||||
RCC_CR |= RCC_CR_HSEON;
|
||||
DMB();
|
||||
while ((RCC_CR & RCC_CR_HSERDY) == 0) {};
|
||||
|
||||
/*
|
||||
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
||||
*/
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~(0xF0);
|
||||
RCC_CFGR = (reg32 | (RCC_PRESCALER_DIV_NONE << 4));
|
||||
DMB();
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~(0x1C00);
|
||||
RCC_CFGR = (reg32 | (RCC_PRESCALER_DIV_2 << 10));
|
||||
DMB();
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~(0x07 << 13);
|
||||
RCC_CFGR = (reg32 | (RCC_PRESCALER_DIV_4 << 13));
|
||||
DMB();
|
||||
|
||||
/* Set PLL config */
|
||||
reg32 = RCC_PLLCFGR;
|
||||
reg32 &= ~(PLL_FULL_MASK);
|
||||
RCC_PLLCFGR = reg32 | RCC_PLLCFGR_PLLSRC | PLLM |
|
||||
(PLLN << 6) | (((PLLP >> 1) - 1) << 16) |
|
||||
(PLLQ << 24);
|
||||
DMB();
|
||||
/* Enable PLL oscillator and wait for it to stabilize. */
|
||||
RCC_CR |= RCC_CR_PLLON;
|
||||
DMB();
|
||||
while ((RCC_CR & RCC_CR_PLLRDY) == 0) {};
|
||||
|
||||
/* Select PLL as SYSCLK source. */
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 1) | (1 << 0));
|
||||
RCC_CFGR = (reg32 | RCC_CFGR_SW_PLL);
|
||||
DMB();
|
||||
|
||||
/* Wait for PLL clock to be selected. */
|
||||
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_PLL) {};
|
||||
|
||||
/* Disable internal high-speed oscillator. */
|
||||
RCC_CR &= ~RCC_CR_HSION;
|
||||
}
|
||||
|
||||
#endif /* PLATFORM_stm32f4 */
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/* system.h
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2020 wolfSSL Inc.
|
||||
*
|
||||
* This file is part of wolfBoot.
|
||||
*
|
||||
* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* wolfBoot is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_H_INCLUDED
|
||||
#define SYSTEM_H_INCLUDED
|
||||
|
||||
/* System specific: PLL with 8 MHz external oscillator, CPU at 168MHz */
|
||||
#define CPU_FREQ (168000000)
|
||||
#define PLL_FULL_MASK (0x7F037FFF)
|
||||
|
||||
/* Assembly helpers */
|
||||
#define DMB() asm volatile ("dmb");
|
||||
#define WFI() asm volatile ("wfi");
|
||||
|
||||
/* Master clock setting */
|
||||
void clock_config(void);
|
||||
void flash_set_waitstates(void);
|
||||
|
||||
|
||||
/* NVIC */
|
||||
/* NVIC ISER Base register (Cortex-M) */
|
||||
|
||||
#define NVIC_TIM2_IRQN (28)
|
||||
#define NVIC_ISER_BASE (0xE000E100)
|
||||
#define NVIC_ICER_BASE (0xE000E180)
|
||||
#define NVIC_IPRI_BASE (0xE000E400)
|
||||
|
||||
static inline void nvic_irq_enable(uint8_t n)
|
||||
{
|
||||
int i = n / 32;
|
||||
volatile uint32_t *nvic_iser = ((volatile uint32_t *)(NVIC_ISER_BASE + 4 * i));
|
||||
*nvic_iser |= (1 << (n % 32));
|
||||
}
|
||||
|
||||
static inline void nvic_irq_disable(uint8_t n)
|
||||
{
|
||||
int i = n / 32;
|
||||
volatile uint32_t *nvic_icer = ((volatile uint32_t *)(NVIC_ICER_BASE + 4 * i));
|
||||
*nvic_icer |= (1 << (n % 32));
|
||||
}
|
||||
|
||||
static inline void nvic_irq_setprio(uint8_t n, uint8_t prio)
|
||||
{
|
||||
volatile uint8_t *nvic_ipri = ((volatile uint8_t *)(NVIC_IPRI_BASE + n));
|
||||
*nvic_ipri = prio;
|
||||
}
|
||||
|
||||
#endif /* !SYSTEM_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x20100, LENGTH = 0x1FF00
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 16K /* Run in lowmem */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
_start_text = .;
|
||||
KEEP(*(.isr_vector))
|
||||
*(.init)
|
||||
*(.fini)
|
||||
*(.text*)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
_end_text = .;
|
||||
} > FLASH
|
||||
|
||||
_stored_data = .;
|
||||
|
||||
.data : AT (_stored_data)
|
||||
{
|
||||
_start_data = .;
|
||||
KEEP(*(.data*))
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.ramcode))
|
||||
. = ALIGN(4);
|
||||
_end_data = .;
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
_start_bss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_end_bss = .;
|
||||
_end = .;
|
||||
} > RAM
|
||||
}
|
||||
|
||||
PROVIDE(_start_heap = _end);
|
||||
PROVIDE(_end_stack = ORIGIN(RAM) + LENGTH(RAM));
|
||||
|
|
@ -0,0 +1,171 @@
|
|||
/* timer.c
|
||||
*
|
||||
* Test bare-metal blinking led application
|
||||
*
|
||||
* Copyright (C) 2020 wolfSSL Inc.
|
||||
*
|
||||
* This file is part of wolfBoot.
|
||||
*
|
||||
* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* wolfBoot is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
|
||||
*/
|
||||
|
||||
#ifdef PLATFORM_stm32f4
|
||||
#include <stdint.h>
|
||||
|
||||
#include "system.h"
|
||||
#include "led.h"
|
||||
|
||||
|
||||
/* STM32 specific defines */
|
||||
#define APB1_CLOCK_ER (*(volatile uint32_t *)(0x40023840))
|
||||
#define APB1_CLOCK_RST (*(volatile uint32_t *)(0x40023820))
|
||||
#define TIM4_APB1_CLOCK_ER_VAL (1 << 2)
|
||||
#define TIM2_APB1_CLOCK_ER_VAL (1 << 0)
|
||||
|
||||
#define TIM2_BASE (0x40000000)
|
||||
#define TIM2_CR1 (*(volatile uint32_t *)(TIM2_BASE + 0x00))
|
||||
#define TIM2_DIER (*(volatile uint32_t *)(TIM2_BASE + 0x0c))
|
||||
#define TIM2_SR (*(volatile uint32_t *)(TIM2_BASE + 0x10))
|
||||
#define TIM2_PSC (*(volatile uint32_t *)(TIM2_BASE + 0x28))
|
||||
#define TIM2_ARR (*(volatile uint32_t *)(TIM2_BASE + 0x2c))
|
||||
|
||||
#define TIM4_BASE (0x40000800)
|
||||
#define TIM4_CR1 (*(volatile uint32_t *)(TIM4_BASE + 0x00))
|
||||
#define TIM4_DIER (*(volatile uint32_t *)(TIM4_BASE + 0x0c))
|
||||
#define TIM4_SR (*(volatile uint32_t *)(TIM4_BASE + 0x10))
|
||||
#define TIM4_CCMR1 (*(volatile uint32_t *)(TIM4_BASE + 0x18))
|
||||
#define TIM4_CCMR2 (*(volatile uint32_t *)(TIM4_BASE + 0x1c))
|
||||
#define TIM4_CCER (*(volatile uint32_t *)(TIM4_BASE + 0x20))
|
||||
#define TIM4_PSC (*(volatile uint32_t *)(TIM4_BASE + 0x28))
|
||||
#define TIM4_ARR (*(volatile uint32_t *)(TIM4_BASE + 0x2c))
|
||||
#define TIM4_CCR4 (*(volatile uint32_t *)(TIM4_BASE + 0x40))
|
||||
|
||||
#define TIM_DIER_UIE (1 << 0)
|
||||
#define TIM_SR_UIF (1 << 0)
|
||||
#define TIM_CR1_CLOCK_ENABLE (1 << 0)
|
||||
#define TIM_CR1_UPD_RS (1 << 2)
|
||||
#define TIM_CR1_ARPE (1 << 7)
|
||||
|
||||
#define TIM_CCER_CC4_ENABLE (1 << 12)
|
||||
#define TIM_CCMR1_OC1M_PWM1 (0x06 << 4)
|
||||
#define TIM_CCMR2_OC4M_PWM1 (0x06 << 12)
|
||||
|
||||
#define AHB1_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
|
||||
#define GPIOD_AHB1_CLOCK_ER (1 << 3)
|
||||
|
||||
#define GPIOD_BASE 0x40020c00
|
||||
#define GPIOD_MODE (*(volatile uint32_t *)(GPIOD_BASE + 0x00))
|
||||
#define GPIOD_OTYPE (*(volatile uint32_t *)(GPIOD_BASE + 0x04))
|
||||
#define GPIOD_PUPD (*(volatile uint32_t *)(GPIOD_BASE + 0x0c))
|
||||
#define GPIOD_ODR (*(volatile uint32_t *)(GPIOD_BASE + 0x14))
|
||||
|
||||
static uint32_t master_clock = 0;
|
||||
|
||||
/** Use TIM4_CH4, which is linked to PD15 AF1 **/
|
||||
int pwm_init(uint32_t clock, uint32_t threshold)
|
||||
{
|
||||
uint32_t val = (clock / 100000); /* Frequency is 100 KHz */
|
||||
uint32_t lvl;
|
||||
master_clock = clock;
|
||||
|
||||
if (threshold > 100)
|
||||
return -1;
|
||||
|
||||
lvl = (val * threshold) / 100;
|
||||
if (lvl != 0)
|
||||
lvl--;
|
||||
|
||||
APB1_CLOCK_RST |= TIM4_APB1_CLOCK_ER_VAL;
|
||||
asm volatile ("dmb");
|
||||
APB1_CLOCK_RST &= ~TIM4_APB1_CLOCK_ER_VAL;
|
||||
APB1_CLOCK_ER |= TIM4_APB1_CLOCK_ER_VAL;
|
||||
|
||||
/* disable CC */
|
||||
TIM4_CCER &= ~TIM_CCER_CC4_ENABLE;
|
||||
TIM4_CR1 = 0;
|
||||
TIM4_PSC = 0;
|
||||
TIM4_ARR = val - 1;
|
||||
TIM4_CCR4 = lvl;
|
||||
TIM4_CCMR1 &= ~(0x03 << 0);
|
||||
TIM4_CCMR1 &= ~(0x07 << 4);
|
||||
TIM4_CCMR1 |= TIM_CCMR1_OC1M_PWM1;
|
||||
TIM4_CCMR2 &= ~(0x03 << 8);
|
||||
TIM4_CCMR2 &= ~(0x07 << 12);
|
||||
TIM4_CCMR2 |= TIM_CCMR2_OC4M_PWM1;
|
||||
TIM4_CCER |= TIM_CCER_CC4_ENABLE;
|
||||
TIM4_CR1 |= TIM_CR1_CLOCK_ENABLE | TIM_CR1_ARPE;
|
||||
asm volatile ("dmb");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int timer_init(uint32_t clock, uint32_t prescaler, uint32_t interval_ms)
|
||||
{
|
||||
uint32_t val = 0;
|
||||
uint32_t psc = 1;
|
||||
uint32_t err = 0;
|
||||
clock = ((clock * prescaler) / 1000) * interval_ms;
|
||||
|
||||
while (psc < 65535) {
|
||||
val = clock / psc;
|
||||
err = clock % psc;
|
||||
if ((val < 65535) && (err == 0)) {
|
||||
val--;
|
||||
break;
|
||||
}
|
||||
val = 0;
|
||||
psc++;
|
||||
}
|
||||
if (val == 0)
|
||||
return -1;
|
||||
|
||||
nvic_irq_enable(NVIC_TIM2_IRQN);
|
||||
nvic_irq_setprio(NVIC_TIM2_IRQN, 0);
|
||||
APB1_CLOCK_RST |= TIM2_APB1_CLOCK_ER_VAL;
|
||||
asm volatile ("dmb");
|
||||
APB1_CLOCK_RST &= ~TIM2_APB1_CLOCK_ER_VAL;
|
||||
APB1_CLOCK_ER |= TIM2_APB1_CLOCK_ER_VAL;
|
||||
|
||||
TIM2_CR1 = 0;
|
||||
asm volatile ("dmb");
|
||||
TIM2_PSC = psc;
|
||||
TIM2_ARR = val;
|
||||
TIM2_CR1 |= TIM_CR1_CLOCK_ENABLE;
|
||||
TIM2_DIER |= TIM_DIER_UIE;
|
||||
asm volatile ("dmb");
|
||||
return 0;
|
||||
}
|
||||
|
||||
extern volatile uint32_t time_elapsed;
|
||||
void isr_tim2(void)
|
||||
{
|
||||
static volatile uint32_t tim2_ticks = 0;
|
||||
TIM2_SR &= ~TIM_SR_UIF;
|
||||
|
||||
/* Dim the led by altering the PWM duty-cicle */
|
||||
if (++tim2_ticks > 15)
|
||||
tim2_ticks = 0;
|
||||
if (tim2_ticks > 8)
|
||||
pwm_init(master_clock, 10 * (16 - tim2_ticks));
|
||||
else
|
||||
pwm_init(master_clock, 10 * tim2_ticks);
|
||||
|
||||
time_elapsed++;
|
||||
}
|
||||
#else
|
||||
void isr_tim2(void)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* PLATFORM_stm32f4 */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* timer.h
|
||||
*
|
||||
* Test bare-metal blinking led application
|
||||
*
|
||||
* Copyright (C) 2020 wolfSSL Inc.
|
||||
*
|
||||
* This file is part of wolfBoot.
|
||||
*
|
||||
* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* wolfBoot is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
|
||||
*/
|
||||
|
||||
#ifndef TIMER_H_INCLUDED
|
||||
#define TIMER_H_INCLUDED
|
||||
|
||||
int pwm_init(uint32_t clock, uint32_t threshold);
|
||||
int timer_init(uint32_t clock, uint32_t scaler, uint32_t interval);
|
||||
|
||||
#endif /* !TIMER_H_INCLUDED */
|
||||
Loading…
Reference in New Issue