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ARMASM. Macros for clocks+gpios. Set MAC pins.

pull/508/head
Daniele Lacamera 2024-10-07 15:43:20 +02:00 committed by Daniele Lacamera
parent b97abd4ace
commit 07bdae680a
6 changed files with 81 additions and 33 deletions
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8
arch.mk
View File

@ -68,7 +68,8 @@ endif
ifeq ($(ARCH),ARM)
CROSS_COMPILE?=arm-none-eabi-
CFLAGS+=-mthumb -mlittle-endian -mthumb-interwork -DARCH_ARM
CFLAGS+=-DARCH_ARM
CFLAGS+=-mthumb -mlittle-endian -mthumb-interwork
LDFLAGS+=-mthumb -mlittle-endian -mthumb-interwork
## Target specific configuration
@ -194,7 +195,10 @@ ifeq ($(CORTEX_A5),1)
MATH_OBJS+=./lib/wolfssl/wolfcrypt/src/sp_c32.o
else
MATH_OBJS+=./lib/wolfssl/wolfcrypt/src/sp_arm32.o
CFLAGS+=-DWOLFSSL_SP_ARM32_ASM
OBJS+=./lib/wolfssl/wolfcrypt/src/port/arm/armv8-sha256.o
OBJS+=./lib/wolfssl/wolfcrypt/src/port/arm/armv8-32-sha256-asm.o
OBJS+=./lib/wolfssl/wolfcrypt/src/port/arm/armv8-32-sha256-asm_c.o
CFLAGS+=-DWOLFSSL_SP_ARM32_ASM -DWOLFSSL_ARMASM -DWOLFSSL_ARMASM_NO_HW_CRYPTO -DWOLFSSL_ARM_ARCH=7 -DWOLFSSL_ARMASM_INLINE -DWOLFSSL_ARMASM_NO_NEON
endif
else
# All others use boot_arm.o

35
hal/sama5d3.c
View File

@ -195,6 +195,31 @@ static void pll_init(void)
master_clock_set(PRESCALER_PLLA_CLOCK);
}
/* GMAC PINS: PB8, PB11, PB16, PB18 */
/* EMAC PINS: PC7, PC8 */
#define GMAC_PINS ( (1 << 8) | (1 << 11) | (1 << 16) | (1 << 18) )
#define EMAC_PINS ( (1 << 7) | (1 << 8) )
#define GPIO_GMAC GPIOB
#define GPIO_EMAC GPIOC
static void mac_init(void)
{
PMC_CLOCK_EN(GPIOB_PMCID);
PMC_CLOCK_EN(GPIOC_PMCID);
GPIO_PPUDR(GPIO_GMAC) = GMAC_PINS;
GPIO_PPDDR(GPIO_GMAC) = GMAC_PINS;
GPIO_PER(GPIO_GMAC) = GMAC_PINS;
GPIO_OER(GPIO_GMAC) = GMAC_PINS;
GPIO_CODR(GPIO_GMAC) = GMAC_PINS;
GPIO_PPUDR(GPIO_EMAC) = EMAC_PINS;
GPIO_PPDDR(GPIO_EMAC) = EMAC_PINS;
GPIO_PER(GPIO_EMAC) = EMAC_PINS;
GPIO_OER(GPIO_EMAC) = EMAC_PINS;
GPIO_CODR(GPIO_EMAC) = EMAC_PINS;
}
static void ddr_init(void)
{
@ -245,10 +270,7 @@ static void ddr_init(void)
*
*/
/* Turn on the DDRAM controller peripheral clock */
PMC_PCR = MPDDRC_PMCID;
pmc_pcr = PMC_PCR & (~PMC_PCR_DIV_MASK);
pmc_pcr |= PMC_PCR_CMD | PMC_PCR_EN;
PMC_PCR = pmc_pcr;
PMC_CLOCK_EN(MPDDRC_PMCID);
/* Enable DDR in system clock */
PMC_SCER = MPDDRC_SCERID;
@ -649,10 +671,7 @@ void pit_init(void)
uint32_t pmc_pcr;
/* Turn on clock for PIT */
PMC_PCR = PIT_PMCID;
pmc_pcr = PMC_PCR & (~PMC_PCR_DIV_MASK);
pmc_pcr |= PMC_PCR_CMD | PMC_PCR_EN;
PMC_PCR = pmc_pcr;
PMC_CLOCK_EN(PIT_PMCID);
/* Set clock source to MCK/2 */
PIT_MR = MAX_PIV | PIT_MR_EN;

52
hal/sama5d3.h
View File

@ -278,6 +278,14 @@
#define MAX_PIV 0xfffff
#define PIT_MR_EN (1 << 24)
/* GPIO PMC IDs */
#define GPIOA_PMCID 0x06
#define GPIOB_PMCID 0x07
#define GPIOC_PMCID 0x08
#define GPIOD_PMCID 0x09
#define GPIOE_PMCID 0x0A
struct dram {
struct dram_timing {
@ -427,22 +435,36 @@ extern void *kernel_addr, *update_addr, *dts_addr;
#define MAX_ECC_BYTES 8
#endif
#define GPIOE_BASE 0xFFFFFA00
#define GPIOE_PER *(volatile uint32_t *)(GPIOE_BASE + 0x00)
#define GPIOE_PDR *(volatile uint32_t *)(GPIOE_BASE + 0x04)
#define GPIOE_PSR *(volatile uint32_t *)(GPIOE_BASE + 0x08)
#define GPIOE_OER *(volatile uint32_t *)(GPIOE_BASE + 0x10)
#define GPIOE_ODR *(volatile uint32_t *)(GPIOE_BASE + 0x14)
#define GPIOE_OSR *(volatile uint32_t *)(GPIOE_BASE + 0x18)
#define GPIOE_SODR *(volatile uint32_t *)(GPIOE_BASE + 0x30)
#define GPIOE_CODR *(volatile uint32_t *)(GPIOE_BASE + 0x34)
#define GPIOE_IER *(volatile uint32_t *)(GPIOE_BASE + 0x40)
#define GPIOE_IDR *(volatile uint32_t *)(GPIOE_BASE + 0x44)
#define GPIOE_MDER *(volatile uint32_t *)(GPIOE_BASE + 0x50)
#define GPIOE_MDDR *(volatile uint32_t *)(GPIOE_BASE + 0x54)
#define GPIOE_PPUDR *(volatile uint32_t *)(GPIOE_BASE + 0x60)
#define GPIOE_PPUER *(volatile uint32_t *)(GPIOE_BASE + 0x64)
#define GPIOB 0xFFFFF400
#define GPIOC 0xFFFFF600
#define GPIOE 0xFFFFFA00
#define GPIO_PER(base) *(volatile uint32_t *)(base + 0x00)
#define GPIO_PDR(base) *(volatile uint32_t *)(base + 0x04)
#define GPIO_PSR(base) *(volatile uint32_t *)(base + 0x08)
#define GPIO_OER(base) *(volatile uint32_t *)(base + 0x10)
#define GPIO_ODR(base) *(volatile uint32_t *)(base + 0x14)
#define GPIO_OSR(base) *(volatile uint32_t *)(base + 0x18)
#define GPIO_SODR(base) *(volatile uint32_t *)(base + 0x30)
#define GPIO_CODR(base) *(volatile uint32_t *)(base + 0x34)
#define GPIO_IER(base) *(volatile uint32_t *)(base + 0x40)
#define GPIO_IDR(base) *(volatile uint32_t *)(base + 0x44)
#define GPIO_MDER(base) *(volatile uint32_t *)(base + 0x50)
#define GPIO_MDDR(base) *(volatile uint32_t *)(base + 0x54)
#define GPIO_PPUDR(base) *(volatile uint32_t *)(base + 0x60)
#define GPIO_PPUER(base) *(volatile uint32_t *)(base + 0x64)
#define GPIO_PPDDR(base) *(volatile uint32_t *)(base + 0x90)
/* PMC Macro to enable clock */
#define PMC_CLOCK_EN(id) { \
register uint32_t pmc_pcr; \
PMC_PCR = id; \
pmc_pcr = PMC_PCR & (~PMC_PCR_DIV_MASK); \
pmc_pcr |= PMC_PCR_CMD | PMC_PCR_EN; \
PMC_PCR = pmc_pcr; \
}
#endif

2
hal/sama5d3.ld
View File

@ -3,7 +3,7 @@ OUTPUT_ARCH(arm)
MEMORY
{
DDR_MEM(rwx): ORIGIN = 0x00000000, LENGTH = 0x0000F000
DDR_MEM(rwx): ORIGIN = 0x00000000, LENGTH = 0x000100000
}
ENTRY(reset_vector_entry)

3
include/user_settings.h
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@ -41,6 +41,8 @@
/* Stdlib Types */
#define CTYPE_USER /* don't let wolfCrypt types.h include ctype.h */
#ifndef WOLFSSL_ARMASM
#ifndef toupper
extern int toupper(int c);
#endif
@ -49,6 +51,7 @@ extern int tolower(int c);
#endif
#define XTOUPPER(c) toupper((c))
#define XTOLOWER(c) tolower((c))
#endif
#ifdef USE_FAST_MATH
/* wolfBoot only does public asymmetric operations,

14
test-app/app_sama5d3.c
View File

@ -37,20 +37,20 @@
void led_init(uint32_t pin)
{
uint32_t mask = 1U << pin;
GPIOE_MDDR |= mask;
GPIOE_PER |= mask;
GPIOE_IDR |= mask;
GPIOE_PPUDR |= mask;
GPIOE_CODR |= mask;
GPIO_MDDR(GPIOE) |= mask;
GPIO_PER(GPIOE) |= mask;
GPIO_IDR(GPIOE) |= mask;
GPIO_PPUDR(GPIOE) |= mask;
GPIO_CODR(GPIOE) |= mask;
}
void led_put(uint32_t pin, int val)
{
uint32_t mask = 1U << pin;
if (val)
GPIOE_SODR |= mask;
GPIO_SODR(GPIOE) |= mask;
else
GPIOE_CODR |= mask;
GPIO_CODR(GPIOE) |= mask;
}
volatile uint32_t time_elapsed = 0;