mirror of https://github.com/wolfSSL/wolfBoot.git
Progress on eSPI support for NXP P1021 TPM.
David Garske
parent
ef35f473c9
commit
0f110e4cd9
1
arch.mk
1
arch.mk
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@ -331,6 +331,7 @@ ifeq ($(TARGET),nxp_p1021)
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# Use the SP math all assembly accelerations
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CFLAGS+=-DWOLFSSL_SP_PPC
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endif
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SPI_TARGET=nxp
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endif
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ifeq ($(TARGET),ti_hercules)
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@ -20,12 +20,13 @@ SPMATH?=0
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SPMATHALL?=1
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RAM_CODE?=0
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DUALBANK_SWAP?=0
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WOLFTPM?=0
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WOLFTPM?=1
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# Flash Sector (Block) Size (16KB)
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WOLFBOOT_SECTOR_SIZE=0x4000
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# Maximum size of wolfBoot stage 1 loader
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# Maximum size of wolfBoot stage 1 loader (can be increased for debugging)
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# Needs to be 4KB 0x1000 to fit into boot ROM loaded region
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WOLFBOOT_STAGE1_SIZE=0x1000
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# wolfBoot partition size (128KB)
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@ -39,7 +40,7 @@ WOLFBOOT_PARTITION_SIZE?=0x1000000
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# Location in Flash for stage 1 loader (XIP from boot ROM)
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WOLFBOOT_STAGE1_FLASH_ADDR=0x0
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# Location in Flash for wolfBoot
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WOLFBOOT_ORIGIN=0x4000
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WOLFBOOT_ORIGIN=0x8000
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# Location in Flash for Application Partition
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WOLFBOOT_PARTITION_BOOT_ADDRESS?= 0x200000
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# Location in Flash for Update Partition
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@ -49,7 +50,7 @@ WOLFBOOT_PARTITION_SWAP_ADDRESS?= 0x2200000
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## Loader Destinations (DDR) ##
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# Address in RAM to load stage 1 loader
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# Address in RAM to load stage 1 loader (can't be 0x0)
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WOLFBOOT_STAGE1_BASE_ADDR=0x4000
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# Address in RAM to load wolfBoot
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@ -1162,6 +1162,22 @@ make clean && make
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| swap block | 0x02200000 |
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### Debugging NXP P1021 PPC
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Use `V=1` to show verbose output for build steps.
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Use `DEBUG=1` to enable debug symbols.
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The first stage loader must fit into 4KB. To build this in release and assemble a debug version of wolfBoot use the following steps:
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```
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make clean
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make stage1
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make DEBUG=1 wolfboot.bin
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make DEBUG=1 test-app/image_v1_signed.bin
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make factory_wstage1.bin
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```
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## NXP QorIQ T2080 PPC
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The NXP QorIQ T2080 is a PPC e6500 based processor (four cores). Support has been tested with the NAII 68PPC2.
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@ -34,6 +34,10 @@
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#define ENABLE_CONF_IO
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#endif
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#ifdef WOLFBOOT_TPM
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#define ENABLE_ESPI
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#endif
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/* TODO */
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/* Ethernet */
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/* QUICC */
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@ -51,7 +55,8 @@ static int test_flash(void);
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/* P1021 Platform */
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#define SYS_CLK (533000000) /* 533MHz */
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//#define SYS_CLK (533000000) /* 533MHz */
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#define SYS_CLK (400000000) /* 400MHz */
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#define RESET_BPTR ((volatile uint32_t*)(CCSRBAR + 0x42)) /* Boot page translation register */
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@ -380,6 +385,113 @@ enum elbc_amask_sizes {
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#define ECM_BASE (CCSRBAR + 0x1000)
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#define ECM_EEBACR ((volatile uint32_t*)(ECM_BASE + 0x0)) /* ECM CCB address configuration register */
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/* eSPI */
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#define ESPI_MAX_CS_NUM 4
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#define ESPI_MAX_RX_LEN (1 << 16)
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#define ESPI_BASE (CCSRBAR + 0x7000)
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#define ESPI_SPMODE ((volatile uint32_t*)(ESPI_BASE + 0x00)) /* controls eSPI general operation mode */
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#define ESPI_SPIE ((volatile uint32_t*)(ESPI_BASE + 0x04)) /* controls interrupts and report events */
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#define ESPI_SPIM ((volatile uint32_t*)(ESPI_BASE + 0x08)) /* enables/masks interrupts */
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#define ESPI_SPCOM ((volatile uint32_t*)(ESPI_BASE + 0x0C)) /* command frame information */
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#define ESPI_SPITF ((volatile uint32_t*)(ESPI_BASE + 0x10)) /* transmit FIFO access register */
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#define ESPI_SPIRF ((volatile uint32_t*)(ESPI_BASE + 0x14)) /* 32-bit read-only receive data register */
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#define ESPI_SPCSMODE(x) ((volatile uint32_t*)(ESPI_BASE + 0x20 + ((cs) * 4))) /* controls master operation with chip select 0-3 */
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#define ESPI_SPMODE_EN (0x80000000) /* Enable eSPI */
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#define ESPI_SPMODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold (1-32) */
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#define ESPI_SPMODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold (0-31) */
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#define ESPI_SPCOM_CS(x) ((x) << 30) /* Chip select-chip select for which transaction is destined */
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#define ESPI_SPCOM_RXSKIP(x) ((x) << 16) /* Number of characters skipped for reception from frame start */
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#define ESPI_SPCOM_TRANLEN(x) (((x) - 1) << 0) /* Transaction length */
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#define ESPI_SPIE_RNE (1 << 9) /* recevie not empty */
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#define ESPI_SPIE_TNF (1 << 8) /* transmit not full */
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#define ESPI_CSMODE_CI 0x80000000 /* Inactive high */
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#define ESPI_CSMODE_CP 0x40000000 /* Begin edge clock */
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#define ESPI_CSMODE_REV 0x20000000 /* MSB first */
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#define ESPI_CSMODE_DIV16 0x10000000 /* divide system clock by 16 */
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#define ESPI_CSMODE_PM(x) (((x) & 0xF) << 24) /* presale modulus select */
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#define ESPI_CSMODE_POL 0x00100000 /* asserted low */
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#define ESPI_CSMODE_LEN(x) ((((x) - 1) & 0xF) << 16) /* Character length in bits per character */
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#define ESPI_CSMODE_CSBEF(x) (((x) & 0xF) << 12) /* CS assertion time in bits before frame start */
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#define ESPI_CSMODE_CSAFT(x) (((x) & 0xF) << 8) /* CS assertion time in bits after frame end */
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#define ESPI_CSMODE_CSCG(x) (((x) & 0xF) << 3) /* Clock gaps between transmitted frames according to this size */
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#ifdef ENABLE_ESPI
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void hal_espi_init(uint32_t cs, uint32_t clock_hz, uint32_t mode)
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{
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uint32_t spibrg = SYS_CLK / 2, pm, csmode;
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/* Enable eSPI with TX threadshold 4 and TX threshold 3 */
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set32(ESPI_SPMODE, (ESPI_SPMODE_EN | ESPI_SPMODE_TXTHR(4) |
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ESPI_SPMODE_RXTHR(3)));
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set32(ESPI_SPIE, 0xffffffff); /* Clear all eSPI events */
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set32(ESPI_SPIM, 0x00000000); /* Mask all eSPI interrupts */
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csmode = (ESPI_CSMODE_REV | ESPI_CSMODE_POL | ESPI_CSMODE_LEN(8) |
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ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | ESPI_CSMODE_CSCG(1));
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/* calculate clock divisor */
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if (spibrg / clock_hz > 16) {
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csmode |= ESPI_CSMODE_DIV16;
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pm = (spibrg / (clock_hz * 16));
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}
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else {
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pm = (spibrg / (clock_hz));
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}
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if (pm > 0)
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pm--;
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csmode |= ESPI_CSMODE_PM(pm);
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if (mode & 1)
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csmode |= ESPI_CSMODE_CP;
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if (mode & 2)
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csmode |= ESPI_CSMODE_CI;
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/* configure CS */
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set32(ESPI_SPCSMODE(cs), csmode);
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}
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int hal_espi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz)
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{
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uint32_t reg, blks;
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/* assert CS */
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set32(ESPI_SPCOM, ESPI_SPCOM_CS(cs) | ESPI_SPCOM_TRANLEN(sz));
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set32(ESPI_SPIE, 0xffffffff); /* Clear all eSPI events */
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/* calculate the number of 4 byte blocks rounded up */
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blks = (sz + 3) / 4;
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while (blks--) {
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/* wait till TX fifo has room */
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while ((get32(ESPI_SPIE) & ESPI_SPIE_TNF) == 0);
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reg = *((uint32_t*)tx);
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set32(ESPI_SPITF, reg);
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tx += 4;
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/* wait till RX has data */
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while ((get32(ESPI_SPIE) & ESPI_SPIE_RNE) == 0);
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reg = get32(ESPI_SPIRF);
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*((uint32_t*)rx) = reg;
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rx += 4;
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}
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/* toggle ESPI_SPMODE_EN - to deassert CS */
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reg = get32(ESPI_SPMODE);
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set32(ESPI_SPMODE, reg & ~ESPI_SPMODE_EN);
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set32(ESPI_SPMODE, reg);
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return 0;
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}
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void hal_espi_deinit(void)
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{
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/* do nothing */
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}
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#endif /* ENABLE_ESPI */
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static void set_law(uint8_t idx, uint32_t addr, uint32_t trgt_id,
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@ -932,10 +1044,7 @@ void hal_init(void)
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#ifdef DEBUG_UART
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uart_init();
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#ifdef DEBUG
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uart_write("wolfBoot Init\r\n", 15);
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#endif
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uart_write("wolfBoot HAL Init\r\n", 19);
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#endif
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#ifdef GET_PSVR
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@ -79,3 +79,4 @@ SECTIONS
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PROVIDE(_start_heap = _end);
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PROVIDE(_end_stack = _end + HEAP_SIZE + STACK_SIZE );
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@ -28,6 +28,8 @@
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#include "spi_drv.h"
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#include "spi_drv_nrf52.h"
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#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
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#define SPI0 (0x40003000)
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#define SPI1 (0x40004000)
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#define SPI2 (0x40023000)
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@ -122,3 +124,19 @@ void spi_release(void)
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{
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}
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#ifdef WOLFBOOT_TPM
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int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz)
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{
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uint32_t i;
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spi_cs_on(SPI_CS_TPM_PIO_BASE, cs);
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for (i = 0; i < sz; i++) {
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spi_write((const char)tx[i]);
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rx[i] = spi_read();
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}
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spi_cs_off(SPI_CS_TPM_PIO_BASE, cs);
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return 0;
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}
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#endif /* WOLFBOOT_TPM */
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#endif /* SPI_FLASH || WOLFBOOT_TPM */
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@ -0,0 +1,62 @@
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/* spi_drv_nxp.c
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*
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* Driver for the SPI back-end of the SPI_FLASH module.
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*
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* Pinout: see spi_drv_nxp.h
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*
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* Copyright (C) 2023 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include <stddef.h>
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#include "spi_drv.h"
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#include "spi_drv_nxp.h"
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#ifdef WOLFBOOT_TPM
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#if defined(PLATFORM_nxp_p1021)
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/* functions from nxp_p1021.c hal */
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extern void hal_espi_init(uint32_t cs, uint32_t clock_hz, uint32_t mode);
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extern int hal_espi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz);
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extern void hal_espi_deinit(void);
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#endif
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#include <wolftpm/tpm2_types.h>
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void spi_init(int polarity, int phase)
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{
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static int initialized = 0;
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if (!initialized) {
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initialized++;
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hal_espi_init(SPI_CS_TPM, TPM2_SPI_MAX_HZ, (polarity | (phase << 1)));
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}
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(void)polarity;
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(void)phase;
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}
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void spi_release(void)
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{
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hal_espi_deinit();
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}
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int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz)
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{
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return hal_espi_xfer(cs, tx, rx, sz);
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}
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#endif /* WOLFBOOT_TPM */
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@ -0,0 +1,32 @@
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/* spi_drv_nxp.h
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef SPI_DRV_NXP_H_INCLUDED
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#define SPI_DRV_NXP_H_INCLUDED
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#include <stdint.h>
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#if defined(PLATFORM_nxp_p1021)
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/* Chip select for TPM */
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#ifndef SPI_CS_TPM
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#define SPI_CS_TPM 2
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#endif
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#endif
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#endif /* !SPI_DRV_NXP_H_INCLUDED */
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@ -499,4 +499,18 @@ void RAMFUNCTION spi_release(void)
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}
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}
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#ifdef WOLFBOOT_TPM
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int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz)
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{
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uint32_t i;
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spi_cs_on(SPI_CS_TPM_PIO_BASE, cs);
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for (i = 0; i < sz; i++) {
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spi_write((const char)tx[i]);
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rx[i] = spi_read();
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}
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spi_cs_off(SPI_CS_TPM_PIO_BASE, cs);
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return 0;
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}
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#endif /* WOLFBOOT_TPM */
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#endif /* SPI_FLASH || WOLFBOOT_TPM || QSPI_FLASH || OCTOSPI_FLASH */
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@ -29,7 +29,7 @@
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#include "spi_drv.h"
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#include "spi_drv_zynq.h"
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#ifdef SPI_FLASH
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#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
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void spi_cs_off(uint32_t base, int pin)
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{
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@ -70,4 +70,18 @@ void spi_release(void)
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}
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#endif
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#ifdef WOLFBOOT_TPM
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int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz)
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{
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uint32_t i;
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spi_cs_on(SPI_CS_TPM_PIO_BASE, cs);
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for (i = 0; i < sz; i++) {
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spi_write((const char)tx[i]);
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rx[i] = spi_read();
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}
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spi_cs_off(SPI_CS_TPM_PIO_BASE, cs);
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return 0;
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}
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#endif /* WOLFBOOT_TPM */
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#endif /* SPI_FLASH | WOLFBOOT_TPM */
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@ -49,15 +49,23 @@
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#include "hal/spi/spi_drv_nrf52.h"
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#endif
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#if defined(PLATFORM_nxp_p1021)
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#include "hal/spi/spi_drv_nxp.h"
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#endif
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void spi_init(int polarity, int phase);
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void spi_release(void);
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#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
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#ifdef SPI_FLASH
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void spi_cs_on(uint32_t base, int pin);
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void spi_cs_off(uint32_t base, int pin);
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void spi_write(const char byte);
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uint8_t spi_read(void);
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#endif /* SPI_FLASH || WOLFBOOT_TPM */
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#endif
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#ifdef WOLFBOOT_TPM
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int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz);
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#endif
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#if defined(QSPI_FLASH) || defined(OCTOSPI_FLASH)
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@ -448,8 +448,7 @@ ifeq ($(WOLFTPM),1)
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-D"MAX_COMMAND_SIZE=1024" -D"MAX_RESPONSE_SIZE=1024" -D"WOLFTPM2_MAX_BUFFER=1500" \
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-D"MAX_SESSION_NUM=2" -D"MAX_DIGEST_BUFFER=973" \
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-D"WOLFTPM_SMALL_STACK"
|
||||
# Chip Type: WOLFTPM_SLB9670, WOLFTPM_ST33, WOLFTPM_MCHP
|
||||
CFLAGS+=-D"WOLFTPM_SLB9670"
|
||||
CFLAGS+=-D"WOLFTPM_AUTODETECT"
|
||||
# Use TPM for hashing (slow)
|
||||
#CFLAGS+=-D"WOLFBOOT_HASH_TPM"
|
||||
ifneq ($(SPI_FLASH),1)
|
||||
|
|
|
|||
39
src/image.c
39
src/image.c
|
|
@ -717,17 +717,11 @@ static void key_sha3_384(uint8_t key_slot, uint8_t *hash)
|
|||
static int TPM2_IoCb(TPM2_CTX* ctx, const byte* txBuf, byte* rxBuf,
|
||||
word16 xferSz, void* userCtx)
|
||||
{
|
||||
(void)userCtx;
|
||||
(void)ctx;
|
||||
word16 i;
|
||||
spi_cs_on(SPI_CS_TPM_PIO_BASE, SPI_CS_TPM);
|
||||
int ret;
|
||||
|
||||
memset(rxBuf, 0, xferSz);
|
||||
for (i = 0; i < xferSz; i++)
|
||||
{
|
||||
spi_write(txBuf[i]);
|
||||
rxBuf[i] = spi_read();
|
||||
}
|
||||
spi_cs_off(SPI_CS_TPM_PIO_BASE, SPI_CS_TPM);
|
||||
ret = spi_xfer(SPI_CS_TPM, txBuf, rxBuf, xferSz);
|
||||
|
||||
/*
|
||||
printf("\r\nSPI TX: ");
|
||||
printbin(txBuf, xferSz);
|
||||
|
|
@ -735,7 +729,11 @@ static int TPM2_IoCb(TPM2_CTX* ctx, const byte* txBuf, byte* rxBuf,
|
|||
printbin(rxBuf, xferSz);
|
||||
printf("\r\n");
|
||||
*/
|
||||
return 0;
|
||||
|
||||
(void)userCtx;
|
||||
(void)ctx;
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* !ARCH_SIM */
|
||||
|
||||
|
|
@ -791,17 +789,18 @@ int wolfBoot_tpm2_init(void)
|
|||
#else
|
||||
rc = wolfTPM2_Init(&wolftpm_dev, TPM2_IoCb, NULL);
|
||||
#endif
|
||||
if (rc != 0) {
|
||||
return rc;
|
||||
if (rc == 0) {
|
||||
/* Get device capabilities + options */
|
||||
rc = wolfTPM2_GetCapabilities(&wolftpm_dev, &caps);
|
||||
}
|
||||
if (rc == 0) {
|
||||
wolfBoot_printf("Mfg %s (%d), Vendor %s, Fw %u.%u (0x%x), "
|
||||
"FIPS 140-2 %d, CC-EAL4 %d\n",
|
||||
caps.mfgStr, caps.mfg, caps.vendorStr, caps.fwVerMajor,
|
||||
caps.fwVerMinor, caps.fwVerVendor, caps.fips140_2, caps.cc_eal4);
|
||||
}
|
||||
|
||||
/* Get device capabilities + options */
|
||||
rc = wolfTPM2_GetCapabilities(&wolftpm_dev, &caps);
|
||||
if (rc != 0) {
|
||||
return rc;
|
||||
}
|
||||
|
||||
return 0;
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Currently only supports ecc256 */
|
||||
|
|
|
|||
|
|
@ -29,6 +29,9 @@ OBJS:= \
|
|||
WOLFCRYPT_OBJS:=
|
||||
PUBLIC_KEY_OBJS:=
|
||||
|
||||
# Forcefully disable TPM support in first stage loader
|
||||
WOLFTPM=0
|
||||
|
||||
## Architecture/CPU configuration
|
||||
include ../arch.mk
|
||||
|
||||
|
|
|
|||
|
|
@ -40,12 +40,6 @@
|
|||
#define WOLFBOOT_STAGE1_SIZE (4*1024)
|
||||
#endif
|
||||
|
||||
#ifndef WOLFBOOT_STAGE1_START_ADDR
|
||||
/* default is end of 4KB region (0x0FFC) */
|
||||
#define WOLFBOOT_STAGE1_START_ADDR \
|
||||
(WOLFBOOT_STAGE1_LOAD_ADDR + WOLFBOOT_STAGE1_SIZE - 0x4)
|
||||
#endif
|
||||
|
||||
#ifdef BUILD_LOADER_STAGE1
|
||||
|
||||
#if defined(WOLFBOOT_ARCH) && WOLFBOOT_ARCH == PPC
|
||||
|
|
@ -87,7 +81,13 @@ int main(void)
|
|||
BOOTLOADER_PARTITION_SIZE /* boot-loader partition (entire) */
|
||||
);
|
||||
if (ret >= 0) {
|
||||
wolfboot_start = (void*)WOLFBOOT_STAGE1_START_ADDR;
|
||||
wolfboot_start = (void*)WOLFBOOT_STAGE1_LOAD_ADDR;
|
||||
#ifdef PRINTF_ENABLED
|
||||
wolfBoot_printf("Jumping to %p\r\n", wolfboot_start);
|
||||
#elif defined(DEBUG_UART)
|
||||
uart_write("Jump to relocated wolfboot_start\r\n", 34);
|
||||
#endif
|
||||
|
||||
wolfboot_start(); /* never returns */
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue