diff --git a/.gitignore b/.gitignore index 39bb7d52..0bf51973 100644 --- a/.gitignore +++ b/.gitignore @@ -123,3 +123,5 @@ CMakeCache.txt # Stage 1 stage1/loader_stage1.ld + +debug/lauterbach diff --git a/arch.mk b/arch.mk index c75d8bad..df5d6cdf 100644 --- a/arch.mk +++ b/arch.mk @@ -613,5 +613,5 @@ ifeq ($(DEBUG_UART),1) CFLAGS+=-DDEBUG_UART endif -CFLAGS+=-DWOLFBOOT_ARCH=$(ARCH) +CFLAGS+=-DWOLFBOOT_ARCH_$(ARCH) CFLAGS+=-DTARGET_$(TARGET) diff --git a/hal/nxp_p1021.c b/hal/nxp_p1021.c index d4bd47a5..69ec0b9b 100644 --- a/hal/nxp_p1021.c +++ b/hal/nxp_p1021.c @@ -26,27 +26,30 @@ #include "nxp_ppc.h" -#define ENABLE_ELBC +/* Debugging */ +/* #define DEBUG_EXT_FLASH */ +/* #define DEBUG_ESPI 1 */ + +/* Tests */ +/* #define TEST_DDR */ +/* #define TEST_FLASH */ +/* #define TEST_TPM */ + +#define ENABLE_ELBC /* Flash Controller */ #define ENABLE_BUS_CLK_CALC #ifndef BUILD_LOADER_STAGE1 #define ENABLE_PCIE #define ENABLE_CPLD /* Board Configuration and Status Registers (BCSR) */ #define ENABLE_CONF_IO #define ENABLE_QE /* QUICC Engine */ - #define ENABLE_ESPI /* SPI for TPM */ + #if defined(WOLFBOOT_TPM) || defined(TEST_TPM) + #define ENABLE_ESPI /* SPI for TPM */ + #endif #define ENABLE_MP /* multi-core support */ #define ENABLE_IRQ /* #define ENABLE_QE_CRC32 */ /* CRC32 check on QE disabled by default */ #endif -/* Debugging */ -/* #define DEBUG_EXT_FLASH */ - -/* Tests */ -/* #define TEST_DDR */ -/* #define TEST_FLASH */ -/* #define TEST_TPM */ - #if defined(ENABLE_DDR) && defined(TEST_DDR) static int test_ddr(void); #endif @@ -57,6 +60,9 @@ static int test_flash(void); static int test_tpm(void); #endif +#ifdef ENABLE_ESPI +#include "spi_drv.h" /* for transfer flags */ +#endif /* P1021 Platform */ /* System input clock */ @@ -92,17 +98,6 @@ static int test_tpm(void); #define GUTS_DEVDISR_TB1 0x00001000 -/* L2 Cache */ -#define L2_BASE (CCSRBAR + 0x20000) -#define L2CTL (volatile uint32_t*)(L2_BASE + 0x000) /* 0xFFE20000 - L2 control register */ -#define L2SRBAR0 (volatile uint32_t*)(L2_BASE + 0x100) /* 0xFFE20100 - L2 SRAM base address register */ - -#define L2CTL_EN (1 << 31) /* L2 enable */ -#define L2CTL_INV (1 << 30) /* L2 invalidate */ -#define L2CTL_SIZ(n) (((n) & 0x3) << 28) /* 2=256KB (always) */ -#define L2CTL_L2SRAM(n) (((n) & 0x7) << 16) /* 1=all 256KB, 2=128KB */ - - /* PIC */ #define PIC_BASE (CCSRBAR + 0x40000) #define PIC_WHOAMI ((volatile uint32_t*)(PIC_BASE + 0x0090UL)) /* Returns the ID of the processor core reading this register */ @@ -448,14 +443,17 @@ enum elbc_amask_sizes { /* eSPI */ #define ESPI_MAX_CS_NUM 4 #define ESPI_MAX_RX_LEN (1 << 16) +#define ESPI_FIFO_WORD 4 #define ESPI_BASE (CCSRBAR + 0x7000) #define ESPI_SPMODE ((volatile uint32_t*)(ESPI_BASE + 0x00)) /* controls eSPI general operation mode */ #define ESPI_SPIE ((volatile uint32_t*)(ESPI_BASE + 0x04)) /* controls interrupts and report events */ #define ESPI_SPIM ((volatile uint32_t*)(ESPI_BASE + 0x08)) /* enables/masks interrupts */ #define ESPI_SPCOM ((volatile uint32_t*)(ESPI_BASE + 0x0C)) /* command frame information */ -#define ESPI_SPITF ((volatile uint32_t*)(ESPI_BASE + 0x10)) /* transmit FIFO access register */ -#define ESPI_SPIRF ((volatile uint32_t*)(ESPI_BASE + 0x14)) /* 32-bit read-only receive data register */ +#define ESPI_SPITF ((volatile uint32_t*)(ESPI_BASE + 0x10)) /* transmit FIFO access register (32-bit) */ +#define ESPI_SPIRF ((volatile uint32_t*)(ESPI_BASE + 0x14)) /* read-only receive data register (32-bit) */ +#define ESPI_SPITF8 ((volatile uint8_t*)( ESPI_BASE + 0x10)) /* transmit FIFO access register (8-bit) */ +#define ESPI_SPIRF8 ((volatile uint8_t*)( ESPI_BASE + 0x14)) /* read-only receive data register (8-bit) */ #define ESPI_SPCSMODE(x) ((volatile uint32_t*)(ESPI_BASE + 0x20 + ((cs) * 4))) /* controls master operation with chip select 0-3 */ #define ESPI_SPMODE_EN (0x80000000) /* Enable eSPI */ @@ -466,9 +464,12 @@ enum elbc_amask_sizes { #define ESPI_SPCOM_RXSKIP(x) ((x) << 16) /* Number of characters skipped for reception from frame start */ #define ESPI_SPCOM_TRANLEN(x) (((x) - 1) << 0) /* Transaction length */ +#define ESPI_SPIE_TXE (1 << 15) /* transmit empty */ #define ESPI_SPIE_DON (1 << 14) /* Last character was transmitted */ -#define ESPI_SPIE_RNE (1 << 9) /* receive not empty */ -#define ESPI_SPIE_TNF (1 << 8) /* transmit not full */ +#define ESPI_SPIE_RXT (1 << 13) /* Rx FIFO has more than RXTHR bytes */ +#define ESPI_SPIE_RNE (1 << 9) /* receive not empty */ +#define ESPI_SPIE_TNF (1 << 8) /* transmit not full */ +#define ESPI_SPIE_RXCNT(n) (((n) >> 24) & 0x3F) /* The current number of full Rx FIFO bytes */ #define ESPI_CSMODE_CI 0x80000000 /* Inactive high */ #define ESPI_CSMODE_CP 0x40000000 /* Begin edge clock */ @@ -509,7 +510,10 @@ static uint32_t hal_get_bus_clk(void) } #if defined(ENABLE_ESPI) || defined(ENABLE_DDR) -static void udelay(unsigned long delay_us) +#ifdef BUILD_LOADER_STAGE1 +static +#endif +void udelay(unsigned long delay_us) { delay_us *= (hal_get_bus_clk() / 1000000); wait_ticks(delay_us); @@ -522,7 +526,7 @@ void hal_espi_init(uint32_t cs, uint32_t clock_hz, uint32_t mode) { uint32_t spibrg = hal_get_bus_clk() / 2, pm, csmode; - /* Enable eSPI with TX threadshold 4 and TX threshold 3 */ + /* Enable eSPI with TX threadshold 4 and RX threshold 3 */ set32(ESPI_SPMODE, (ESPI_SPMODE_EN | ESPI_SPMODE_TXTHR(4) | ESPI_SPMODE_RXTHR(3))); @@ -554,41 +558,75 @@ void hal_espi_init(uint32_t cs, uint32_t clock_hz, uint32_t mode) set32(ESPI_SPCSMODE(cs), csmode); } -/* Note: This code assumes all input buffers are multiple of 4 */ -int hal_espi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int cont) +int hal_espi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, + int flags) { - uint32_t reg, blks; + uint32_t mosi, miso, xfer, event; - /* assert CS */ - set32(ESPI_SPCOM, ESPI_SPCOM_CS(cs) | ESPI_SPCOM_TRANLEN(sz)); +#ifdef DEBUG_ESPI + wolfBoot_printf("CS %d, Sz %d, Flags %x\n", cs, sz, flags); +#endif - set32(ESPI_SPIE, 0xffffffff); /* Clear all eSPI events */ + if (sz > 0) { + /* assert CS - use max length and control CS with mode enable toggle */ + set32(ESPI_SPCOM, ESPI_SPCOM_CS(cs) | ESPI_SPCOM_TRANLEN(0x10000)); + set32(ESPI_SPIE, 0xffffffff); /* Clear all eSPI events */ + } + while (sz > 0) { + xfer = ESPI_FIFO_WORD; + if (xfer > sz) + xfer = sz; - /* calculate the number of 4 byte blocks rounded up */ - blks = (sz + 3) / 4; - while (blks--) { - /* wait till TX fifo has room */ - while ((get32(ESPI_SPIE) & ESPI_SPIE_TNF) == 0); - reg = *((uint32_t*)tx); - set32(ESPI_SPITF, reg); - tx += 4; - set32(ESPI_SPIE, ESPI_SPIE_TNF); /* clear event */ + /* Transfer 4 or 1 */ + if (xfer == ESPI_FIFO_WORD) { + set32(ESPI_SPITF, *((uint32_t*)tx)); + } + else { + xfer = 1; + set8(ESPI_SPITF8, *((uint8_t*)tx)); + } - udelay(5); + /* wait till TX fifo is empty or done */ + while (1) { + event = get32(ESPI_SPIE); + if (event & (ESPI_SPIE_TXE | ESPI_SPIE_DON)) { + /* clear events */ + set32(ESPI_SPIE, (ESPI_SPIE_TXE | ESPI_SPIE_DON)); + break; + } + } - /* wait till RX has data */ - while ((get32(ESPI_SPIE) & ESPI_SPIE_RNE) == 0); - reg = get32(ESPI_SPIRF); - *((uint32_t*)rx) = reg; - rx += 4; - set32(ESPI_SPIE, ESPI_SPIE_RNE); /* clear event */ + /* wait till RX has enough data */ + while (1) { + event = get32(ESPI_SPIE); + if ((event & ESPI_SPIE_RNE) == 0) + continue; + #if defined(DEBUG_ESPI) && DEBUG_ESPI > 1 + wolfBoot_printf("event %x\n", event); + #endif + if (ESPI_SPIE_RXCNT(event) >= xfer) + break; + } + if (xfer == ESPI_FIFO_WORD) { + *((uint32_t*)rx) = get32(ESPI_SPIRF); + } + else { + *((uint8_t*)rx) = get8(ESPI_SPIRF8); + } + +#ifdef DEBUG_ESPI + wolfBoot_printf("MOSI %x, MISO %x\n", + *((uint32_t*)tx), *((uint32_t*)rx)); +#endif + tx += xfer; + rx += xfer; + sz -= xfer; } - if (!cont) { + if (!(flags & SPI_XFER_FLAG_CONTINUE)) { /* toggle ESPI_SPMODE_EN - to deassert CS */ - reg = get32(ESPI_SPMODE); - set32(ESPI_SPMODE, reg & ~ESPI_SPMODE_EN); - set32(ESPI_SPMODE, reg); + set32(ESPI_SPMODE, get32(ESPI_SPMODE) & ~ESPI_SPMODE_EN); + set32(ESPI_SPMODE, get32(ESPI_SPMODE) | ESPI_SPMODE_EN); } return 0; @@ -1497,40 +1535,6 @@ static void hal_irq_init(void) } #endif -#ifdef ENABLE_L2_CACHE -static void hal_l2_init(void) -{ - uint32_t reg; - - /* e500v2 L2 Cache */ -#ifdef L2SRAM_ADDR - /* L2 L2SRAM_ADDR: TLB 1, Entry 9, Supervisor X/R/W, G, TS=0, 256KB, IPROT */ - set_tlb(1, 9, - L2SRAM_ADDR, L2SRAM_ADDR, 0, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G, 0, - BOOKE_PAGESZ_256K, 1, r3); -#endif - - /* Configure the L2 Cache */ - asm volatile("mbar; isync"); -#ifdef L2SRAM_ADDR /* as SRAM (1=256KB) */ - set32(L2CTL, (L2CTL_EN | L2CTL_INV | L2CTL_L2SRAM(1))); -#else - set32(L2CTL, (L2CTL_EN | L2CTL_INV | L2CTL_SIZ(2))); -#endif - reg = get32(L2CTL); /* read back (per P1021 RM) */ - asm volatile("mbar"); - -#ifdef L2SRAM_ADDR - /* Set the L2SRAM base address */ - asm volatile("mbar; isync"); - set32(L2SRBAR0, L2SRAM_ADDR); - reg = get32(L2SRBAR0); - asm volatile("mbar"); -#endif -} -#endif /* ENABLE_L2_CACHE */ - void hal_init(void) { #ifdef DEBUG_UART @@ -1539,9 +1543,6 @@ void hal_init(void) uart_write("wolfBoot HAL Init\n", 19); #endif #endif -#ifdef ENABLE_L2_CACHE - hal_l2_init(); -#endif #ifdef ENABLE_PCIE hal_pcie_init(); #endif diff --git a/hal/nxp_p1021_stage1.bin b/hal/nxp_p1021_stage1.bin index 884859f6..bad237a2 100644 Binary files a/hal/nxp_p1021_stage1.bin and b/hal/nxp_p1021_stage1.bin differ diff --git a/hal/nxp_p1021_stage1.ld b/hal/nxp_p1021_stage1.ld index 21b4bc0f..f1aa2c85 100644 --- a/hal/nxp_p1021_stage1.ld +++ b/hal/nxp_p1021_stage1.ld @@ -104,5 +104,5 @@ SECTIONS } > DRAM } -PROVIDE(_start_heap = _end); -PROVIDE(_end_stack = ORIGIN(L1RAM) + (LENGTH(L1RAM)) ); +PROVIDE(_start_heap = ORIGIN(L2RAM)); +PROVIDE(_end_stack = ORIGIN(L2RAM) + (LENGTH(L2RAM)) ); diff --git a/hal/nxp_ppc.h b/hal/nxp_ppc.h index 92eab377..6c452c04 100644 --- a/hal/nxp_ppc.h +++ b/hal/nxp_ppc.h @@ -30,26 +30,23 @@ #define CCSRBAR_DEF (0xFF700000) /* P1021RM 4.3 default base */ #define CCSRBAR_SIZE BOOKE_PAGESZ_1M - #define ENABLE_L1_CACHE - #define ENABLE_DDR + /* Memory used for transferring blocks to/from NAND. + * Maps to eLBC FCM internal 8KB region (by hardware) */ + #define FLASH_BASE_ADDR 0xFC000000 + #ifdef BUILD_LOADER_STAGE1 /* First stage loader features */ - /* For Boot ROM FCM buffer */ - #define FLASH_BASE_ADDR 0xFFF00000 - - /* L2 is not available while FMR[BOOT]=1 */ - #define L1_CACHE_ADDR 0xFFD00000 + #define ENABLE_L2_CACHE + #define L2SRAM_ADDR (0xF8F80000) /* L2 as SRAM */ + #define L2SRAM_SIZE (256 * 1024) #else /* For wolfBoot features */ + #define ENABLE_L1_CACHE #define ENABLE_L2_CACHE - /* Memory used for transferring blocks to/from NAND. - * Maps to eLBC FCM internal 8KB region (by hardware) */ - #define FLASH_BASE_ADDR 0xFC000000 - /* Relocate CCSRBAR */ #define CCSRBAR 0xFFE00000 @@ -117,14 +114,10 @@ #endif /* L1 */ -#ifndef L1_CACHE_ADDR -#define L1_CACHE_ADDR 0xFFD00000 -#endif #ifndef L1_CACHE_SZ #define L1_CACHE_SZ (32 * 1024) #endif - #ifdef CORE_E500 /* PowerPC e500 */ /* EREF: 7.5.3.2 - TLB Entry Page Size */ @@ -143,7 +136,7 @@ #define MAS1_TSIZE_MASK 0x00000F00 #define MAS1_TSIZE(x) (((x) << 8) & MAS1_TSIZE_MASK) - #define L1_CACHE_LINE_SHIFT 5 /* 32 bytes per L1 cache line */ + #define CACHE_LINE_SHIFT 5 /* 32 bytes per L1 cache line */ /* P1021 LAW - Local Access Window (Memory Map) - RM 2.4 */ #define LAWBAR_BASE(n) (0xC08 + (n * 0x20)) @@ -157,7 +150,7 @@ #define LAW_TRGT_PCIE2 0x01 #define LAW_TRGT_PCIE1 0x02 #define LAW_TRGT_ELBC 0x04 /* eLBC (Enhanced Local Bus Controller) */ - #define LAW_TRGT_DDR 0x0F /* DDR Memory Controller */ + #define LAW_TRGT_DDR 0x0F /* DDR Memory Controller */ /* P1021 2.4.2 - size is equal to 2^(enum + 1) */ #define LAW_SIZE_4KB 0x0B @@ -218,7 +211,7 @@ #define MAS1_TSIZE_MASK 0x00000F80 #define MAS1_TSIZE(x) (((x) << 7) & MAS1_TSIZE_MASK) - #define L1_CACHE_LINE_SHIFT 6 /* 64 bytes per L1 cache line */ + #define CACHE_LINE_SHIFT 6 /* 64 bytes per L1 cache line */ /* CoreNet Platform Cache Base */ #define CPC_BASE (CCSRBAR + 0x10000) @@ -271,8 +264,8 @@ #endif -#ifndef L1_CACHE_LINE_SIZE -#define L1_CACHE_LINE_SIZE (1 << L1_CACHE_LINE_SHIFT) +#ifndef CACHE_LINE_SIZE +#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT) #endif diff --git a/hal/spi/spi_drv_nrf52.c b/hal/spi/spi_drv_nrf52.c index fb4a001d..03e424bf 100644 --- a/hal/spi/spi_drv_nrf52.c +++ b/hal/spi/spi_drv_nrf52.c @@ -126,7 +126,7 @@ void spi_release(void) } #ifdef WOLFBOOT_TPM -int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int cont) +int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int flags) { uint32_t i; spi_cs_on(SPI_CS_TPM_PIO_BASE, cs); @@ -134,7 +134,7 @@ int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int cont) spi_write((const char)tx[i]); rx[i] = spi_read(); } - if (!cont) { + if (!(flags & SPI_XFER_FLAG_CONTINUE)) { spi_cs_off(SPI_CS_TPM_PIO_BASE, cs); } return 0; diff --git a/hal/spi/spi_drv_nxp.c b/hal/spi/spi_drv_nxp.c index 6f155646..968516f2 100644 --- a/hal/spi/spi_drv_nxp.c +++ b/hal/spi/spi_drv_nxp.c @@ -32,7 +32,7 @@ #if defined(PLATFORM_nxp_p1021) /* functions from nxp_p1021.c hal */ extern void hal_espi_init(uint32_t cs, uint32_t clock_hz, uint32_t mode); -extern int hal_espi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int cont); +extern int hal_espi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int flags); extern void hal_espi_deinit(void); #endif @@ -55,8 +55,8 @@ void spi_release(void) hal_espi_deinit(); } -int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int cont) +int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int flags) { - return hal_espi_xfer(cs, tx, rx, sz, cont); + return hal_espi_xfer(cs, tx, rx, sz, flags); } #endif /* WOLFBOOT_TPM */ diff --git a/hal/spi/spi_drv_stm32.c b/hal/spi/spi_drv_stm32.c index 767741e3..8e12b310 100644 --- a/hal/spi/spi_drv_stm32.c +++ b/hal/spi/spi_drv_stm32.c @@ -500,7 +500,7 @@ void RAMFUNCTION spi_release(void) } #ifdef WOLFBOOT_TPM -int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int cont) +int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int flags) { uint32_t i; spi_cs_on(SPI_CS_TPM_PIO_BASE, cs); @@ -508,7 +508,7 @@ int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int cont) spi_write((const char)tx[i]); rx[i] = spi_read(); } - if (!cont) { + if (!(flags & SPI_XFER_FLAG_CONTINUE)) { spi_cs_off(SPI_CS_TPM_PIO_BASE, cs); } return 0; diff --git a/hal/spi/spi_drv_zynq.c b/hal/spi/spi_drv_zynq.c index 26c70fa7..02361703 100644 --- a/hal/spi/spi_drv_zynq.c +++ b/hal/spi/spi_drv_zynq.c @@ -71,7 +71,7 @@ void spi_release(void) } #ifdef WOLFBOOT_TPM -int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int cont) +int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int flags) { uint32_t i; spi_cs_on(SPI_CS_TPM_PIO_BASE, cs); @@ -79,7 +79,7 @@ int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int cont) spi_write((const char)tx[i]); rx[i] = spi_read(); } - if (!cont) { + if (!(flags & SPI_XFER_FLAG_CONTINUE)) { spi_cs_off(SPI_CS_TPM_PIO_BASE, cs); } return 0; diff --git a/include/spi_drv.h b/include/spi_drv.h index 4c941b05..37c958c2 100644 --- a/include/spi_drv.h +++ b/include/spi_drv.h @@ -64,9 +64,13 @@ uint8_t spi_read(void); #endif #ifdef WOLFBOOT_TPM -/* Perform a SPI transaction. Set cont!=0 to not let CS go low after this */ -/* cont 0=is last transfer and will de-assert CS, 1=leave CS asserted */ -int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int cont); +/* SPI transfer flags */ +#define SPI_XFER_FLAG_NONE 0x0 +#define SPI_XFER_FLAG_CONTINUE 0x1 /* keep CS asserted */ + +/* Perform a SPI transaction. + * Set flags == SPI_XFER_FLAG_CONTINUE to keep CS asserted after transfer. */ +int spi_xfer(int cs, const uint8_t* tx, uint8_t* rx, uint32_t sz, int flags); #endif #if defined(QSPI_FLASH) || defined(OCTOSPI_FLASH) diff --git a/src/boot_ppc.c b/src/boot_ppc.c index 93777913..0a60d8e7 100644 --- a/src/boot_ppc.c +++ b/src/boot_ppc.c @@ -120,18 +120,18 @@ void flush_cache(uint32_t start_addr, uint32_t size) { uint32_t addr, start, end; - start = start_addr & ~(L1_CACHE_LINE_SIZE - 1); + start = start_addr & ~(CACHE_LINE_SIZE - 1); end = start_addr + size - 1; for (addr = start; (addr <= end) && (addr >= start); - addr += L1_CACHE_LINE_SIZE) { + addr += CACHE_LINE_SIZE) { asm volatile("dcbst 0,%0" : : "r" (addr) : "memory"); } /* wait for all dcbst to complete on bus */ asm volatile("sync" : : : "memory"); for (addr = start; (addr <= end) && (addr >= start); - addr += L1_CACHE_LINE_SIZE) { + addr += CACHE_LINE_SIZE) { asm volatile("icbi 0,%0" : : "r" (addr) : "memory"); } asm volatile("sync" : : : "memory"); diff --git a/src/boot_ppc_mp.S b/src/boot_ppc_mp.S index 78b869bc..598c7235 100644 --- a/src/boot_ppc_mp.S +++ b/src/boot_ppc_mp.S @@ -235,7 +235,7 @@ _mp_page_start: _bootpg_addr: .long 0 - .align L1_CACHE_LINE_SHIFT + .align CACHE_LINE_SHIFT /* Reserve space for spin table entries */ .globl _spin_table diff --git a/src/boot_ppc_start.S b/src/boot_ppc_start.S index 216eb34f..f6fd9401 100644 --- a/src/boot_ppc_start.S +++ b/src/boot_ppc_start.S @@ -494,14 +494,13 @@ flash_tlb: BOOKE_PAGESZ_256M, 0, r3); #endif -#ifdef CORE_E6500 - #ifdef ENABLE_L2_CACHE - +#ifdef CORE_E6500 /* --- L2 E6500 --- */ #ifdef L2SRAM_ADDR l2_sram_law: /* L2 SRAM - LAW2 (DDR 256KB) */ - #define L2SRAM_LAW (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_DDR_1) | LAW_SIZE_256KB) + #define L2SRAM_LAW \ + (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_DDR_1) | LAW_SIZE_256KB) lis r9, CCSRBAR + LAWBAR_BASE(2)@h ori r9, r9, CCSRBAR + LAWBAR_BASE(2)@l li r0, 0 @@ -517,11 +516,11 @@ l2_sram_law: isync l2_sram_tlb: - /* L2 0xFEC20000: TLB 1, Entry 9, Supervisor X/R/W, M, TS=0, 512KB, IPROT */ + /* L2 0xFEC20000: TLB 1, Entry 9, Supervisor X/R/W, M, TS=0, 256KB, IPROT */ set_tlb(1, 9, L2SRAM_ADDR, L2SRAM_ADDR, 0, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0, - BOOKE_PAGESZ_512K, 1, r3); + BOOKE_PAGESZ_256K, 1, r3); l2_setup_sram: /* 8.2 CoreNet Platform Cache (CPC) Memory Map */ @@ -565,7 +564,7 @@ l2_setup_sram: isync stw r0, CPCCSR0(r1) mbar -#endif +#endif /* L2SRAM_ADDR */ /* Disable speculation */ lwz r0, CPCHDBCR0(r1) @@ -616,24 +615,78 @@ l2_poll_invclear: li r4, 32 stw r4, L2CSR1(r5) -#ifdef L2SRAM_ADDR -l2_sram_init: - /* clear 8 bytes at a time */ - lis r2, (L2SRAM_ADDR - 8)@h - ori r2, r2, (L2SRAM_ADDR - 8)@l - lis r3, (L2SRAM_SIZE / 8)@h - ori r3, r3, (L2SRAM_SIZE / 8)@l - mtctr r3 - li r3, 0 -l2_sram_init_loop: - stdu r3, 8(r2) - bdnz l2_sram_init_loop -#endif /* L2SRAM_ADDR */ -#endif /* ENABLE_L2_CACHE */ -#endif /* CORE_E6500 */ +#elif defined(CORE_E500) /* --- L2 E500 --- */ + +#ifdef L2SRAM_ADDR +l2_sram_law: + /* L2 SRAM - LAW2 (eLBC 256KB) */ + #define L2SRAM_LAW \ + (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_ELBC) | LAW_SIZE_256KB) + lis r9, CCSRBAR + LAWBAR_BASE(2)@h + ori r9, r9, CCSRBAR + LAWBAR_BASE(2)@l + lis r1, L2SRAM_ADDR@h + ori r1, r1, L2SRAM_ADDR@l + lis r2, L2SRAM_LAW@h + ori r2, r2, L2SRAM_LAW@l + stw r1, 0(r9) /* LAWBAR */ + sync + stw r2, 8(r9) /* LAWAR */ + lwz r2, 8(r9) /* read back LAWAR */ + isync + +l2_sram_tlb: + /* L2 0xF8F80000: TLB 1, Entry 9, Supervisor X/R/W, G, TS=0, 256KB, IPROT */ + set_tlb(1, 9, + L2SRAM_ADDR, L2SRAM_ADDR, 0, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G, 0, + BOOKE_PAGESZ_256K, 1, r3); +#endif + + /* e500 - L2 Cache */ +l2_setup_cache: + #define L2_BASE (CCSRBAR + 0x20000) + #define L2CTL 0x000 /* 0xFFE20000 - L2 control register */ + #define L2SRBAR0 0x100 /* 0xFFE20100 - L2 SRAM base address register */ + + #define L2CTL_EN (1 << 31) /* L2 enable */ + #define L2CTL_INV (1 << 30) /* L2 invalidate */ + #define L2CTL_SIZ(n) (((n) & 0x3) << 28) /* 2=256KB (always) */ + #define L2CTL_L2SRAM(n) (((n) & 0x7) << 16) /* 1=all 256KB, 2=128KB */ + + #ifdef L2SRAM_ADDR /* as SRAM (1=256KB) */ + #define L2CTL_VAL (L2CTL_EN | L2CTL_INV | L2CTL_SIZ(2) | L2CTL_L2SRAM(1)) + #else + #define L2CTL_VAL (L2CTL_EN | L2CTL_INV | L2CTL_SIZ(2)) + #endif + /* Configure the L2 Cache */ + lis r5, L2_BASE@h + ori r5, r5, L2_BASE@l + lis r1, L2CTL_VAL@h + ori r1, r1, L2CTL_VAL@l + msync + isync + stw r1, L2CTL(r5) + msync + isync + lwz r1, L2CTL(r5) /* read back (per P1021 RM) */ + +#ifdef L2SRAM_ADDR +l2_setup_sram: + /* Set the L2SRAM base address */ + mbar + isync + lis r1, L2SRAM_ADDR@h + ori r1, r1, L2SRAM_ADDR@l + stw r1, L2SRBAR0(r5) + mbar +#endif /* L2SRAM_ADDR */ + +#endif /* CORE_* */ +#endif /* ENABLE_L2_CACHE */ + -setup_l1: #ifdef ENABLE_L1_CACHE +setup_l1: #ifndef BUILD_LOADER_STAGE1 /* L1 Instruction Cache */ bl icache_enable; @@ -655,27 +708,38 @@ l1_tlb: set_tlb(0, 0, L1_CACHE_ADDR+0x3000, L1_CACHE_ADDR+0x3000, 0, (MAS3_SX | MAS3_SW | MAS3_SR), 0, 0, BOOKE_PAGESZ_4K, 0, r3); -l1_cache: - /* setup L1 cache */ - lis r3, L1_CACHE_ADDR@h - ori r3, r3, L1_CACHE_ADDR@l + #define CACHE_SRAM_ADDR L1_CACHE_ADDR +#elif defined(L2SRAM_ADDR) + #define CACHE_SRAM_ADDR L2SRAM_ADDR +#endif +#endif /* ENABLE_L1_CACHE */ + +#ifdef CACHE_SRAM_ADDR +cache_sram_init: + lis r3, CACHE_SRAM_ADDR@h + ori r3, r3, CACHE_SRAM_ADDR@l /* read the cache size */ mfspr r2, L1CFG0 andi. r2, r2, 0x1FF /* calculate (cache size * 1024 / (2 * L1 line size)) */ - slwi r2, r2, (10 - 1 - L1_CACHE_LINE_SHIFT) - mtctr r2 + slwi r2, r2, (10 - 1 - CACHE_LINE_SHIFT) + mtctr r2 /* load counter */ li r0, 0 +cache_sram_init_loop: + /* Data cache block zero */ + dcbz r0, r3 + /* Data cache block touch and lock set */ +#ifdef CORE_E6500 + dcbtls 2, r0, r3 + dcbtls 0, r0, r3 +#else + dcbtls 0, r0, r3 +#endif + addi r3, r3, CACHE_LINE_SIZE + bdnz cache_sram_init_loop +#endif /* CACHE_SRAM_ADDR */ -l1_cache_init: - dcbz r0, r3 /* Data cache block zero */ - dcbtls 0, r0, r3 /* Data cache block touch and lock set */ - addi r3, r3, L1_CACHE_LINE_SIZE - bdnz l1_cache_init -#endif /* L1_CACHE_ADDR */ -#endif /* ENABLE_L1_CACHE */ - -setup_ts0: +setup_stack: /* Build top of stack address */ /* Reserve 64 bytes of initial data (must be 16 byte aligned) */ lis r1, (_end_stack-64)@h @@ -839,7 +903,7 @@ dcache_disable: relocate_code: mr r9, r3 /* Save copy of Destination Address */ mr r10, r4 /* Save copy of Source Address */ - li r6, L1_CACHE_LINE_SIZE /* Cache Line size */ + li r6, CACHE_LINE_SIZE /* Cache Line size */ /* Fix GOT pointer */ GET_GOT diff --git a/stage1/loader_stage1.c b/stage1/loader_stage1.c index 5a43e67f..20a98a48 100644 --- a/stage1/loader_stage1.c +++ b/stage1/loader_stage1.c @@ -42,7 +42,7 @@ #ifdef BUILD_LOADER_STAGE1 -#if defined(WOLFBOOT_ARCH) && WOLFBOOT_ARCH == PPC +#ifdef WOLFBOOT_ARCH_PPC #include "hal/nxp_ppc.h" #endif @@ -85,11 +85,11 @@ int main(void) /* relocate 4KB code to DST and jump */ memcpy32((void*)wolfboot_start, (void*)BOOT_ROM_ADDR, BOOT_ROM_SIZE); - #if defined(WOLFBOOT_ARCH) && WOLFBOOT_ARCH == PPC + #ifdef WOLFBOOT_ARCH_PPC /* TODO: Fix hack and consider moving to hal_prepare_boot */ /* HACK: Fix up stack values modified with trap */ - *((uint32_t*)(WOLFBOOT_STAGE1_BASE_ADDR + 0xC18)) = 0x9421FFF0; - *((uint32_t*)(WOLFBOOT_STAGE1_BASE_ADDR + 0xC74)) = 0x39200000; + *((uint32_t*)(WOLFBOOT_STAGE1_BASE_ADDR + 0xB70)) = 0x9421FFF0; /* main() */ + *((uint32_t*)(WOLFBOOT_STAGE1_BASE_ADDR + 0xBCC)) = 0x39200000; /* instruction above */ /* call to relocate code does not return */ relocate_code(wolfboot_start, (void*)BOOT_ROM_ADDR, BOOT_ROM_SIZE);