From 11f46a51e15f599b5c6311ac19956c0ce767b0a1 Mon Sep 17 00:00:00 2001 From: David Garske Date: Thu, 29 Jun 2023 12:52:44 -0700 Subject: [PATCH] Further fixes and improvements with NXP T2080 regression testing. Added required LAW's to startup assembly. Moved LAW definitions to header. Move isr_empty so other boot functions go in the boot section. --- hal/nxp_p1021.c | 45 -------- hal/nxp_ppc.h | 262 +++++++++++++++++++++++++++++++------------ hal/nxp_t2080.c | 52 +-------- hal/nxp_t2080.ld | 2 +- src/boot_ppc_start.S | 203 +++++++++++++++++++++++++-------- 5 files changed, 349 insertions(+), 215 deletions(-) diff --git a/hal/nxp_p1021.c b/hal/nxp_p1021.c index e1ab0cff..684a5564 100644 --- a/hal/nxp_p1021.c +++ b/hal/nxp_p1021.c @@ -199,51 +199,6 @@ static int test_tpm(void); #define UART_LSR_TEMT (0x40) /* Transmitter empty */ #define UART_LSR_THRE (0x20) /* Transmitter holding register empty */ - -/* P1021 LAW - Local Access Window (Memory Map) - RM 2.4 */ -#define LAWBAR_BASE(n) (CCSRBAR + 0xC08 + (n * 0x20)) -#define LAWBAR(n) ((volatile uint32_t*)(LAWBAR_BASE(n) + 0x0)) -#define LAWAR(n) ((volatile uint32_t*)(LAWBAR_BASE(n) + 0x8)) - -#define LAWAR_ENABLE (1<<31) -#define LAWAR_TRGT_ID(id) (id<<20) - -/* P1021 Global Source/Target ID Assignments - RM Table 2-7 */ -enum law_target_id { - LAW_TRGT_PCIE2 = 0x01, - LAW_TRGT_PCIE1 = 0x02, - LAW_TRGT_ELBC = 0x4, /* eLBC (Enhanced Local Bus Controller) */ - LAW_TRGT_DDR = 0xF, /* DDR Memory Controller */ -}; - -/* P1021 2.4.2 - size is equal to 2^(enum + 1) */ -enum law_sizes { - LAW_SIZE_4KB = 0x0B, - LAW_SIZE_8KB, - LAW_SIZE_16KB, - LAW_SIZE_32KB, - LAW_SIZE_64KB, - LAW_SIZE_128KB, /* 0x10 */ - LAW_SIZE_256KB, - LAW_SIZE_512KB, - LAW_SIZE_1MB, - LAW_SIZE_2MB, - LAW_SIZE_4MB, - LAW_SIZE_8MB, - LAW_SIZE_16MB, - LAW_SIZE_32MB, - LAW_SIZE_64MB, - LAW_SIZE_128MB, - LAW_SIZE_256MB, /* 0x1B */ - LAW_SIZE_512MB, - LAW_SIZE_1GB, - LAW_SIZE_2GB, - LAW_SIZE_4GB, - LAW_SIZE_8GB, /* 0x20 */ - LAW_SIZE_16GB, - LAW_SIZE_32GB, -}; - /* P1021 eLBC (Enhanced Local Bus Controller) - RM 12.3 */ #define ELBC_BASE (CCSRBAR + 0x5000) #define ELBC_MAX_BANKS 8 diff --git a/hal/nxp_ppc.h b/hal/nxp_ppc.h index 3ddf0a4d..92eab377 100644 --- a/hal/nxp_ppc.h +++ b/hal/nxp_ppc.h @@ -25,9 +25,10 @@ #ifdef PLATFORM_nxp_p1021 /* NXP P1021 */ #define CPU_NUMCORES 2 + #define CORE_E500 + #define CCSRBAR_DEF (0xFF700000) /* P1021RM 4.3 default base */ #define CCSRBAR_SIZE BOOKE_PAGESZ_1M - #define MMU_V1 #define ENABLE_L1_CACHE @@ -58,46 +59,74 @@ #elif defined(PLATFORM_nxp_t2080) /* NXP T0280 */ #define CPU_NUMCORES 4 - #define CCSRBAR_DEF (0xFE000000) /* T2080RM 4.3.1 default base */ + #define CORE_E6500 + + #define CCSRBAR_DEF (0xFE000000) /* T2080RM 4.3.1 default base - 0xFF000000 */ #define CCSRBAR_SIZE BOOKE_PAGESZ_16M - #define MMU_V2 + + /* relocate to 64-bit 0xE_ */ + //#define CCSRBAR_PHYS_HIGH 0xE + //#define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF) + #define ENABLE_L1_CACHE #define ENABLE_L2_CACHE - #define L2SRAM_ADDR (0xFEC20000) /* L2 as SRAM */ + #define L2SRAM_ADDR (0xF8F80000) /* L2 as SRAM */ #define L2SRAM_SIZE (256 * 1024) #define ENABLE_INTERRUPTS #define ENABLE_DDR - /* This flash mapping window is automatically enabled - * T2080RM: 4.3.3 Boot Space Translation: - * default boot window (8 MB at 0x0_FF80_0000 to 0x0_FFFF_FFFF) - */ - #define FLASH_BASE_ADDR 0xEF800000 + #define FLASH_BASE_ADDR 0xE8000000 + #define FLASH_BASE_PHYS_HIGH 0x0 + #define USE_LONG_JUMP #else - #error Please define MMU version and CCSRBAR for platform + #error Please define platform PowerPC core version and CCSRBAR #endif -/* boot address */ -#define BOOT_ROM_ADDR 0xFFFFF000 -#define BOOT_ROM_SIZE (4*1024) + +/* boot address */ +#ifndef BOOT_ROM_ADDR +#define BOOT_ROM_ADDR 0xFFFFF000 +#endif +#ifndef BOOT_ROM_SIZE +#define BOOT_ROM_SIZE (4*1024) +#endif + +/* reset vector */ #define RESET_VECTOR (BOOT_ROM_ADDR + (BOOT_ROM_SIZE - 4)) +/* CCSRBAR */ #ifndef CCSRBAR_DEF #define CCSRBAR_DEF 0xFE000000 #endif #ifndef CCSRBAR #define CCSRBAR CCSRBAR_DEF #endif - -#ifndef DDR_ADDRESS -#define DDR_ADDRESS 0x00000000 +#ifndef CCSRBAR_PHYS +#define CCSRBAR_PHYS CCSRBAR +#endif +#ifndef CCSRBAR_PHYS_HIGH +#define CCSRBAR_PHYS_HIGH 0 #endif -#ifdef MMU_V1 - /* MMU V1 - e500 */ +/* DDR */ +#ifndef DDR_ADDRESS +#define DDR_ADDRESS 0x00000000 +#endif + +/* L1 */ +#ifndef L1_CACHE_ADDR +#define L1_CACHE_ADDR 0xFFD00000 +#endif +#ifndef L1_CACHE_SZ +#define L1_CACHE_SZ (32 * 1024) +#endif + + +#ifdef CORE_E500 + /* PowerPC e500 */ /* EREF: 7.5.3.2 - TLB Entry Page Size */ #define BOOKE_PAGESZ_4K 1 #define BOOKE_PAGESZ_16K 2 @@ -116,8 +145,53 @@ #define L1_CACHE_LINE_SHIFT 5 /* 32 bytes per L1 cache line */ -#else - /* MMU V2 - e6500 */ + /* P1021 LAW - Local Access Window (Memory Map) - RM 2.4 */ + #define LAWBAR_BASE(n) (0xC08 + (n * 0x20)) + #define LAWBAR(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x0)) + #define LAWAR(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x8)) + + #define LAWAR_ENABLE (1<<31) + #define LAWAR_TRGT_ID(id) (id<<20) + + /* P1021 Global Source/Target ID Assignments - RM Table 2-7 */ + #define LAW_TRGT_PCIE2 0x01 + #define LAW_TRGT_PCIE1 0x02 + #define LAW_TRGT_ELBC 0x04 /* eLBC (Enhanced Local Bus Controller) */ + #define LAW_TRGT_DDR 0x0F /* DDR Memory Controller */ + + /* P1021 2.4.2 - size is equal to 2^(enum + 1) */ + #define LAW_SIZE_4KB 0x0B + #define LAW_SIZE_8KB 0x0C + #define LAW_SIZE_16KB 0x0D + #define LAW_SIZE_32KB 0x0E + #define LAW_SIZE_64KB 0x0F + #define LAW_SIZE_128KB 0x10 + #define LAW_SIZE_256KB 0x11 + #define LAW_SIZE_512KB 0x12 + #define LAW_SIZE_1MB 0x13 + #define LAW_SIZE_2MB 0x14 + #define LAW_SIZE_4MB 0x15 + #define LAW_SIZE_8MB 0x16 + #define LAW_SIZE_16MB 0x17 + #define LAW_SIZE_32MB 0x18 + #define LAW_SIZE_64MB 0x19 + #define LAW_SIZE_128MB 0x1A + #define LAW_SIZE_256MB 0x1B + #define LAW_SIZE_512MB 0x1C + #define LAW_SIZE_1GB 0x1D + #define LAW_SIZE_2GB 0x1E + #define LAW_SIZE_4GB 0x1F + #define LAW_SIZE_8GB 0x20 + #define LAW_SIZE_16GB 0x21 + #define LAW_SIZE_32GB 0x22 + + +#elif defined(CORE_E6500) + /* PowerPC e6500 */ + + /* CoreNet on-chip interface between the core cluster and rest of SoC */ + #define USE_CORENET_INTERFACE + /* EREF 2.0: 6.5.3.2 - TLB Entry Page Size */ #define BOOKE_PAGESZ_4K 2 #define BOOKE_PAGESZ_8K 3 @@ -144,24 +218,68 @@ #define MAS1_TSIZE_MASK 0x00000F80 #define MAS1_TSIZE(x) (((x) << 7) & MAS1_TSIZE_MASK) - #define L1_CACHE_LINE_SHIFT 4 /* 64 bytes per L1 cache line */ - #endif /* MMU V1/V2 */ - - #ifndef L1_CACHE_ADDR - #define L1_CACHE_ADDR 0xFFD00000 - #endif - #ifndef L1_CACHE_SZ - #define L1_CACHE_SZ (32 * 1024) - #endif - - #ifndef L1_CACHE_LINE_SIZE - #define L1_CACHE_LINE_SIZE (1 << L1_CACHE_LINE_SHIFT) + #define L1_CACHE_LINE_SHIFT 6 /* 64 bytes per L1 cache line */ + /* CoreNet Platform Cache Base */ #define CPC_BASE (CCSRBAR + 0x10000) + + /* T2080 LAW - Local Access Window (Memory Map) - RM 2.4 */ + #define LAWBAR_BASE(n) (0xC00 + (n * 0x10)) + #define LAWBARH(n) *((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x0)) + #define LAWBARL(n) *((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x4)) + #define LAWAR(n) *((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x8)) + + #define LAWAR_ENABLE (1<<31) + #define LAWAR_TRGT_ID(id) (id<<20) + + /* T2080 Global Source/Target ID Assignments - RM Table 2-1 */ + #define LAW_TRGT_DDR_1 0x10 + #define LAW_TRGT_BMAN 0x18 /* Buffer Manager (BMan) (control) */ + #define LAW_TRGT_CORENET 0x1E + #define LAW_TRGT_IFC 0x1F /* Integrated Flash Controller */ + + /* T2080 2.4.3 - size is equal to 2^(enum + 1) */ + #define LAW_SIZE_4KB 0x0B + #define LAW_SIZE_8KB 0x0C + #define LAW_SIZE_16KB 0x0D + #define LAW_SIZE_32KB 0x0E + #define LAW_SIZE_64KB 0x0F + #define LAW_SIZE_128KB 0x10 + #define LAW_SIZE_256KB 0x11 + #define LAW_SIZE_512KB 0x12 + #define LAW_SIZE_1MB 0x13 + #define LAW_SIZE_2MB 0x14 + #define LAW_SIZE_4MB 0x15 + #define LAW_SIZE_8MB 0x16 + #define LAW_SIZE_16MB 0x17 + #define LAW_SIZE_32MB 0x18 + #define LAW_SIZE_64MB 0x19 + #define LAW_SIZE_128MB 0x1A + #define LAW_SIZE_256MB 0x1B + #define LAW_SIZE_512MB 0x1C + #define LAW_SIZE_1GB 0x1D + #define LAW_SIZE_2GB 0x1E + #define LAW_SIZE_4GB 0x1F + #define LAW_SIZE_8GB 0x20 + #define LAW_SIZE_16GB 0x21 + #define LAW_SIZE_32GB 0x22 + #define LAW_SIZE_64GB 0x23 + #define LAW_SIZE_128GB 0x24 + #define LAW_SIZE_256GB 0x25 + #define LAW_SIZE_512GB 0x26 + #define LAW_SIZE_1TB 0x27 + +#endif + +#ifndef L1_CACHE_LINE_SIZE +#define L1_CACHE_LINE_SIZE (1 << L1_CACHE_LINE_SHIFT) #endif -/* MMU Assist Registers */ +/* MMU Assist Registers + * E6500RM 2.13.10 + * E500CORERM 2.12.5 + */ #define MAS0 0x270 #define MAS1 0x271 #define MAS2 0x272 @@ -170,6 +288,43 @@ #define MAS7 0x3B0 #define MMUCSR0 0x3F4 /* MMU control and status register 0 */ +#define MAS0_TLBSEL_MSK 0x30000000 +#define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK) +#define MAS0_ESEL_MSK 0x0FFF0000 +#define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK) +#define MAS0_NV(x) ((x) & 0x00000FFF) + +#define MAS1_VALID 0x80000000 +#define MAS1_IPROT 0x40000000 /* can not be invalidated by tlbivax */ +#define MAS1_TID(x) (((x) << 16) & 0x3FFF0000) +#define MAS1_TS 0x00001000 + +#define MAS2_EPN 0xFFFFF000 /* Effective page number */ +#define MAS2_X0 0x00000040 +#define MAS2_X1 0x00000020 +#define MAS2_W 0x00000010 /* Write-through */ +#define MAS2_I 0x00000008 /* Caching-inhibited */ +#define MAS2_M 0x00000004 /* Memory coherency required */ +#define MAS2_G 0x00000002 /* Guarded */ +#define MAS2_E 0x00000001 /* Endianness - 0=big, 1=little */ + +#define MAS3_RPN 0xFFFFF000 /* Real page number */ +/* User attribute bits */ +#define MAS3_U0 0x00000200 +#define MAS3_U1 0x00000100 +#define MAS3_U2 0x00000080 +#define MAS3_U3 0x00000040 +#define MAS3_UX 0x00000020 +/* User and supervisor read, write, and execute permission bits */ +#define MAS3_SX 0x00000010 +#define MAS3_UW 0x00000008 +#define MAS3_SW 0x00000004 +#define MAS3_UR 0x00000002 +#define MAS3_SR 0x00000001 + +#define MAS7_RPN 0xFF000000 /* Real page number - upper 8-bits */ + + /* L1 Cache */ #define L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ #define L1CSR0 0x3F2 /* L1 Data */ @@ -245,47 +400,6 @@ #define SPRN_TBWL 0x11C /* Time Base Write Lower Register */ #define SPRN_TBWU 0x11D /* Time Base Write Upper Register */ - -/* MMU Assist Registers - * E6500RM 2.13.10 - * E500CORERM 2.12.5 - */ -#define MAS0_TLBSEL_MSK 0x30000000 -#define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK) -#define MAS0_ESEL_MSK 0x0FFF0000 -#define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK) -#define MAS0_NV(x) ((x) & 0x00000FFF) - -#define MAS1_VALID 0x80000000 -#define MAS1_IPROT 0x40000000 /* can not be invalidated by tlbivax */ -#define MAS1_TID(x) (((x) << 16) & 0x3FFF0000) -#define MAS1_TS 0x00001000 - -#define MAS2_EPN 0xFFFFF000 /* Effective page number */ -#define MAS2_X0 0x00000040 -#define MAS2_X1 0x00000020 -#define MAS2_W 0x00000010 /* Write-through */ -#define MAS2_I 0x00000008 /* Caching-inhibited */ -#define MAS2_M 0x00000004 /* Memory coherency required */ -#define MAS2_G 0x00000002 /* Guarded */ -#define MAS2_E 0x00000001 /* Endianness - 0=big, 1=little */ - -#define MAS3_RPN 0xFFFFF000 /* Real page number */ -/* User attribute bits */ -#define MAS3_U0 0x00000200 -#define MAS3_U1 0x00000100 -#define MAS3_U2 0x00000080 -#define MAS3_U3 0x00000040 -#define MAS3_UX 0x00000020 -/* User and supervisor read, write, and execute permission bits */ -#define MAS3_SX 0x00000010 -#define MAS3_UW 0x00000008 -#define MAS3_SW 0x00000004 -#define MAS3_UR 0x00000002 -#define MAS3_SR 0x00000001 - -#define MAS7_RPN 0xFF000000 /* Real page number - upper 8-bits */ - #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ #define TLBNCFG_NENTRY_MASK 0x00000FFF diff --git a/hal/nxp_t2080.c b/hal/nxp_t2080.c index 1bb6bf99..bdbd0f20 100644 --- a/hal/nxp_t2080.c +++ b/hal/nxp_t2080.c @@ -24,6 +24,8 @@ #include "nxp_ppc.h" +/* Tested on T2080E Rev 1.1, e6500 core 2.0, PVR 8040_0120 and SVR 8538_0011 */ + /* T2080 */ #define SYS_CLK (600000000) @@ -56,56 +58,6 @@ #define GET_PHYS_HIGH(addr) (((uint64_t)(addr)) >> 32) -/* T2080 LAW - Local Access Window (Memory Map) - RM 2.4 */ -#define LAWBAR_BASE(n) (CCSRBAR + 0xC00 + (n * 0x10)) -#define LAWBARH(n) *((volatile uint32_t*)(LAWBAR_BASE(n) + 0x0)) -#define LAWBARL(n) *((volatile uint32_t*)(LAWBAR_BASE(n) + 0x4)) -#define LAWAR(n) *((volatile uint32_t*)(LAWBAR_BASE(n) + 0x8)) - -#define LAWAR_ENABLE (1<<31) -#define LAWAR_TRGT_ID(id) (id<<20) - -/* T2080 Global Source/Target ID Assignments - RM Table 2-1 */ -enum law_target_id { - LAW_TRGT_DDR_1 = 0x10, - LAW_TRGT_BMAN = 0x18, /* Buffer Manager (BMan) (control) */ - LAW_TRGT_CORENET = 0x1E, - LAW_TRGT_IFC = 0x1F, /* Integrated Flash Controller */ -}; - -/* T2080 2.4.3 - size is equal to 2^(enum + 1) */ -enum law_sizes { - LAW_SIZE_4KB = 0x0B, - LAW_SIZE_8KB, - LAW_SIZE_16KB, - LAW_SIZE_32KB, - LAW_SIZE_64KB, - LAW_SIZE_128KB, /* 0x10 */ - LAW_SIZE_256KB, - LAW_SIZE_512KB, - LAW_SIZE_1MB, - LAW_SIZE_2MB, - LAW_SIZE_4MB, - LAW_SIZE_8MB, - LAW_SIZE_16MB, - LAW_SIZE_32MB, - LAW_SIZE_64MB, - LAW_SIZE_128MB, - LAW_SIZE_256MB, /* 0x1B */ - LAW_SIZE_512MB, - LAW_SIZE_1GB, - LAW_SIZE_2GB, - LAW_SIZE_4GB, - LAW_SIZE_8GB, /* 0x20 */ - LAW_SIZE_16GB, - LAW_SIZE_32GB, - LAW_SIZE_64GB, - LAW_SIZE_128GB, - LAW_SIZE_256GB, - LAW_SIZE_512GB, - LAW_SIZE_1TB, -}; - /* T2080 IFC (Integrated Flash Controller) - RM 13.3 */ #define IFC_BASE (CCSRBAR + 0x00124000) #define IFC_MAX_BANKS 8 diff --git a/hal/nxp_t2080.ld b/hal/nxp_t2080.ld index 00f8bfec..47089974 100644 --- a/hal/nxp_t2080.ld +++ b/hal/nxp_t2080.ld @@ -14,7 +14,7 @@ MEMORY FLASH (rx) : ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @BOOTLOADER_PARTITION_SIZE@ /* L2 as SRAM - 256KB */ - RAM (rwx) : ORIGIN = 0xFEC20000, LENGTH = 0x40000 + RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 0x40000 /* DDR - 2GB */ DRAM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x7FFFFFFF diff --git a/src/boot_ppc_start.S b/src/boot_ppc_start.S index 1302f13b..216eb34f 100644 --- a/src/boot_ppc_start.S +++ b/src/boot_ppc_start.S @@ -301,18 +301,19 @@ setup_interrupts: #endif /* If needed, relocate CCSRBAR */ -#if CCSRBAR_DEF != CCSRBAR +#if CCSRBAR_DEF != CCSRBAR_PHYS + /* Use R8 = new, R9 = old virtual */ - lis r8, CCSRBAR@h - ori r8, r8, CCSRBAR@l - lis r9, (CCSRBAR + 0x1000)@h - ori r9, r9, (CCSRBAR + 0x1000)@l + lis r8, CCSRBAR@h + ori r8, r8, CCSRBAR@l + lis r9, (CCSRBAR + 0x1000)@h + ori r9, r9, (CCSRBAR + 0x1000)@l create_temp_ccsr: /* Create a temporary TLB entry for new and old location */ /* CCSRBAR: TLB 0, Entry 0, Supervisor R/W, IG, TS=0, 4KB */ set_tlb(0, 0, - CCSRBAR, CCSRBAR, 0, + CCSRBAR, CCSRBAR, CCSRBAR_PHYS_HIGH, MAS3_SR | MAS3_SW, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_4K, 0, r3); @@ -325,20 +326,63 @@ verify_old_ccsr: /* verify the TLB is for old one */ lis r0, CCSRBAR_DEF@h ori r0, r0, CCSRBAR_DEF@l - lwz r1, 0(r9) +#ifdef USE_CORENET_INTERFACE + lwz r1, 4(r9) /* CCSRBARL */ +#else + lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ slwi r1, r1, 12 +#endif cmpl 0, r0, r1 infinite_debug_loop: bne infinite_debug_loop /* should not get here */ +#ifdef USE_CORENET_INTERFACE +ccsr_temp_law: + /* CCSR - LAW0 (Temp CoreNet 4K) */ + #define CCSR_TEMP_LAW (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_CORENET) | LAW_SIZE_4KB) + lis r0, CCSRBAR_PHYS_HIGH@h + ori r0, r0, CCSRBAR_PHYS_HIGH@l + lis r1, CCSRBAR_DEF@h + ori r1, r1, CCSRBAR_DEF@l + lis r2, CCSR_TEMP_LAW@h + ori r2, r2, CCSR_TEMP_LAW@l + stw r0, LAWBAR_BASE(0)(r9) /* LAWBARH */ + stw r1, LAWBAR_BASE(0)+4(r9) /* LAWBARL */ + sync + stw r2, LAWBAR_BASE(0)+8(r9) /* LAWAR */ + lwz r2, LAWBAR_BASE(0)+8(r9) /* read back LAWAR (per 2.3.2 Configuring Local Access Windows) */ + isync + +read_old_ccsr: + lwz r0, 0(r9) + lwz r0, 4(r9) + isync + +write_new_ccsrbar: + lis r0, CCSRBAR_PHYS_HIGH@h + ori r0, r0, CCSRBAR_PHYS_HIGH@l + lis r1, CCSRBAR@h + ori r1, r1, CCSRBAR@l + #define CCSRAR_C 0x80000000 /* Commit */ + lis r2, CCSRAR_C@h + ori r2, r2, CCSRAR_C@l + stw r0, 0(r9) /* CCSRBARH */ + sync + stw r1, 4(r9) /* CCSRBARL */ + sync + + stw r2, 8(r9) /* commit */ + sync + +#else write_new_ccsrbar: /* Read current value of CCSBAR - forces all accesses to complete */ sync lwz r0, 0(r9) isync /* write new CCSBAR */ - lis r0, (CCSRBAR >> 12)@h - ori r0, r0, (CCSRBAR >> 12)@l + lis r0, (CCSRBAR_PHYS_HIGH << 20) | (CCSRBAR >> 12)@h + ori r0, r0, (CCSRBAR_PHYS_HIGH << 20) | (CCSRBAR >> 12)@l stw r0, 0(r9) sync isync @@ -346,11 +390,14 @@ write_new_ccsrbar: /* Read current value of CCSRBAR from new location */ lwz r0, 0(r8) isync +#endif +invalidate_temp_tlb: /* invalidate TLB 0 */ li r3, 0x04 /* L2TLB0_FI: TLB0 flash invalidate (write 1 to invalidate) */ mtspr MMUCSR0, r3 -#endif +#endif /* CCSRBAR_DEF != CCSRBAR_PHYS */ + #ifndef BUILD_LOADER_STAGE1 /* TLBs */ @@ -370,7 +417,53 @@ ccsr_tlb: MAS3_SX | MAS3_SR | MAS3_SW, MAS2_I | MAS2_G, 0, CCSRBAR_SIZE, 1, r3); +#ifdef CORE_E6500 +ccsr_law: + /* CCSR - LAW0 (CoreNet 16MB) */ + #define CCSR_LAW (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_CORENET) | LAW_SIZE_16MB) + lis r9, CCSRBAR + LAWBAR_BASE(0)@h + ori r9, r9, CCSRBAR + LAWBAR_BASE(0)@l + lis r0, CCSRBAR_PHYS_HIGH@h + ori r0, r0, CCSRBAR_PHYS_HIGH@l + lis r1, CCSRBAR@h + ori r1, r1, CCSRBAR@l + lis r2, CCSR_LAW@h + ori r2, r2, CCSR_LAW@l + stw r0, 0(r9) /* LAWBARH */ + stw r1, 4(r9) /* LAWBARL */ + sync + stw r2, 8(r9) /* LAWAR */ + lwz r2, 8(r9) /* read back LAWAR (per 2.3.2 Configuring Local Access Windows) */ + isync +#endif /* CORE_E6500 */ + #ifdef FLASH_BASE_ADDR +#ifdef CORE_E6500 + /* Memory Mapped NOR Flash (128MB) at 0xE8000000 */ +flash_law: + /* FLASH - LAW1 (IFC 128MB) */ + #define FLASH_LAW (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_IFC) | LAW_SIZE_128MB) + lis r9, CCSRBAR + LAWBAR_BASE(1)@h + ori r9, r9, CCSRBAR + LAWBAR_BASE(1)@l + lis r0, FLASH_BASE_PHYS_HIGH@h + ori r0, r0, FLASH_BASE_PHYS_HIGH@l + lis r1, FLASH_BASE_ADDR@h + ori r1, r1, FLASH_BASE_ADDR@l + lis r2, FLASH_LAW@h + ori r2, r2, FLASH_LAW@l + stw r0, 0(r9) /* LAWBARH */ + stw r1, 4(r9) /* LAWBARL */ + sync + stw r2, 8(r9) /* LAWAR */ + lwz r2, 8(r9) /* read back LAWAR (per 2.3.2 Configuring Local Access Windows) */ + isync +flash_tlb: + /* Flash: TLB 1, Entry 7, Super X/R, W, TS=0, 128M, IPROT */ + set_tlb(1, 7, + FLASH_BASE_ADDR, FLASH_BASE_ADDR, FLASH_BASE_PHYS_HIGH, + MAS3_SX | MAS3_SR, MAS2_W, 0, + BOOKE_PAGESZ_128M, 1, r3); +#else flash_tlb: /* For TS/AS=1 map boot ROM */ /* Flash: TLB 1, Entry 7, Super X/R/W, IG, TS=0, 1M, IPROT */ @@ -378,7 +471,8 @@ flash_tlb: FLASH_BASE_ADDR, FLASH_BASE_ADDR, 0, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_1M, 1, r3); -#endif +#endif /* CORE_E6500 */ +#endif /* FLASH_BASE_ADDR */ #ifdef ENABLE_DDR #ifdef BUILD_LOADER_STAGE1 @@ -400,16 +494,36 @@ flash_tlb: BOOKE_PAGESZ_256M, 0, r3); #endif -#if defined(ENABLE_L2_CACHE) && defined(MMU_V2) +#ifdef CORE_E6500 -create_ccsr_l2_tlb: - /* L2 0xFEC20000: TLB 1, Entry 9, Supervisor X/R/W, IG, TS=0, 512KB, IPROT */ +#ifdef ENABLE_L2_CACHE + +#ifdef L2SRAM_ADDR +l2_sram_law: + /* L2 SRAM - LAW2 (DDR 256KB) */ + #define L2SRAM_LAW (LAWAR_ENABLE | LAWAR_TRGT_ID(LAW_TRGT_DDR_1) | LAW_SIZE_256KB) + lis r9, CCSRBAR + LAWBAR_BASE(2)@h + ori r9, r9, CCSRBAR + LAWBAR_BASE(2)@l + li r0, 0 + lis r1, L2SRAM_ADDR@h + ori r1, r1, L2SRAM_ADDR@l + lis r2, L2SRAM_LAW@h + ori r2, r2, L2SRAM_LAW@l + stw r0, 0(r9) /* LAWBARH */ + stw r1, 4(r9) /* LAWBARL */ + sync + stw r2, 8(r9) /* LAWAR */ + lwz r2, 8(r9) /* read back LAWAR (per 2.3.2 Configuring Local Access Windows) */ + isync + +l2_sram_tlb: + /* L2 0xFEC20000: TLB 1, Entry 9, Supervisor X/R/W, M, TS=0, 512KB, IPROT */ set_tlb(1, 9, L2SRAM_ADDR, L2SRAM_ADDR, 0, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0, BOOKE_PAGESZ_512K, 1, r3); -setup_l2_sram: +l2_setup_sram: /* 8.2 CoreNet Platform Cache (CPC) Memory Map */ #define CPCCSR0 (0x000) #define CPCSRCR1 (0x100) @@ -451,13 +565,14 @@ setup_l2_sram: isync stw r0, CPCCSR0(r1) mbar +#endif /* Disable speculation */ lwz r0, CPCHDBCR0(r1) oris r0, r0, CPCHDBCR0_SPEC_DIS@h stw r0, CPCHDBCR0(r1) -setup_l2_cache: +l2_setup_cache: /* L2 Cache Control - E6500CORERM 2.2.3 Memory-mapped registers (MMRs) */ #define L2_CLUSTER_BASE(n) (CCSRBAR + 0xC20000 + (n * 0x40000)) #define L2CSR0 (0x000) /* L2 Cache Control and Status 0 */ @@ -484,10 +599,10 @@ setup_l2_cache: stw r1, L2CSR0(r5) /* poll till invalidate and lock bits are cleared */ -poll_l2_invclear: +l2_poll_invclear: lwz r4, L2CSR0(r5) and. r4, r1, r4 - bne poll_l2_invclear + bne l2_poll_invclear isync /* enable L2 with parity */ @@ -501,34 +616,21 @@ poll_l2_invclear: li r4, 32 stw r4, L2CSR1(r5) +#ifdef L2SRAM_ADDR l2_sram_init: /* clear 8 bytes at a time */ lis r2, (L2SRAM_ADDR - 8)@h ori r2, r2, (L2SRAM_ADDR - 8)@l lis r3, (L2SRAM_SIZE / 8)@h + ori r3, r3, (L2SRAM_SIZE / 8)@l mtctr r3 li r3, 0 l2_sram_init_loop: stdu r3, 8(r2) bdnz l2_sram_init_loop -#endif /* ENABLE_L2_CACHE && MMU_V2 */ - -#ifdef MMU_V2 -set_stack_as: - - lis r6, (MSR_IS | MSR_DS | MSR_DE)@h - ori r6, r6, (MSR_IS | MSR_DS | MSR_DE)@l - lis r7, switch_as@h - ori r7, r7, switch_as@l - - mtspr SRR0, r7 - mtspr SRR1, r6 - - /* return from interrupt call and switch to AS=1 (aka TS=1) */ - rfi - -switch_as: -#endif /* MMU_V2 */ +#endif /* L2SRAM_ADDR */ +#endif /* ENABLE_L2_CACHE */ +#endif /* CORE_E6500 */ setup_l1: #ifdef ENABLE_L1_CACHE @@ -601,19 +703,20 @@ setup_ts0: GET_GOT #endif +#ifdef USE_LONG_JUMP + /* load absolute address into "LR" and branch return to it */ + /* Enables long jump in 32-bit */ + lis r3, boot_entry_C@h + ori r3, r3, boot_entry_C@l + mtlr r3 + blr +#else /* jump to wolfboot */ b boot_entry_C /* no return */ - -#ifdef ENABLE_INTERRUPTS -/* Interrupt functions */ -.section .isr_vector -.align 8 -isr_empty: - nop - rfi #endif +/* -- Assembly Functions -- */ /* * unsigned long long get_ticks(void); * @@ -658,6 +761,7 @@ get_pc: mtlr r0 blr +/* L1 Cache Helpers */ .global invalidate_icache invalidate_icache: mfspr r4, L1CSR1 @@ -824,6 +928,15 @@ in_ram: #endif /* USE_GOT */ +#ifdef ENABLE_INTERRUPTS +/* Interrupt functions */ +.section .isr_vector +.align 8 +isr_empty: + nop + rfi +#endif + /* reset entry point - must be at end of .S */ .section .reset, "ax" b _reset