WolfSSL
/
wolfBoot
mirror of https://github.com/wolfSSL/wolfBoot.git
1
0
Fork 0
Code Issues Releases Wiki Activity

Initial support for STM32H5, sunny day boot 

STM32H5: Tested sunny day boot

- Temporarily decreased clock speed to 125MHz
- Test app working
- Re-mapped Nucleo board LEDs
- Tested on STM32H563ZI
pull/420/head
Daniele Lacamera 2024-03-15 14:28:36 +01:00
parent dc92ac3721
commit 19fdbb8998
18 changed files with 1250 additions and 977 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
arch.mk
View File

@ -164,6 +164,21 @@ ifeq ($(ARCH),ARM)
SPI_TARGET=stm32
endif
ifeq ($(TARGET),stm32h5)
CORTEX_M33=1
CFLAGS+=-Ihal
ARCH_FLASH_OFFSET=0x08000000
ifeq ($(TZEN),1)
WOLFBOOT_ORIGIN=0x0C000000
else
WOLFBOOT_ORIGIN=0x08000000
endif
ifneq ($(TZEN),1)
LSCRIPT_IN=hal/$(TARGET)-ns.ld
endif
SPI_TARGET=stm32
endif
## Cortex-M CPU
ifeq ($(CORTEX_M33),1)
CFLAGS+=-mcpu=cortex-m33 -DCORTEX_M33

27
config/examples/stm32h5-nonsecure-dualbank.config 100644
View File

@ -0,0 +1,27 @@
ARCH?=ARM
TZEN?=0
TARGET?=stm32h5
SIGN?=ECC256
HASH?=SHA256
DEBUG?=1
VTOR?=1
CORTEX_M0?=0
CORTEX_M33?=1
NO_ASM?=0
NO_MPU=1
EXT_FLASH?=0
SPI_FLASH?=0
ALLOW_DOWNGRADE?=0
NVM_FLASH_WRITEONCE?=1
WOLFBOOT_VERSION?=1
V?=0
SPMATH?=1
RAM_CODE?=0
DUALBANK_SWAP?=1
WOLFBOOT_PARTITION_SIZE?=0x20000
WOLFBOOT_SECTOR_SIZE?=0x2000
WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08100000
WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x817F000
WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x81FE000
FLAGS_HOME=0
DISABLE_BACKUP=0

27
config/examples/stm32h5.config 100644
View File

@ -0,0 +1,27 @@
ARCH?=ARM
TZEN?=0
TARGET?=stm32h5
SIGN?=ECC256
HASH?=SHA256
DEBUG?=1
VTOR?=1
CORTEX_M0?=0
CORTEX_M33?=1
NO_ASM?=0
NO_MPU=1
EXT_FLASH?=0
SPI_FLASH?=0
ALLOW_DOWNGRADE?=0
NVM_FLASH_WRITEONCE?=1
WOLFBOOT_VERSION?=1
V?=0
SPMATH?=1
RAM_CODE?=0
DUALBANK_SWAP?=0
WOLFBOOT_PARTITION_SIZE?=0x20000
WOLFBOOT_SECTOR_SIZE?=0x2000
WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08100000
WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x817F000
WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x81FE000
FLAGS_HOME=0
DISABLE_BACKUP=0

16
hal/stm32_tz.c
View File

@ -29,6 +29,10 @@
#include "hal/stm32u5.h"
#endif
#ifdef PLATFORM_stm32h5
#include "hal/stm32h5.h"
#endif
#include "image.h"
#include "hal.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (!defined(FLAGS_HOME) || !defined(DISABLE_BACKUP))
@ -81,15 +85,25 @@ void hal_tz_claim_nonsecure_area(uint32_t address, int len)
hal_flash_wait_complete(0);
hal_flash_nonsecure_lock();
/* Erase claimed non-secure page, in secure mode */
#ifndef PLATFORM_stm32h5
reg = FLASH_CR & (~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER | FLASH_CR_BKER | FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_MER2));
FLASH_CR = reg | ((page_n << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER | FLASH_CR_BKER);
FLASH_CR = reg | ((page_n << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER);
#else
reg = FLASH_CR & (~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT) | FLASH_CR_SER | FLASH_CR_BER | FLASH_CR_PG | FLASH_CR_MER));
FLASH_CR = reg | ((page_n << FLASH_CR_PNB_SHIFT) | FLASH_CR_SER);
#endif
DMB();
FLASH_CR |= FLASH_CR_STRT;
ISB();
hal_flash_wait_complete(0);
address += FLASH_PAGE_SIZE;
}
#ifndef PLATFORM_stm32h5
FLASH_CR &= ~FLASH_CR_PER ;
#else
FLASH_CR &= ~FLASH_CR_SER ;
#endif
}
#else
#define claim_nonsecure_area(...) do{}while(0)

50
hal/stm32h5-ns.ld 100644
View File

@ -0,0 +1,50 @@
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = @BOOTLOADER_PARTITION_SIZE@
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* mapping TCM only */
}
SECTIONS
{
.text :
{
_start_text = .;
KEEP(*(.isr_vector))
*(.text*)
*(.rodata*)
. = ALIGN(4);
_end_text = .;
} > FLASH
.edidx :
{
. = ALIGN(4);
*(.ARM.exidx*)
} > FLASH
_stored_data = .;
.data : AT (_stored_data)
{
_start_data = .;
KEEP(*(.data*))
. = ALIGN(4);
KEEP(*(.ramcode))
. = ALIGN(4);
_end_data = .;
} > RAM
.bss (NOLOAD) :
{
_start_bss = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
_end_bss = .;
__bss_end__ = .;
_end = .;
} > RAM
. = ALIGN(4);
}
END_STACK = ORIGIN(RAM) + LENGTH(RAM);

418
hal/stm32h5.c 100644
View File

@ -0,0 +1,418 @@
/* stm32h5.c
*
* Copyright (C) 2024 wolfSSL Inc.
*
* This file is part of wolfBoot.
*
* wolfBoot is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* wolfBoot is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
*/
#include <stdint.h>
#include <image.h>
#include <string.h>
#include "hal.h"
#include "hal/stm32h5.h"
static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
{
uint32_t reg = FLASH_ACR;
if ((reg & FLASH_ACR_LATENCY_MASK) < waitstates)
do {
FLASH_ACR = (reg & ~FLASH_ACR_LATENCY_MASK) | waitstates ;
}
while ((FLASH_ACR & FLASH_ACR_LATENCY_MASK) != waitstates);
}
void RAMFUNCTION hal_flash_wait_complete(uint8_t bank)
{
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
;
#if (TZ_SECURE())
while ((FLASH_NS_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
;
#endif
}
void RAMFUNCTION hal_flash_clear_errors(uint8_t bank)
{
FLASH_SR |= ( FLASH_SR_WBNE | FLASH_SR_DBNE );
#if (TZ_SECURE())
FLASH_NS_SR |= ( FLASH_SR_WBNE | FLASH_SR_DBNE );
#endif
}
int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
{
int i = 0;
uint32_t *src, *dst;
uint32_t dword[2];
volatile uint32_t *sr, *cr;
cr = &FLASH_CR;
sr = &FLASH_SR;
hal_flash_clear_errors(0);
src = (uint32_t *)data;
dst = (uint32_t *)address;
#if (TZ_SECURE())
if (address >= FLASH_BANK2_BASE)
hal_tz_claim_nonsecure_area(address, len);
/* Convert into secure address space */
dst = (uint32_t *)((address & (~FLASHMEM_ADDRESS_SPACE)) | FLASH_SECURE_MMAP_BASE);
#endif
while (i < len) {
dword[0] = src[i >> 2];
dword[1] = src[(i >> 2) + 1];
*cr |= FLASH_CR_PG;
dst[i >> 2] = dword[0];
ISB();
dst[(i >> 2) + 1] = dword[1];
hal_flash_wait_complete(0);
if ((*sr & FLASH_SR_EOP) != 0)
*sr |= FLASH_SR_EOP;
*cr &= ~FLASH_CR_PG;
i+=8;
}
#if (TZ_SECURE())
hal_tz_release_nonsecure_area();
#endif
return 0;
}
void RAMFUNCTION hal_flash_unlock(void)
{
hal_flash_wait_complete(0);
if ((FLASH_CR & FLASH_CR_LOCK) != 0) {
FLASH_KEYR = FLASH_KEY1;
DMB();
FLASH_KEYR = FLASH_KEY2;
DMB();
while ((FLASH_CR & FLASH_CR_LOCK) != 0)
;
}
}
void RAMFUNCTION hal_flash_lock(void)
{
hal_flash_wait_complete(0);
if ((FLASH_CR & FLASH_CR_LOCK) == 0)
FLASH_CR |= FLASH_CR_LOCK;
}
void RAMFUNCTION hal_flash_opt_unlock(void)
{
hal_flash_wait_complete(0);
if ((FLASH_OPTCR & FLASH_OPTCR_OPTLOCK) != 0) {
FLASH_OPTKEYR = FLASH_OPTKEY1;
DMB();
FLASH_OPTKEYR = FLASH_OPTKEY2;
DMB();
while ((FLASH_CR & FLASH_CR_LOCK) != 0)
;
}
}
void RAMFUNCTION hal_flash_opt_lock(void)
{
FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT;
hal_flash_wait_complete(0);
if ((FLASH_OPTCR & FLASH_OPTCR_OPTLOCK) == 0)
FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
}
int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
{
uint32_t end_address;
uint32_t p;
hal_flash_clear_errors(0);
if (len == 0)
return -1;
if (address < ARCH_FLASH_OFFSET)
return -1;
end_address = address + len - 1;
for (p = address; p < end_address; p += FLASH_PAGE_SIZE) {
uint32_t reg;
uint32_t base;
uint32_t bker = 0;
if ((((FLASH_OPTCR & FLASH_OPTCR_SWAP_BANK) == 0) && (p <= FLASH_TOP)) ||
(p < FLASH_BANK2_BASE)) {
base = FLASHMEM_ADDRESS_SPACE;
}
else if(p >= (FLASH_BANK2_BASE) && (p <= (FLASH_TOP) ))
{
#if TZ_SECURE()
/* When in secure mode, skip erasing non-secure pages: will be erased upon claim */
return 0;
#endif
bker = FLASH_CR_BER;
base = FLASH_BANK2_BASE;
} else {
FLASH_CR &= ~FLASH_CR_SER ;
return 0; /* Address out of range */
}
reg = FLASH_CR & (~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT) | FLASH_CR_BER));
reg |= ((((p - base) >> 11) << FLASH_CR_PNB_SHIFT) | FLASH_CR_SER | bker );
FLASH_CR = reg;
DMB();
FLASH_CR |= FLASH_CR_STRT;
hal_flash_wait_complete(0);
}
/* If the erase operation is completed, disable the associated bits */
FLASH_CR &= ~FLASH_CR_SER ;
return 0;
}
static void clock_pll_off(void)
{
uint32_t reg32;
/* Select HSI as SYSCLK source. */
RCC_CFGR1 &= ~(0x07 << RCC_CFGR1_SW_SHIFT);
DMB();
/* Turn off PLL1 */
RCC_PLL1CFGR &= ~RCC_PLL1CFGR_PLL1PEN;
DMB();
RCC_CR &= ~RCC_CR_PLL1ON;
DMB();
/* Wait until PLL1 is disabled */
while ((RCC_CR & RCC_CR_PLL1RDY) != 0)
;
}
/*This implementation will setup MSI 48 MHz as PLL Source Mux, PLLCLK as System Clock Source*/
static void clock_pll_on(void)
{
uint32_t reg32;
uint32_t plln, pllm, pllq, pllp, pllr, hpre, apb1pre, apb2pre, apb3pre, flash_waitstates;
/* Select clock parameters (CPU Speed = 125 MHz) */
pllm = 4;
plln = 125; /* TODO: increase to 250 MHz */
pllp = 2;
pllq = 2;
pllr = 2;
flash_waitstates = 5;
/* Disable PLL1 */
RCC_CR &= ~RCC_CR_PLL1ON;
/* Wait until PLL1 is disabled */
while ((RCC_CR & RCC_CR_PLL1RDY) != 0)
;
/* Set flash wait states */
flash_set_waitstates(flash_waitstates);
/* PLL Oscillator configuration */
RCC_CR |= RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_HSEEXT;
/* Wait until HSE is Ready */
while ((RCC_CR & RCC_CR_HSERDY) == 0)
;
/* Configure PLL1 div/mul factors */
reg32 = RCC_PLL1CFGR;
reg32 &= ~((0x3F << RCC_PLL1CFGR_PLL1M_SHIFT) | (0x03));
reg32 |= (pllm << RCC_PLL1CFGR_PLL1M_SHIFT) | RCC_PLL1CFGR_PLL1SRC_HSE;
RCC_PLL1CFGR = reg32;
DMB();
RCC_PLL1DIVR = ((plln - 1) << RCC_PLL1DIVR_DIVN_SHIFT) | ((pllp - 1) << RCC_PLL1DIVR_DIVP_SHIFT) |
((pllq - 1) << RCC_PLL1DIVR_DIVQ_SHIFT) | ((pllr - 1) << RCC_PLL1DIVR_DIVR_SHIFT);
DMB();
/* Disable Fractional PLL */
RCC_PLL1CFGR &= ~RCC_PLL1CFGR_PLL1FRACEN;
DMB();
/* Configure Fractional PLL factor */
RCC_PLL1FRACR = 0x00000000;
DMB();
/* Enable Fractional PLL */
RCC_PLL1CFGR |= RCC_PLL1CFGR_PLL1FRACEN;
DMB();
/* Select PLL1 Input frequency range: VCI */
RCC_PLL1CFGR |= RCC_PLL1CFGR_RGE_1_2 << RCC_PLL1CFGR_PLL1RGE_SHIFT;
/* Select PLL1 Output frequency range: VCO = 0 */
RCC_PLL1CFGR &= ~RCC_PLL1CFGR_PLL1VCOSEL;
DMB();
/* Enable PLL1 system clock out (DIV: P) */
RCC_PLL1CFGR |= RCC_PLL1CFGR_PLL1PEN;
/* Enable PLL1 */
RCC_CR |= RCC_CR_PLL1ON;
/* Set up APB3, 2, 1 and AHB prescalers */
hpre = RCC_AHB_PRESCALER_DIV_NONE;
apb1pre = RCC_APB_PRESCALER_DIV_NONE;
apb2pre = RCC_APB_PRESCALER_DIV_NONE;
apb3pre = RCC_APB_PRESCALER_DIV_NONE;
reg32 = RCC_CFGR2;
reg32 &= ~( (0x0F << RCC_CFGR2_HPRE_SHIFT) |
(0x07 << RCC_CFGR2_PPRE1_SHIFT) |
(0x07 << RCC_CFGR2_PPRE2_SHIFT) |
(0x07 << RCC_CFGR2_PPRE3_SHIFT));
reg32 |= ((hpre) << RCC_CFGR2_HPRE_SHIFT) | ((apb1pre) << RCC_CFGR2_PPRE1_SHIFT) |
((apb2pre) << RCC_CFGR2_PPRE2_SHIFT) | ((apb3pre) << RCC_CFGR2_PPRE3_SHIFT);
RCC_CFGR2 = reg32;
DMB();
/* Wait until PLL1 is Ready */
while ((RCC_CR & RCC_CR_PLL1RDY) == 0)
;
/* Set PLL as clock source */
reg32 = RCC_CFGR1 & (~RCC_CFGR1_SW_MASK);
RCC_CFGR1 = reg32 | RCC_CFGR1_SW_PLL1;
DMB();
/* Wait until selection of PLL as source is complete */
while ((RCC_CFGR1 & (RCC_CFGR1_SW_PLL1 << RCC_CFGR1_SWS_SHIFT)) == 0)
;
}
#if TZ_SECURE()
static void periph_unsecure()
{
uint32_t pin;
/*Enable clock for User LED GPIOs */
RCC_AHB2_CLOCK_ER|= LED_AHB2_ENABLE;
/* Enable clock for LPUART1 */
RCC_APB2_CLOCK_ER |= UART1_APB2_CLOCK_ER_VAL;
PWR_CR2 |= PWR_CR2_IOSV;
/*Un-secure User LED GPIO pins */
#ifdef STM32_DISCOVERY
GPIO_SECCFGR(GPIOD_BASE) &= ~(1<<LED_USR_PIN);
GPIO_SECCFGR(GPIOG_BASE) &= ~(1<<LED_BOOT_PIN);
#else /* Nucleo board */
GPIO_SECCFGR(GPIOA_BASE) &= ~(1<<LED_BOOT_PIN);
GPIO_SECCFGR(GPIOB_BASE) &= ~(1<<LED_USR_PIN);
GPIO_SECCFGR(GPIOC_BASE) &= ~(1<<LED_EXTRA_PIN);
#endif
/* Unsecure LPUART1 */
TZSC_PRIVCFGR2 &= ~(TZSC_PRIVCFG2_LPUARTPRIV);
GPIO_SECCFGR(GPIOG_BASE) &= ~(1<<UART1_TX_PIN);
GPIO_SECCFGR(GPIOG_BASE) &= ~(1<<UART1_RX_PIN);
}
#endif
#define OPTR_SWAP_BANK (1 << 20)
#define AIRCR *(volatile uint32_t *)(0xE000ED0C)
#define AIRCR_VKEY (0x05FA << 16)
#define AIRCR_SYSRESETREQ (1 << 2)
static void RAMFUNCTION stm32h5_reboot(void)
{
AIRCR = AIRCR_SYSRESETREQ | AIRCR_VKEY;
while(1)
;
}
#if defined(DUALBANK_SWAP) && defined(__WOLFBOOT)
void RAMFUNCTION hal_flash_dualbank_swap(void)
{
uint32_t cur_opts;
hal_flash_unlock();
hal_flash_opt_unlock();
cur_opts = (FLASH_OPTCR & FLASH_OPTCR_SWAP_BANK) >> 31;
if (cur_opts)
FLASH_SECCR &= ~(FLASH_SECCR_BKSEL);
else
FLASH_SECCR |= FLASH_SECCR_BKSEL;
hal_flash_opt_lock();
hal_flash_lock();
stm32h5_reboot();
}
static uint8_t bootloader_copy_mem[BOOTLOADER_SIZE];
static void RAMFUNCTION fork_bootloader(void)
{
uint8_t *data = (uint8_t *) FLASHMEM_ADDRESS_SPACE;
uint32_t dst = FLASH_BANK2_BASE;
uint32_t r = 0, w = 0;
int i;
/* Return if content already matches */
if (memcmp(data, (void *)FLASH_BANK2_BASE, BOOTLOADER_SIZE) == 0)
return;
/* Read the wolfBoot image in RAM */
memcpy(bootloader_copy_mem, data, BOOTLOADER_SIZE);
/* Mass-erase */
hal_flash_unlock();
hal_flash_erase(dst, BOOTLOADER_SIZE);
hal_flash_write(dst, bootloader_copy_mem, BOOTLOADER_SIZE);
hal_flash_lock();
}
#endif
void hal_init(void)
{
#if TZ_SECURE()
hal_tz_sau_init();
hal_gtzc_init();
#endif
clock_pll_on();
#if defined(DUALBANK_SWAP) && defined(__WOLFBOOT)
if ((FLASH_OPTSR_CUR & (FLASH_OPTSR_CUR_SWAP_BANK)) == 0)
fork_bootloader();
#endif
}
void hal_prepare_boot(void)
{
clock_pll_off();
#if TZ_SECURE()
periph_unsecure();
#endif
}

352
hal/stm32h5.h 100644
View File

@ -0,0 +1,352 @@
/* stm32h5.h
*
* Copyright (C) 2024 wolfSSL Inc.
*
* This file is part of wolfBoot.
*
* wolfBoot is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* wolfBoot is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
*/
#ifndef STM32H5_DEF_INCLUDED
#define STM32H5_DEF_INCLUDED
/* Assembly helpers */
#define DMB() __asm__ volatile ("dmb")
#define ISB() __asm__ volatile ("isb")
#define DSB() __asm__ volatile ("dsb")
#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && !defined(NONSECURE_APP))
# define TZ_SECURE() (1)
#else
# define TZ_SECURE() (0)
#endif
/* STM32 H5 register configuration */
/*** RCC ***/
#if TZ_SECURE()
/*Secure */
#define RCC_BASE (0x54020c00) /* RM0481 - Table 3 */
#else
/*Non-Secure */
#define RCC_BASE (0x44020C00) /* RM0481 - Table 3 */
#endif
#define FLASH_SECURE_MMAP_BASE (0x0C000000)
#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00)) /* RM0481 - Table 108 */
#define RCC_CR_PLL3RDY (1 << 29) /* RM0481 - Table 108 */
#define RCC_CR_PLL3ON (1 << 28) /* RM0481 - Table 108 */
#define RCC_CR_PLL2RDY (1 << 27) /* RM0481 - Table 108 */
#define RCC_CR_PLL2ON (1 << 26) /* RM0481 - Table 108 */
#define RCC_CR_PLL1RDY (1 << 25) /* RM0481 - Table 108 */
#define RCC_CR_PLL1ON (1 << 24) /* RM0481 - Table 108 */
#define RCC_CR_HSEEXT (1 << 20) /* RM0481 - Table 108 */
#define RCC_CR_HSECSSON (1 << 19) /* RM0481 - Table 108 */
#define RCC_CR_HSEBYP (1 << 18) /* RM0481 - Table 108 */
#define RCC_CR_HSERDY (1 << 17) /* RM0481 - Table 108 */
#define RCC_CR_HSEON (1 << 16) /* RM0481 - Table 108 */
#define RCC_CR_HSI48RDY (1 << 13) /* RM0481 - Table 108 */
#define RCC_CR_HSI48ON (1 << 12) /* RM0481 - Table 108 */
#define RCC_CR_CSIKERON (1 << 10) /* RM0481 - Table 108 */
#define RCC_CR_CSIRDY (1 << 9) /* RM0481 - Table 108 */
#define RCC_CR_CSION (1 << 8) /* RM0481 - Table 108 */
#define RCC_CR_HSIDIVF (1 << 5) /* RM0481 - Table 108 */
#define RCC_CR_HSIDIV_SHIFT (3) /* RM0481 - Table 108 */
#define RCC_CR_HSIKERON (1 << 2) /* RM0481 - Table 108 */
#define RCC_CR_HSIRDY (1 << 1) /* RM0481 - Table 108 */
#define RCC_CR_HSION (1 << 0) /* RM0481 - Table 108 */
#define RCC_CFGR1 (*(volatile uint32_t *)(RCC_BASE + 0x1C)) /* RM0481 - 11.8.5 */
#define RCC_CFGR2 (*(volatile uint32_t *)(RCC_BASE + 0x20)) /* RM0481 - 11.8.6 */
/* CFGR1 - PLL Source selection */
#define RCC_CFGR1_SW_SHIFT (0x0)
#define RCC_CFGR1_SWS_SHIFT (0x3)
#define RCC_CFGR1_SW_HSI (0x0) /* 00: HSI selected as system clock, default after reset */
#define RCC_CFGR1_SW_CSI (0x1)
#define RCC_CFGR1_SW_HSE (0x2)
#define RCC_CFGR1_SW_PLL1 (0x3)
#define RCC_CFGR1_SW_MASK (0x3)
/* HPRE - PPRE1 - PPRE2 - PPRE3 */
#define RCC_CFGR2_HPRE_SHIFT (0x0)
#define RCC_CFGR2_PPRE1_SHIFT (0x4)
#define RCC_CFGR2_PPRE2_SHIFT (0x8)
#define RCC_CFGR2_PPRE3_SHIFT (0xC)
/* PLL1 Configuration */
#define RCC_PLL1CFGR (*(volatile uint32_t *)(RCC_BASE + 0x28)) /* RM0481 - Table 108 */
#define RCC_PLL1DIVR (*(volatile uint32_t *)(RCC_BASE + 0x34)) /* RM0481 - Table 108 */
#define RCC_PLL1FRACR (*(volatile uint32_t *)(RCC_BASE + 0x38)) /* RM0481 - Table 108 */
#define RCC_PLL1CFGR_PLL1SRC_SHIFT (0x0)
#define RCC_PLL1CFGR_PLL1SRC_HSE (0x3)
#define RCC_PLL1CFGR_PLL1RGE_SHIFT (0x2)
#define RCC_PLL1CFGR_RGE_1_2 (0x0) /* Default at boot: 1-2 MHz */
#define RCC_PLL1CFGR_RGE_2_4 (0x1) /* 2-4 MHz */
#define RCC_PLL1CFGR_RGE_4_8 (0x2) /* 4-8 MHz */
#define RCC_PLL1CFGR_RGE_8_16 (0x3) /* 8-16 MHz */
#define RCC_PLL1CFGR_PLL1PEN (1 << 16)
#define RCC_PLL1CFGR_PLL1QEN (1 << 17)
#define RCC_PLL1CFGR_PLL1REN (1 << 18)
#define RCC_PLL1CFGR_PLL1FRACEN (1 << 4)
#define RCC_PLL1CFGR_PLL1VCOSEL (1 << 5)
#define RCC_PLL1CFGR_PLL1M_SHIFT (0x8)
#define RCC_PLL1CFGR_PLL1PEN (1 << 16)
#define RCC_PLL1CFGR_PLL1QEN (1 << 17)
#define RCC_PLL1CFGR_PLL1REN (1 << 18)
#define RCC_PLL1DIVR_DIVN_SHIFT (0)
#define RCC_PLL1DIVR_DIVP_SHIFT (9)
#define RCC_PLL1DIVR_DIVQ_SHIFT (16)
#define RCC_PLL1DIVR_DIVR_SHIFT (24)
#define RCC_PLL1FRACR_FRACN_SHIFT (3)
#define RCC_APB_PRESCALER_DIV_NONE 0x0 /* 0xx: HCLK not divided */
#define RCC_APB_PRESCALER_DIV_2 0x4 /* 100: HCLK divided by 2 */
#define RCC_APB_PRESCALER_DIV_4 0x5 /* 101: HCLK divided by 4 */
#define RCC_APB_PRESCALER_DIV_8 0x6 /* 110: HCLK divided by 8 */
#define RCC_APB_PRESCALER_DIV_16 0x7 /* 111: HCLK divided by 16 */
#define RCC_AHB_PRESCALER_DIV_NONE 0x0 /* 0xxx: SYSCLK not divided */
#define RCC_AHB_PRESCALER_DIV_2 0x8 /* 1000: SYSCLK divided by 2 */
#define RCC_AHB_PRESCALER_DIV_4 0x9 /* 1001: SYSCLK divided by 4 */
#define RCC_AHB_PRESCALER_DIV_8 0xA /* 1010: SYSCLK divided by 8 */
#define RCC_AHB_PRESCALER_DIV_16 0xB /* 1011: SYSCLK divided by 16 */
#define RCC_AHB_PRESCALER_DIV_64 0xC /* 1100: SYSCLK divided by 64 */
#define RCC_AHB_PRESCALER_DIV_128 0xD /* 1101: SYSCLK divided by 128 */
#define RCC_AHB_PRESCALER_DIV_256 0xE /* 1110: SYSCLK divided by 256 */
#define RCC_AHB_PRESCALER_DIV_512 0xF /* 1111: SYSCLK divided by 512 */
#define RCC_CFGR_SW_MSI 0x0
#define RCC_CFGR_SW_HSI16 0x1
#define RCC_CFGR_SW_HSE 0x2
#define RCC_CFGR_SW_PLL 0x3
#define RCC_PLLCFGR (*(volatile uint32_t *)(RCC_BASE + 0x0C)) //RM0481 - Table 77
#define RCC_PLLCFGR_PLLP_SHIFT (27)
#define RCC_PLLCFGR_PLLR_SHIFT (25)
#define RCC_PLLCFGR_PLLREN (1 << 24)
#define RCC_PLLCFGR_PLLQ_SHIFT (21)
#define RCC_PLLCFGR_PLLQEN (1 << 20)
#define RCC_PLLCFGR_PLLN_SHIFT (8)
#define RCC_PLLCFGR_PLLM_SHIFT (4)
#define RCC_PLLCFGR_QR_DIV_2 0x0
#define RCC_PLLCFGR_QR_DIV_4 0x1
#define RCC_PLLCFGR_QR_DIV_6 0x2
#define RCC_PLLCFGR_QR_DIV_8 0x3
#define RCC_PLLCFGR_P_DIV_7 0x0
#define RCC_PLLCFGR_P_DIV_17 0x1
#define RCC_PLLCKSELR_PLLSRC_NONE 0x0
#define RCC_PLLCKSELR_PLLSRC_MSI 0x1
#define RCC_PLLCKSELR_PLLSRC_HSI16 0x2
#define RCC_PLLCKSELR_PLLSRC_HSE 0x3
#define RCC_CCIPR1 (*(volatile uint32_t *)(RCC_BASE + 0x88))
#define RCC_CCIPR1_LPUART1SEL_SHIFT (10)
#define RCC_CCIPR1_LPUART1SEL_MASK (0x3)
#define RCC_CRRCR (*(volatile uint32_t *)(RCC_BASE + 0x98))
#define RCC_CRRCR_HSI48ON (1 << 0)
#define RCC_CRRCR_HSI48RDY (1 << 1)
/*** PWR ***/
/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
#if TZ_SECURE()
/*Secure */
#define PWR_BASE (0x50020800) //RM0481 - Table 3
#else
/*Non-Secure */
#define PWR_BASE (0x40020800) //RM0481 - Table 3
#endif
#define PWR_VOSCR (*(volatile uint32_t *)(PWR_BASE + 0x10))
#define PWR_VOSSR (*(volatile uint32_t *)(PWR_BASE + 0x14))
#define PWR_VOS_SCALE_0 (0x3 << 4) //RM0481 - 10.11.3
#define PWR_VOS_SCALE_3 (0x0 << 4) //RM0481 - 10.11.3 - Default on power up
#define PWR_VOS_MASK (0x3 << 4) //RM0481 - 10.11.3
#define PWR_VOSRDY (1 << 3) //RM0481 - 10.11.4 - Voltage scaling ready
#define PWR_CR2 (*(volatile uint32_t *)(PWR_BASE + 0x04))
#define PWR_CR2_IOSV (1 << 9)
#define PWR_CR3 (*(volatile uint32_t *)(PWR_BASE + 0x08))
#define PWR_CR3_UCPD_DBDIS (1 << 14)
#define PWR_CR4 (*(volatile uint32_t *)(PWR_BASE + 0x0C))
#define PWR_SR1 (*(volatile uint32_t *)(PWR_BASE + 0x10))
#define PWR_SR2 (*(volatile uint32_t *)(PWR_BASE + 0x14))
#define PWR_SR2_VOSF (1 << 10)
#if TZ_SECURE()
/*Secure*/
#define FLASH_BASE (0x50022000) //RM0481 - Table 75
#define FLASH_KEYR (*(volatile uint32_t *)(FLASH_BASE + 0x08))
#define FLASH_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x0C))
#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x24))
#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x2C))
#define FLASH_SECBB1 ((volatile uint32_t *)(FLASH_BASE + 0x0A0)) /* Array */
#define FLASH_SECBB2 ((volatile uint32_t *)(FLASH_BASE + 0x1A0)) /* Array */
#define FLASH_SECBB_NREGS 4 /* Array length for the two above */
#define FLASH_NS_BASE (0x40022000) //RM0481 - Table 3
#define FLASH_NS_KEYR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x08))
#define FLASH_NS_OPTKEYR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x10))
#define FLASH_NS_SR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x20))
#define FLASH_NS_CR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x28))
#define TZSC_PRIVCFGR2 *((uint32_t *)(0x50036424))
#define TZSC_PRIVCFG2_LPUARTPRIV (1 << 25) /* LPUART1 */
#else
/* Non-Secure only */
#define FLASH_BASE (0x40022000) //RM0481 - Table 3
#define FLASH_KEYR (*(volatile uint32_t *)(FLASH_BASE + 0x04))
#define FLASH_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x10))
#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x20))
#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x28))
#endif
/* Both secure + non secure */
#define FLASH_OPTCR (*(volatile uint32_t *)(FLASH_BASE + 0x1C))
#define FLASH_OPSR (*(volatile uint32_t *)(FLASH_BASE + 0x18))
#define FLASH_OPSR_DATA_OP (1 << 21)
#define FLASH_OPSR_BK_OP (1 << 22)
#define FLASH_OPSR_SYSF_OP (1 << 23)
#define FLASH_OPSR_OTP_OP (1 << 24)
#define FLASH_OPSR_CODE_MASK (0x7 << 29)
#define FLASH_OPSR_CODE_WRITE (0x1 << 29)
#define FLASH_OPSR_CODE_OBK_ALT_ERASE (0x2 << 29)
#define FLASH_OPSR_CODE_SEC_ERASE (0x3 << 29)
#define FLASH_OPSR_CODE_BANK_ERASE (0x4 << 29)
#define FLASH_OPSR_CODE_MASS_ERASE (0x5 << 29)
#define FLASH_OPSR_CODE_OPT_CHANGE (0x6 << 29)
#define FLASH_OPSR_CODE_OBK_SWAP (0x7 << 29)
#if defined(DUALBANK_SWAP) && defined (__WOLFBOOT)
/* Mapping FLASH_SECCR for bank swapping */
#define FLASH_OPTSR_CUR (*(volatile uint32_t *)(FLASH_BASE + 0x50))
#define FLASH_SECCR (*(volatile uint32_t *)(FLASH_BASE + 0x2C))
#define FLASH_SECCR_BKSEL (1 << 31)
#define FLASH_OPTSR_CUR_SWAP_BANK (1 << 31)
#endif
/* Register values (for both secure and non secure registers)
* RM0481 Table 75 */
#define FLASH_SR_BSY (1 << 0)
#define FLASH_SR_WBNE (1 << 1)
#define FLASH_SR_DBNE (1 << 3)
#define FLASH_SR_EOP (1 << 16)
#define FLASH_SR_WRPERR (1 << 17)
#define FLASH_SR_PGSERR (1 << 18)
#define FLASH_SR_STRBERR (1 << 19)
#define FLASH_SR_INCERR (1 << 20)
#define FLASH_SR_OPTERR (1 << 21)
#define FLASH_SR_OPTWERR (1 << 22)
#define FLASH_CR_LOCK (1 << 0)
#define FLASH_CR_PG (1 << 1)
#define FLASH_CR_SER (1 << 2)
#define FLASH_CR_BER (1 << 3)
#define FLASH_CR_FW (1 << 4)
#define FLASH_CR_STRT (1 << 5)
#define FLASH_CR_PNB_SHIFT 6
#define FLASH_CR_PNB_MASK 0x7F
#define FLASH_CR_MER (1 << 15)
#define FLASH_CR_EOPIE (1 << 16)
#define FLASH_CR_WRPERRIE (1 << 17)
#define FLASH_CR_PGSERRIE (1 << 18)
#define FLASH_CR_STRBERRIE (1 << 19)
#define FLASH_CR_INCERRIE (1 << 20)
#define FLASH_CR_OBKIE (1 << 21)
#define FLASH_CR_OBKWIE (1 << 22)
#define FLASH_CR_OPTCHANGEERRIE (1 << 23)
#define FLASH_CR_BKSEL (1 << 31)
#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
#define FLASH_ACR_LATENCY_MASK (0x0F)
#define FLASH_OPTCR (*(volatile uint32_t *)(FLASH_BASE + 0x1C))
#define FLASH_OPTCR_OPTSTRT (1 << 1)
#define FLASH_OPTCR_OPTLOCK (1 << 0)
#define FLASH_OPTCR_SWAP_BANK (1 << 31)
#define FLASHMEM_ADDRESS_SPACE (0x08000000)
#define FLASH_PAGE_SIZE (0x2000) /* 8KB */
#define FLASH_BANK2_BASE (0x08100000) /*!< Base address of Flash Bank2 */
#define BOOTLOADER_SIZE (0x8000)
#define FLASH_TOP (0x080FFFFF) /*!< FLASH end address (sector 127) */
#define FLASH_KEY1 (0x45670123U)
#define FLASH_KEY2 (0xCDEF89ABU)
#define FLASH_OPTKEY1 (0x08192A3BU)
#define FLASH_OPTKEY2 (0x4C5D6E7FU)
/* GPIO*/
#define GPIOA_BASE 0x52020000
#define GPIOB_BASE 0x52020400
#define GPIOC_BASE 0x52020800
#define GPIOD_BASE 0x52020C00
#define GPIOG_BASE 0x52021800
/* RCC AHB2 Clock Enable Register */
#define RCC_AHB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C ))
#define GPIOA_AHB2_CLOCK_ER (1 << 0)
#define GPIOB_AHB2_CLOCK_ER (1 << 1)
#define GPIOC_AHB2_CLOCK_ER (1 << 2)
#define GPIOD_AHB2_CLOCK_ER (1 << 3)
#define GPIOG_AHB2_CLOCK_ER (1 << 6)
#define TRNG_AHB2_CLOCK_ER (1 << 18)
#define RCC_APB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0xA4))
#define UART1_APB2_CLOCK_ER_VAL (1 << 14)
#define UART1_PIN_AF 8
#define UART1_RX_PIN 8
#define UART1_TX_PIN 7
#define GPIO_SECCFGR(base) (*(volatile uint32_t *)(base + 0x30))
#ifdef STM32_DISCOVERY
#define LED_AHB2_ENABLE (GPIOD_AHB2_CLOCK_ER | GPIOG_AHB2_CLOCK_ER)
#define LED_BOOT_PIN (12) /* PG12 - Discovery - Green Led */
#define LED_USR_PIN (3) /* PD3 - Discovery - Red Led */
#else
#define LED_AHB2_ENABLE (GPIOA_AHB2_CLOCK_ER | GPIOB_AHB2_CLOCK_ER | \
GPIOC_AHB2_CLOCK_ER)
#define LED_BOOT_PIN (9) /* PA9 - Nucleo board - Red Led */
#define LED_USR_PIN (7) /* PC7 - Nucleo board - Green Led */
#define LED_EXTRA_PIN (7) /* PB7 - Nucleo board - Blue Led */
#endif
#endif /* STM32H5_DEF_INCLUDED */

59
hal/stm32h5.ld 100644
View File

@ -0,0 +1,59 @@
MEMORY
{
FLASH (rx) : ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @BOOTLOADER_PARTITION_SIZE@
RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00017FFF
FLASH_NSC(rx): ORIGIN = @WOLFBOOT_ORIGIN@ + 0x20000, LENGTH = 0x20000
}
SECTIONS
{
.text :
{
_start_text = .;
KEEP(*(.isr_vector))
*(.text*)
*(.rodata*)
. = ALIGN(8);
_end_text = .;
} > FLASH
.edidx :
{
. = ALIGN(4);
*(.ARM.exidx*)
} > FLASH
.gnu.sgstubs :
{
. = ALIGN(4);
*(.gnu.sgstubs*) /* Secure Gateway stubs */
. = ALIGN(4);
} >FLASH_NSC
_stored_data = .;
.data : AT (_stored_data)
{
_start_data = .;
KEEP(*(.data*))
. = ALIGN(8);
KEEP(*(.ramcode))
. = ALIGN(8);
_end_data = .;
} > RAM
.bss (NOLOAD) :
{
_start_bss = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(8);
_end_bss = .;
__bss_end__ = .;
_end = .;
} > RAM
. = ALIGN(8);
}
END_STACK = ORIGIN(RAM) + LENGTH(RAM);

403
hal/stm32l5_ns.c
View File

@ -1,403 +0,0 @@
/* stm32l5.c
*
* Copyright (C) 2021 wolfSSL Inc.
*
* This file is part of wolfBoot.
*
* wolfBoot is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* wolfBoot is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
*/
#include <stdint.h>
#include <image.h>
/* Assembly helpers */
#define DMB() __asm__ volatile ("dmb")
#define ISB() __asm__ volatile ("isb")
#define DSB() __asm__ volatile ("dsb")
/* STM32 L5 register configuration */
/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
/*Non-Secure */
#define RCC_BASE (0x40021000) //RM0438 - Table 4
#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00)) //RM0438 - Table 77
#define RCC_CR_PLLRDY (1 << 25) //RM0438 - 9.8.1
#define RCC_CR_PLLON (1 << 24) //RM0438 - 9.8.1
#define RCC_CR_HSEBYP (1 << 18) //RM0438 - 9.8.1
#define RCC_CR_HSERDY (1 << 17) //RM0438 - 9.8.1
#define RCC_CR_HSEON (1 << 16) //RM0438 - 9.8.1
#define RCC_CR_HSIRDY (1 << 10) //RM0438 - 9.8.1
#define RCC_CR_HSION (1 << 8) //RM0438 - 9.8.1
#define RCC_CR_MSIRANGE_SHIFT (4) //RM0438 - 9.8.1
#define RCC_CR_MSIRANGE_11 (11)
#define RCC_CR_MSIRGSEL (1 << 3) //RM0438 - 9.8.1
#define RCC_CR_MSIPLLEN (1 << 2) //RM0438 - 9.8.1
#define RCC_CR_MSIRDY (1 << 1) //RM0438 - 9.8.1
#define RCC_CR_MSION (1 << 0) //RM0438 - 9.8.1
#define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08)) //RM0438 - Table 77
/*** APB1&2 PRESCALER ***/
#define RCC_APB_PRESCALER_DIV_NONE 0x0 // 0xx: HCLK not divided
#define RCC_APB_PRESCALER_DIV_2 0x4 // 100: HCLK divided by 2
#define RCC_APB_PRESCALER_DIV_4 0x5 // 101: HCLK divided by 4
#define RCC_APB_PRESCALER_DIV_8 0x6 // 110: HCLK divided by 8
#define RCC_APB_PRESCALER_DIV_16 0x7 // 111: HCLK divided by 16
/*** AHB PRESCALER ***/
#define RCC_AHB_PRESCALER_DIV_NONE 0x0 // 0xxx: SYSCLK not divided
#define RCC_AHB_PRESCALER_DIV_2 0x8 // 1000: SYSCLK divided by 2
#define RCC_AHB_PRESCALER_DIV_4 0x9 // 1001: SYSCLK divided by 4
#define RCC_AHB_PRESCALER_DIV_8 0xA // 1010: SYSCLK divided by 8
#define RCC_AHB_PRESCALER_DIV_16 0xB // 1011: SYSCLK divided by 16
#define RCC_AHB_PRESCALER_DIV_64 0xC // 1100: SYSCLK divided by 64
#define RCC_AHB_PRESCALER_DIV_128 0xD // 1101: SYSCLK divided by 128
#define RCC_AHB_PRESCALER_DIV_256 0xE // 1110: SYSCLK divided by 256
#define RCC_AHB_PRESCALER_DIV_512 0xF // 1111: SYSCLK divided by 512
#define RCC_CFGR_HPRE_SHIFT (0x04)
#define RCC_CFGR_PPRE2_SHIFT (0x0B)
#define RCC_CFGR_PPRE1_SHIFT (0x08)
#define RCC_CFGR_SW_MSI 0x0
#define RCC_CFGR_SW_HSI16 0x1
#define RCC_CFGR_SW_HSE 0x2
#define RCC_CFGR_SW_PLL 0x3
#define RCC_PLLCFGR (*(volatile uint32_t *)(RCC_BASE + 0x0C)) //RM0438 - Table 77
#define RCC_PLLCFGR_PLLP_SHIFT (27)
#define RCC_PLLCFGR_PLLR_SHIFT (25)
#define RCC_PLLCFGR_PLLREN (1 << 24)
#define RCC_PLLCFGR_PLLQ_SHIFT (21)
#define RCC_PLLCFGR_PLLQEN (1 << 20)
#define RCC_PLLCFGR_PLLN_SHIFT (8)
#define RCC_PLLCFGR_PLLM_SHIFT (4)
#define RCC_PLLCFGR_QR_DIV_2 0x0
#define RCC_PLLCFGR_QR_DIV_4 0x1
#define RCC_PLLCFGR_QR_DIV_6 0x2
#define RCC_PLLCFGR_QR_DIV_8 0x3
#define RCC_PLLCFGR_P_DIV_7 0x0
#define RCC_PLLCFGR_P_DIV_17 0x1
#define RCC_PLLCKSELR_PLLSRC_NONE 0x0
#define RCC_PLLCKSELR_PLLSRC_MSI 0x1
#define RCC_PLLCKSELR_PLLSRC_HSI16 0x2
#define RCC_PLLCKSELR_PLLSRC_HSE 0x3
#define RCC_APB1ENR (*(volatile uint32_t *)(RCC_BASE + 0x58))
#define RCC_APB1ENR_PWREN (1 << 28)
#define RCC_APB2ENR (*(volatile uint32_t *)(RCC_BASE + 0x60))
#define RCC_APB2ENR_SYSCFGEN (1 << 0)
/*** PWR ***/
/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
/*Non-Secure */
#define PWR_BASE (0x40007000) //RM0438 - Table 4
#define PWR_CR1 (*(volatile uint32_t *)(PWR_BASE + 0x00))
#define PWR_CR1_VOS_SHIFT (9)
#define PWR_CR1_VOS_0 (0x0)
#define PWR_CR1_VOS_1 (0x1)
#define PWR_CR1_VOS_2 (0x2)
#define PWR_CR2 (*(volatile uint32_t *)(PWR_BASE + 0x04))
#define PWR_CR2_IOSV (1 << 9)
#define PWR_CR3 (*(volatile uint32_t *)(PWR_BASE + 0x08))
#define PWR_CR3_UCPD_DBDIS (1 << 14)
#define PWR_CR4 (*(volatile uint32_t *)(PWR_BASE + 0x0C))
#define PWR_SR1 (*(volatile uint32_t *)(PWR_BASE + 0x10))
#define PWR_SR2 (*(volatile uint32_t *)(PWR_BASE + 0x14))
#define PWR_SR2_VOSF (1 << 10)
#define SYSCFG_BASE (0x50010000) //RM0438 - Table 4
/*** FLASH ***/
#define SYSCFG_APB2_CLOCK_ER_VAL (1 << 0) //RM0438 - RCC_APB2ENR - SYSCFGEN
/*Non-Secure*/
#define FLASH_BASE (0x40022000) //RM0438 - Table 4
#define FLASH_KEYR (*(volatile uint32_t *)(FLASH_BASE + 0x08))
#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x20))
#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x28))
/* Register values */
#define FLASH_SR_EOP (1 << 0)
#define FLASH_SR_OPERR (1 << 1)
#define FLASH_SR_PROGERR (1 << 3)
#define FLASH_SR_WRPERR (1 << 4)
#define FLASH_SR_PGAERR (1 << 5)
#define FLASH_SR_SIZERR (1 << 6)
#define FLASH_SR_PGSERR (1 << 7)
#define FLASH_SR_OPTWERR (1 << 13)
#define FLASH_SR_BSY (1 << 16)
#define FLASH_CR_PG (1 << 0)
#define FLASH_CR_PER (1 << 1)
#define FLASH_CR_MER1 (1 << 2)
#define FLASH_CR_PNB_SHIFT 3
#define FLASH_CR_PNB_MASK 0x7F
#define FLASH_CR_BKER (1 << 11)
#define FLASH_CR_MER2 (1 << 15)
#define FLASH_CR_STRT (1 << 16)
#define FLASH_CR_OPTSTRT (1 << 17)
#define FLASH_CR_EOPIE (1 << 24)
#define FLASH_CR_ERRIE (1 << 25)
#define FLASH_CR_OBL_LAUNCH (1 << 27)
#define FLASH_CR_OPTLOCK (1 << 30)
#define FLASH_CR_LOCK (1UL << 31)
#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
#define FLASH_ACR_LATENCY_MASK (0x0F)
#define FLASHMEM_ADDRESS_SPACE (0x08000000)
#define FLASH_PAGE_SIZE (0x800) /* 2KB */
#define FLASH_BANK2_BASE (0x08040000) /*!< Base address of Flash Bank2 */
#define FLASH_TOP (0x0807FFFF) /*!< FLASH end address */
#define FLASH_KEY1 (0x45670123)
#define FLASH_KEY2 (0xCDEF89AB)
static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
{
uint32_t reg = FLASH_ACR;
if ((reg & FLASH_ACR_LATENCY_MASK) != waitstates)
FLASH_ACR = (reg & ~FLASH_ACR_LATENCY_MASK) | waitstates ;
}
static RAMFUNCTION void flash_wait_complete(uint8_t bank)
{
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
}
static void RAMFUNCTION flash_clear_errors(uint8_t bank)
{
FLASH_SR |= ( FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR |FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR | FLASH_SR_OPTWERR ) ;
}
int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
{
int i = 0;
uint32_t *src, *dst;
flash_clear_errors(0);
src = (uint32_t *)data;
dst = (uint32_t *)(address + FLASHMEM_ADDRESS_SPACE);
while (i < len) {
FLASH_CR |= FLASH_CR_PG;
dst[i >> 2] = src[i >> 2];
dst[(i >> 2) + 1] = src[(i >> 2) + 1];
flash_wait_complete(0);
FLASH_CR &= ~FLASH_CR_PG;
i+=8;
}
return 0;
}
void RAMFUNCTION hal_flash_unlock(void)
{
flash_wait_complete(0);
if ((FLASH_CR & FLASH_CR_LOCK) != 0) {
FLASH_KEYR = FLASH_KEY1;
DMB();
FLASH_KEYR = FLASH_KEY2;
DMB();
while ((FLASH_CR & FLASH_CR_LOCK) != 0)
;
}
}
void RAMFUNCTION hal_flash_lock(void)
{
flash_wait_complete(0);
if ((FLASH_CR & FLASH_CR_LOCK) == 0)
FLASH_CR |= FLASH_CR_LOCK;
}
int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
{
uint32_t end_address;
uint32_t p;
flash_clear_errors(0);
if (len == 0)
return -1;
end_address = address + len - 1;
for (p = address; p < end_address; p += FLASH_PAGE_SIZE) {
// considering DBANK = 1
if (p < (FLASH_BANK2_BASE -FLASHMEM_ADDRESS_SPACE) )
{
FLASH_CR &= ~FLASH_CR_BKER;
}
if(p>=(FLASH_BANK2_BASE -FLASHMEM_ADDRESS_SPACE) && (p <= (FLASH_TOP -FLASHMEM_ADDRESS_SPACE) ))
{
FLASH_CR |= FLASH_CR_BKER;
}
uint32_t reg = FLASH_CR & (~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT)| FLASH_CR_PER));
FLASH_CR = reg | (((p >> 11) << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER );
DMB();
FLASH_CR |= FLASH_CR_STRT;
flash_wait_complete(0);
}
/* If the erase operation is completed, disable the associated bits */
FLASH_CR &= ~FLASH_CR_PER ;
return 0;
}
static void clock_pll_off(void)
{
uint32_t reg32;
/* Select MSI as SYSCLK source. */
reg32 = RCC_CFGR;
reg32 &= ~((1 << 1) | (1 << 0));
RCC_CFGR = (reg32 | RCC_CFGR_SW_MSI);
DMB();
/* Wait for MSI clock to be selected. */
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_MSI) {};
/* Turn off PLL */
RCC_CR &= ~RCC_CR_PLLON;
DMB();
}
/*This implementation will setup MSI 48 MHz as PLL Source Mux, PLLCLK as System Clock Source*/
static void clock_pll_on(int powersave)
{
uint32_t reg32;
uint32_t plln, pllm, pllq, pllp, pllr, hpre, apb1pre, apb2pre , flash_waitstates;
RCC_APB2ENR |= RCC_APB2ENR_SYSCFGEN;
RCC_APB1ENR |= RCC_APB1ENR_PWREN;
PWR_CR3 |= PWR_CR3_UCPD_DBDIS;
PWR_CR1 &= ~((1 << 10) | (1 << 9));
PWR_CR1 |= (PWR_CR1_VOS_0 << PWR_CR1_VOS_SHIFT);
/* Delay after setting the voltage scaling */
reg32 = PWR_CR1;
while ((PWR_SR2 & PWR_SR2_VOSF) != 0) {};
while ((RCC_CR & RCC_CR_MSIRDY) == 0) {};
flash_waitstates = 2;
flash_set_waitstates(flash_waitstates);
RCC_CR |= RCC_CR_MSIRGSEL;
reg32 = RCC_CR;
reg32 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4));
reg32 |= (RCC_CR_MSIRANGE_11 << RCC_CR_MSIRANGE_SHIFT);
RCC_CR = reg32;
reg32 = RCC_CR;
DMB();
/* Select clock parameters (CPU Speed = 110 MHz) */
pllm = 12;
plln = 55;
pllp = 7;
pllq = RCC_PLLCFGR_QR_DIV_2;
pllr = RCC_PLLCFGR_QR_DIV_2;
hpre = RCC_AHB_PRESCALER_DIV_NONE;
apb1pre = RCC_APB_PRESCALER_DIV_NONE;
apb2pre = RCC_APB_PRESCALER_DIV_NONE;
flash_waitstates = 5;
RCC_CR &= ~RCC_CR_PLLON;
while ((RCC_CR & RCC_CR_PLLRDY) != 0) {};
/*PLL Clock source selection*/
reg32 = RCC_PLLCFGR ;
reg32 |= RCC_PLLCKSELR_PLLSRC_MSI;
reg32 |= ((pllm-1) << RCC_PLLCFGR_PLLM_SHIFT);
reg32 |= ((plln) << RCC_PLLCFGR_PLLN_SHIFT);
reg32 |= ((pllp) << RCC_PLLCFGR_PLLP_SHIFT);
reg32 |= ((pllq) << RCC_PLLCFGR_PLLQ_SHIFT);
reg32 |= ((pllr) << RCC_PLLCFGR_PLLR_SHIFT);
RCC_PLLCFGR = reg32;
DMB();
RCC_CR |= RCC_CR_PLLON;
while ((RCC_CR & RCC_CR_PLLRDY) == 0) {};
RCC_PLLCFGR |= RCC_PLLCFGR_PLLREN;
flash_set_waitstates(flash_waitstates);
/*step down HPRE before going to >80MHz*/
reg32 = RCC_CFGR ;
reg32 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4));
reg32 |= ((RCC_AHB_PRESCALER_DIV_2) << RCC_CFGR_HPRE_SHIFT) ;
RCC_CFGR = reg32;
DMB();
/* Select PLL as SYSCLK source. */
reg32 = RCC_CFGR;
reg32 &= ~((1 << 1) | (1 << 0));
RCC_CFGR = (reg32 | RCC_CFGR_SW_PLL);
DMB();
/* Wait for PLL clock to be selected. */
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_PLL) {};
/*step-up HPRE to go > 80MHz*/
reg32 = RCC_CFGR ;
reg32 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4));
reg32 |= ((hpre) << RCC_CFGR_HPRE_SHIFT) ;
RCC_CFGR = reg32;
DMB();
/*PRE1 and PRE2 conf*/
reg32 = RCC_CFGR ;
reg32 &= ~((1 << 10) | (1 << 9) | (1 << 8));
reg32 |= ((apb1pre) << RCC_CFGR_PPRE1_SHIFT) ;
reg32 &= ~((1 << 13) | (1 << 12) | (1 << 11));
reg32 |= ((apb2pre) << RCC_CFGR_PPRE2_SHIFT) ;
RCC_CFGR = reg32;
DMB();
}
void hal_init(void)
{
clock_pll_on(0);
}
void hal_prepare_boot(void)
{
clock_pll_off();
}

18
hal/stm32u5.c
View File

@ -37,7 +37,7 @@ static RAMFUNCTION void flash_wait_complete(uint8_t bank)
{
while ((FLASH_NS_SR & (FLASH_SR_BSY | FLASH_SR_WDW)) != 0)
;
#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
#if (TZ_SECURE())
while ((FLASH_SR & (FLASH_SR_BSY | FLASH_SR_WDW)) != 0)
;
#endif
@ -49,11 +49,11 @@ static void RAMFUNCTION flash_clear_errors(uint8_t bank)
FLASH_NS_SR |= (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR |
FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR
#if !(defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
#if !(TZ_SECURE())
| FLASH_SR_OPTWERR
#endif
);
#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
#if (TZ_SECURE())
FLASH_SR |= (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR |
FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR |
FLASH_SR_OPTWERR);
@ -72,7 +72,7 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
src = (uint32_t*)data;
dst = (uint32_t*)address;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if (TZ_SECURE())
if ((((FLASH_OPTR & FLASH_OPTR_DBANK) == 0) && (address <= FLASH_TOP)) || (address < FLASH_BANK2_BASE)) {
cr = &FLASH_CR;
sr = &FLASH_SR;
@ -118,7 +118,7 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
void RAMFUNCTION hal_flash_unlock(void)
{
flash_wait_complete(0);
#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
#if (TZ_SECURE())
if ((FLASH_CR & FLASH_CR_LOCK) != 0) {
FLASH_KEYR = FLASH_KEY1;
DMB();
@ -141,7 +141,7 @@ void RAMFUNCTION hal_flash_unlock(void)
void RAMFUNCTION hal_flash_lock(void)
{
flash_wait_complete(0);
#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
#if (TZ_SECURE())
if ((FLASH_CR & FLASH_CR_LOCK) == 0)
FLASH_CR |= FLASH_CR_LOCK;
#endif
@ -194,7 +194,7 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
cr = &FLASH_NS_CR;
if ((((FLASH_OPTR & FLASH_OPTR_DBANK) == 0) && (p <= FLASH_TOP)) || (p < FLASH_BANK2_BASE)) {
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if (TZ_SECURE())
cr = &FLASH_CR;
#endif
base = FLASHMEM_ADDRESS_SPACE;
@ -512,7 +512,7 @@ void hal_init(void)
fork_bootloader();
#endif
clock_pll_on(0);
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if TZ_SECURE()
hal_tz_sau_init();
hal_gtzc_init();
#endif
@ -522,7 +522,7 @@ void hal_prepare_boot(void)
{
clock_pll_off();
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if TZ_SECURE()
led_unsecure();
#endif
}

12
hal/stm32u5.h
View File

@ -24,10 +24,16 @@
#define ISB() __asm__ volatile ("isb")
#define DSB() __asm__ volatile ("dsb")
#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && !defined(NONSECURE_APP))
# define TZ_SECURE() (1)
#else
# define TZ_SECURE() (0)
#endif
/* STM32 U5 register configuration */
/*** RCC ***/
/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if (TZ_SECURE())
/*Secure */
#define RCC_BASE (0x56020C00) /* RM0456 - Table 4 */
#else
@ -130,7 +136,7 @@
/*** PWR ***/
/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if (TZ_SECURE())
/*Secure */
#define PWR_BASE (0x56020800) /* RM0456 - Table 4 */
#else
@ -158,7 +164,7 @@
/*** FLASH ***/
#define SYSCFG_APB2_CLOCK_ER_VAL (1 << 0) /* <<RM0438>> - RCC_APB2ENR - SYSCFGEN */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if (TZ_SECURE())
/*Secure*/
#define FLASH_BASE (0x50022000) /* RM0456 - Table 4 */
#define FLASH_KEYR (*(volatile uint32_t *)(FLASH_BASE + 0x0C))

560
hal/stm32u5_ns.c
View File

@ -1,560 +0,0 @@
/* stm32u5_ns.c
*
* Copyright (C) 2021 wolfSSL Inc.
*
* This file is part of wolfBoot.
*
* wolfBoot is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* wolfBoot is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
*/
#include <stdint.h>
#include <image.h>
#include <string.h>
#include "stm32u5_partition.h"
/* Assembly helpers */
#define DMB() __asm__ volatile ("dmb")
#define ISB() __asm__ volatile ("isb")
#define DSB() __asm__ volatile ("dsb")
/* STM32 U5 register configuration */
/*** RCC ***/
/*!< Memory & Instance aliases and base addresses for Non-Secure peripherals */
/*Non-Secure */
#define RCC_BASE (0x46020C00) /* RM0456 - Table 4 */
#define FLASH_SECURE_MMAP_BASE (0x0C000000)
#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00)) /* RM0456 - Table 108 */
#define RCC_CR_PLL3RDY (1UL << 29)
#define RCC_CR_PLL3ON (1UL << 28)
#define RCC_CR_PLL2RDY (1UL << 27)
#define RCC_CR_PLL2ON (1UL << 26)
#define RCC_CR_PLL1RDY (1UL << 25)
#define RCC_CR_PLL1ON (1UL << 24)
#define RCC_CR_CSSON (1UL << 19)
#define RCC_CR_HSEBYP (1UL << 18)
#define RCC_CR_HSERDY (1UL << 17)
#define RCC_CR_HSEON (1UL << 16)
#define RCC_CR_HSIRDY (1UL << 10)
#define RCC_CR_HSION (1UL << 8)
#define RCC_CR_MSIPLLEN (1UL << 3)
#define RCC_CR_MSIRDY (1UL << 2)
#define RCC_CR_MSISON (1UL << 0)
#define RCC_CFGR1 (*(volatile uint32_t *)(RCC_BASE + 0x1C)) /* RM0456 - Table 108 */
#define RCC_CFGR1_SWS (1UL << 2)
/*** APB1&2 PRESCALER ***/
#define RCC_APB_PRESCALER_DIV_NONE 0x0 /* 0xx: HCLK not divided */
/*** AHB PRESCALER ***/
#define RCC_AHB_PRESCALER_DIV_NONE 0x0 /* 0xxx: SYSCLK not divided */
#define RCC_CFGR_SW_MSI 0x0
#define RCC_CFGR_SW_HSI16 0x1
#define RCC_CFGR_SW_HSE 0x2
#define RCC_CFGR_SW_PLL 0x3
#define RCC_CFGR2 (*(volatile uint32_t *)(RCC_BASE + 0x20)) /* RM0456 - Table 108 */
#define RCC_CFGR2_HPRE_SHIFT (0x00)
#define RCC_CFGR2_PPRE2_SHIFT (0x08)
#define RCC_CFGR2_PPRE1_SHIFT (0x04)
#define RCC_CFGR3 (*(volatile uint32_t *)(RCC_BASE + 0x24)) /* RM0456 - Table 108 */
#define RCC_CFGR3_PPRE3_SHIFT (0x04)
#define RCC_PLL1CFGR (*(volatile uint32_t *)(RCC_BASE + 0x28)) /* RM0456 - Table 108 */
#define RCC_PLL1CFGR_PLL1REN (1UL << 18)
#define RCC_PLL1CFGR_PLL1QEN (1UL << 17)
#define RCC_PLL1CFGR_PLL1PEN (1UL << 16)
#define RCC_PLL1CFGR_PLL1FRACEN (1UL << 4)
#define RCC_PLL1CFGR_PLL1RGE_SHIFT (2)
#define RCC_PLL1VCIRANGE_1 0x03
#define RCC_PLL1CFGR_PLLM_SHIFT (8)
#define RCC_PLL1CFGR_PLL1MBOOST_SHIFT (12)
#define RCC_PLL1CFGR_PLL1MBOOST_DIV4 0x02UL
#define RCC_PLLCKSELR_PLLSRC_NONE 0x0UL
#define RCC_PLLCKSELR_PLLSRC_MSI 0x1UL
#define RCC_PLLCKSELR_PLLSRC_HSI16 0x2UL
#define RCC_PLLCKSELR_PLLSRC_HSE 0x3UL
#define RCC_PLL1DIVR (*(volatile uint32_t *)(RCC_BASE + 0x34)) /* RM0456 - Table 108 */
#define RCC_PLL1DIVR_PLLN_SHIFT (0)
#define RCC_PLL1DIVR_PLLP_SHIFT (9)
#define RCC_PLL1DIVR_PLLQ_SHIFT (16)
#define RCC_PLL1DIVR_PLLR_SHIFT (24)
#define RCC_PLL1FRACR (*(volatile uint32_t *)(RCC_BASE + 0x38)) /* RM0456 - Table 108 */
#define RCC_PLL1FRACR_SHIFT (3)
#define RCC_CIER (*(volatile uint32_t *)(RCC_BASE + 0x50)) /* RM0456 - Table 108 */
#define RCC_AHB1ENR (*(volatile uint32_t *)(RCC_BASE + 0x88)) /* RM0456 - Table 108 */
#define RCC_AHB1ENR_GTZC1EN (1UL << 24)
#define RCC_AHB3ENR (*(volatile uint32_t *)(RCC_BASE + 0x94)) /* RM0456 - Table 108 */
#define RCC_AHB3ENR_GTZC2EN (1UL << 12)
#define RCC_AHB3ENR_PWREN (1UL << 2)
#define RCC_ICSCR1 (*(volatile uint32_t *)(RCC_BASE + 0x08))
#define RCC_ICSCR1_MSIRANGE_SHIFT (28)
#define RCC_ICSCR1_MSIRGSEL (1UL << 23)
#define RCC_ICSCR1_MSIRG_0 (0)
#define RCC_ICSCR2 (*(volatile uint32_t *)(RCC_BASE + 0x0C))
#define RCC_ICSCR2_MSITRIM0_SHIFT (15)
#define RCC_ICSCR2_MSITRIM0_DEFAULT (0x10UL)
#define RCC_ICSCR3 (*(volatile uint32_t *)(RCC_BASE + 0x10))
#define RCC_ICSCR3_HSITRIM_SHIFT (16)
#define RCC_ICSCR3_HSITRIM_DEFAULT (0x10UL)
/*** PWR ***/
/*!< Memory & Instance aliases and base addresses for Non-Secure peripherals */
#define PWR_BASE (0x46020800) /* RM0456 - Table 4 */
#define PWR_VOSR (*(volatile uint32_t *)(PWR_BASE + 0x0C))
#define PWR_VOSR_BOOSTEN (1UL << 18)
#define PWR_VOSR_VOS_SHIFT (16)
#define PWR_VOSR_VOS_4 (0x0UL)
#define PWR_VOSR_VOS_3 (0x1UL)
#define PWR_VOSR_VOS_2 (0x2UL)
#define PWR_VOSR_VOS_1 (0x3UL)
#define PWR_VOSR_VOSRDY (1 << 15)
#define PWR_VOSR_BOOSTRDY (1 << 14)
#define PWR_SVMCR (*(volatile uint32_t *)(PWR_BASE + 0x10))
#define PWR_SVMCR_IOS2V (1 << 29)
#define PWR_UCPDR (*(volatile uint32_t *)(PWR_BASE + 0x2C))
#define PWR_UCPDR_DBDIS (1 << 0)
/*** FLASH ***/
#define SYSCFG_APB2_CLOCK_ER_VAL (1 << 0) /* <<RM0438>> - RCC_APB2ENR - SYSCFGEN */
/* Non-Secure only */
#define FLASH_BASE (0x40022000) /* <<RM0438>> - Table 4 */
#define FLASH_KEYR (*(volatile uint32_t *)(FLASH_BASE + 0x08))
#define FLASH_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x10))
#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x20))
#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x28))
/* Register values (for both secure and non secure registers) */
#define FLASH_SR_EOP (1 << 0)
#define FLASH_SR_OPERR (1 << 1)
#define FLASH_SR_PROGERR (1 << 3)
#define FLASH_SR_WRPERR (1 << 4)
#define FLASH_SR_PGAERR (1 << 5)
#define FLASH_SR_SIZERR (1 << 6)
#define FLASH_SR_PGSERR (1 << 7)
#define FLASH_SR_OPTWERR (1 << 13)
#define FLASH_SR_BSY (1 << 16)
#define FLASH_CR_PG (1 << 0)
#define FLASH_CR_PER (1 << 1)
#define FLASH_CR_MER1 (1 << 2)
#define FLASH_CR_PNB_SHIFT 3
#define FLASH_CR_PNB_MASK 0x7F
#define FLASH_CR_BKER (1 << 11)
#define FLASH_CR_MER2 (1 << 15)
#define FLASH_CR_STRT (1 << 16)
#define FLASH_CR_OPTSTRT (1 << 17)
#define FLASH_CR_EOPIE (1 << 24)
#define FLASH_CR_ERRIE (1 << 25)
#define FLASH_CR_OBL_LAUNCH (1 << 27)
#define FLASH_CR_INV (1 << 29)
#define FLASH_CR_OPTLOCK (1UL << 30)
#define FLASH_CR_LOCK (1UL << 31)
#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
#define FLASH_ACR_LATENCY_MASK (0x0F)
#define FLASH_ACR_PRFTEN (1UL << 8)
#define FLASH_OPTR (*(volatile uint32_t *)(FLASH_BASE + 0x40))
#define FLASH_OPTR_DBANK (1 << 21)
#define FLASH_OPTR_SWAP_BANK (1 << 20)
#define FLASHMEM_ADDRESS_SPACE (0x08000000)
#define FLASH_PAGE_SIZE (0x2000) /* 8KB */
#define FLASH_BANK2_BASE (0x08100000) /*!< Base address of Flash Bank2 */
#define BOOTLOADER_SIZE (0x8000)
#define FLASH_TOP (0x081FFFFF) /*!< FLASH end address */
#define FLASH_KEY1 (0x45670123)
#define FLASH_KEY2 (0xCDEF89AB)
#define FLASH_OPTKEY1 (0x08192A3BU)
#define FLASH_OPTKEY2 (0x4C5D6E7FU)
static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
{
uint32_t reg = FLASH_ACR;
if ((reg & FLASH_ACR_LATENCY_MASK) != waitstates)
FLASH_ACR = (reg & ~FLASH_ACR_LATENCY_MASK) | waitstates ;
}
static RAMFUNCTION void flash_wait_complete(uint8_t bank)
{
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
;
}
static void RAMFUNCTION flash_clear_errors(uint8_t bank)
{
FLASH_SR |= (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR |
FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR);
}
int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
{
int i = 0;
uint32_t *src, *dst;
uint32_t qword[4];
volatile uint32_t *sr, *cr;
cr = &FLASH_CR;
sr = &FLASH_SR;
flash_clear_errors(0);
src = (uint32_t *)data;
dst = (uint32_t *)address;
while (i < len) {
qword[0] = src[i >> 2];
qword[1] = src[(i >> 2) + 1];
qword[2] = src[(i >> 2) + 2];
qword[3] = src[(i >> 2) + 3];
*cr |= FLASH_CR_PG;
dst[i >> 2] = qword[0];
ISB();
dst[(i >> 2) + 1] = qword[1];
ISB();
dst[(i >> 2) + 2] = qword[2];
ISB();
dst[(i >> 2) + 3] = qword[3];
ISB();
flash_wait_complete(0);
if ((*sr & FLASH_SR_EOP) != 0)
*sr |= FLASH_SR_EOP;
*cr &= ~FLASH_CR_PG;
i += 16;
}
return 0;
}
void RAMFUNCTION hal_flash_unlock(void)
{
flash_wait_complete(0);
if ((FLASH_CR & FLASH_CR_LOCK) != 0) {
FLASH_KEYR = FLASH_KEY1;
DMB();
FLASH_KEYR = FLASH_KEY2;
DMB();
while ((FLASH_CR & FLASH_CR_LOCK) != 0)
;
}
}
void RAMFUNCTION hal_flash_lock(void)
{
flash_wait_complete(0);
if ((FLASH_CR & FLASH_CR_LOCK) == 0)
FLASH_CR |= FLASH_CR_LOCK;
}
int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
{
uint32_t end_address;
uint32_t p;
flash_clear_errors(0);
if (len == 0)
return -1;
if (address < ARCH_FLASH_OFFSET)
return -1;
end_address = address + len - 1;
for (p = address; p < end_address; p += FLASH_PAGE_SIZE) {
uint32_t reg;
uint32_t base;
uint32_t bker = 0;
if ((((FLASH_OPTR & FLASH_OPTR_DBANK) == 0) && (p <= FLASH_TOP)) || (p < FLASH_BANK2_BASE)) {
base = FLASHMEM_ADDRESS_SPACE;
}
else if(p >= (FLASH_BANK2_BASE) && (p <= (FLASH_TOP) ))
{
bker = FLASH_CR_BKER;
base = FLASH_BANK2_BASE;
} else {
FLASH_CR &= ~FLASH_CR_PER ;
return 0; /* Address out of range */
}
reg = FLASH_CR & (~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT) | FLASH_CR_BKER));
reg |= ((((p - base) >> 13) << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER | bker );
FLASH_CR = reg;
DMB();
FLASH_CR |= FLASH_CR_STRT;
flash_wait_complete(0);
}
/* If the erase operation is completed, disable the associated bits */
FLASH_CR &= ~FLASH_CR_PER ;
return 0;
}
static void clock_pll_off(void)
{
uint32_t reg32, flash_waitstates ;
/* Select MSI as SYSCLK source. */
reg32 = RCC_CFGR1;
reg32 &= ~((1 << 1) | (1 << 0));
RCC_CFGR1 = (reg32 | RCC_CFGR_SW_MSI);
DMB();
/* Wait for MSI clock to be selected. */
while ((RCC_CFGR1 & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_MSI) {};
flash_waitstates = 1;
flash_set_waitstates(flash_waitstates);
/* Turn off PLL */
RCC_CR &= ~RCC_CR_HSION;
RCC_CR &= ~RCC_CR_PLL1ON;
DMB();
}
/* This implementation will setup MSI 48 MHz as PLL Source Mux, PLLCLK as
* System Clock Source */
static void clock_pll_on(int powersave)
{
uint32_t reg32;
uint32_t pll1n, pll1m, pll1mboost, pll1q, pll1p, pll1r, pll1fracn, pll1rge;
uint32_t hpre, apb1pre, apb2pre, apb3pre, flash_waitstates;
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set MSION bit */
RCC_CR = RCC_CR_MSISON;
/* Reset CFGR register */
RCC_CFGR1 = 0U;
RCC_CFGR2 = 0U;
RCC_CFGR3 = 0U;
/* Reset HSEON, CSSON , HSION, PLLxON bits */
RCC_CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
/* Reset PLLCFGR register */
RCC_PLL1CFGR = 0U;
/* Reset HSEBYP bit */
RCC_CR &= ~(RCC_CR_HSEBYP);
/* Disable all interrupts */
RCC_CIER = 0U;
SCB_VTOR = FLASH_SECURE_MMAP_BASE; /* Vector Table Relocation in Internal FLASH */
FLASH_ACR|=FLASH_ACR_PRFTEN;
RCC_AHB3ENR |= RCC_AHB3ENR_PWREN;
RCC_AHB1ENR |= RCC_AHB1ENR_GTZC1EN;
RCC_AHB3ENR |= RCC_AHB3ENR_GTZC2EN;
PWR_UCPDR |= PWR_UCPDR_DBDIS;
PWR_SVMCR |= PWR_SVMCR_IOS2V;
PWR_VOSR &= ~( (PWR_VOSR_VOS_1 << PWR_VOSR_VOS_SHIFT) | PWR_VOSR_BOOSTEN );
PWR_VOSR|= ((PWR_VOSR_VOS_1<< PWR_VOSR_VOS_SHIFT) | PWR_VOSR_BOOSTEN);
/* Wait until VOSRDY is raised */
reg32 = PWR_VOSR;
while ((PWR_VOSR & PWR_VOSR_VOSRDY) == 0) {};
RCC_ICSCR1|= RCC_ICSCR1_MSIRGSEL;
reg32 = RCC_ICSCR1;
reg32 &= ~( (0xFUL << RCC_ICSCR1_MSIRANGE_SHIFT));
reg32|= (RCC_ICSCR1_MSIRG_0 << RCC_ICSCR1_MSIRANGE_SHIFT);
RCC_ICSCR1 = reg32;
reg32 = RCC_ICSCR1;
DMB();
/* Adjusts the Multiple Speed oscillator (MSI) calibration value */
reg32 = RCC_ICSCR2;
reg32 &= ~((0x1FUL << RCC_ICSCR2_MSITRIM0_SHIFT));
reg32 |= (RCC_ICSCR2_MSITRIM0_DEFAULT << RCC_ICSCR2_MSITRIM0_SHIFT);
RCC_ICSCR2 = reg32;
reg32 = RCC_ICSCR2;
DMB();
flash_waitstates = 1;
flash_set_waitstates(flash_waitstates);
/*----------------------------- HSI Configuration --------------------------*/
/* Enable the Internal High Speed oscillator (HSI) */
RCC_CR |= RCC_CR_HSION;
/* Wait till HSI is ready */
while ((RCC_CR & RCC_CR_HSIRDY) == 0) {};
/* Adjusts the Internal High Speed oscillator (HSI) calibration value */
reg32 = RCC_ICSCR3;
reg32 &= ~((1 << 20) | (1 << 19) | (1 << 18) | (1 << 17) | (1 << 16) );
reg32 |= (RCC_ICSCR3_HSITRIM_DEFAULT << RCC_ICSCR3_HSITRIM_SHIFT);
RCC_ICSCR3 = reg32;
reg32 = RCC_ICSCR3;
DMB();
/*-------------------------------- PLL Configuration -----------------------*/
/* Select clock parameters (CPU Speed = 160 MHz) */
pll1m = 3;
pll1mboost = RCC_PLL1CFGR_PLL1MBOOST_DIV4;
pll1n = 10;
pll1p = 2;
pll1q = 2;
pll1r = 1;
pll1fracn = 0;
pll1rge = RCC_PLL1VCIRANGE_1;
hpre = RCC_AHB_PRESCALER_DIV_NONE;
apb1pre = RCC_APB_PRESCALER_DIV_NONE;
apb2pre = RCC_APB_PRESCALER_DIV_NONE;
apb3pre = RCC_APB_PRESCALER_DIV_NONE;
/* Disable the main PLL */
RCC_CR &= ~RCC_CR_PLL1ON;
/* Wait till PLL is ready */
while ((RCC_CR & RCC_CR_PLL1RDY) != 0) {};
/* Enable PWR CLK */
RCC_AHB3ENR|= RCC_AHB3ENR_PWREN;
/*Disable EPOD to configure PLL1MBOOST*/
PWR_VOSR &= ~PWR_VOSR_BOOSTEN;
/* Configure the main PLL clock source, multiplication and division factors */
reg32 = RCC_PLL1CFGR ;
reg32 &= ~((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12) | (1 << 11) |
(1 << 10) | (1 << 9) | (1 << 8) | (1 << 1) | (1 << 0));
reg32 |= RCC_PLLCKSELR_PLLSRC_MSI;
reg32 |= ((pll1m-1) << RCC_PLL1CFGR_PLLM_SHIFT);
reg32 |= ((pll1mboost) << RCC_PLL1CFGR_PLL1MBOOST_SHIFT);
RCC_PLL1CFGR = reg32;
reg32 =0;
reg32 |= ((pll1n-1) << RCC_PLL1DIVR_PLLN_SHIFT);
reg32 |= ((pll1p-1) << RCC_PLL1DIVR_PLLP_SHIFT);
reg32 |= ((pll1q-1) << RCC_PLL1DIVR_PLLQ_SHIFT);
reg32 |= ((pll1r-1) << RCC_PLL1DIVR_PLLR_SHIFT);
RCC_PLL1DIVR = reg32;
DMB();
/* Disable PLL1FRACN */
RCC_PLL1CFGR&= ~RCC_PLL1CFGR_PLL1FRACEN;
/* Configure PLL PLL1FRACN */
reg32 = RCC_PLL1FRACR ;
reg32 &= ~((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12) | (1 << 11) |
(1 << 10) | (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |
(1 << 5) | (1 << 4) | (1 << 3));
reg32 |= ((pll1fracn) << RCC_PLL1FRACR_SHIFT);
RCC_PLL1FRACR = reg32;
/* Enable PLL1FRACN */
RCC_PLL1CFGR|= RCC_PLL1CFGR_PLL1FRACEN;
/* Select PLL1 input reference frequency range: VCI */
reg32 = RCC_PLL1CFGR ;
reg32 &= ~((1 << 3) | (1 << 2));
reg32 |= ((pll1rge) << RCC_PLL1CFGR_PLL1RGE_SHIFT);
RCC_PLL1CFGR = reg32;
/* Enable the EPOD to reach max frequency */
PWR_VOSR |= PWR_VOSR_BOOSTEN;
/* Disable PWR clk */
RCC_AHB3ENR&=~RCC_AHB3ENR_PWREN;
/* Enable PLL System Clock output */
RCC_PLL1CFGR|=RCC_PLL1CFGR_PLL1REN;
/* Enable the main PLL */
RCC_CR|=RCC_CR_PLL1ON;
/* Wait till PLL is ready */
while ((RCC_CR & RCC_CR_PLL1RDY) == 0) {};
/* Increasing the number of wait states because of higher CPU frequency */
flash_waitstates = 4;
flash_set_waitstates(flash_waitstates);
/* Enable PWR CLK */
RCC_AHB3ENR|= RCC_AHB3ENR_PWREN;
/* Wait till BOOST is ready */
while ((PWR_VOSR & PWR_VOSR_BOOSTRDY) == 0) {};
/*Disable PWR clk */
RCC_AHB3ENR&=~RCC_AHB3ENR_PWREN;
/* Select PLL as SYSCLK source. */
reg32 = RCC_CFGR1;
reg32 &= ~((1 << 1) | (1 << 0));
RCC_CFGR1 = (reg32 | RCC_CFGR_SW_PLL);
DMB();
/* Wait for PLL clock to be selected. */
while ((RCC_CFGR1 & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_PLL) {};
/* HCLK Configuration */
reg32 = RCC_CFGR2 ;
reg32 &= ~((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
reg32 |= hpre;
RCC_CFGR2 = reg32;
DMB();
/* PRE1 and PRE2 conf */
reg32 = RCC_CFGR2 ;
reg32 &= ~((1 << 6) | (1 << 5) | (1 << 4));
reg32 |= ((apb1pre) << RCC_CFGR2_PPRE1_SHIFT) ;
reg32 &= ~((1 << 10) | (1 << 9) | (1 << 8));
reg32 |= ((apb2pre) << RCC_CFGR2_PPRE2_SHIFT) ;
RCC_CFGR2 = reg32;
DMB();
/* PRE3 conf */
reg32 = RCC_CFGR3 ;
reg32 &= ~((1 << 6) | (1 << 5) | (1 << 4));
reg32 |= ((apb3pre) << RCC_CFGR3_PPRE3_SHIFT) ;
RCC_CFGR3 = reg32;
DMB();
/* Disable PWR clk */
RCC_AHB3ENR&=~RCC_AHB3ENR_PWREN;
}
void hal_init(void)
{
clock_pll_on(0);
}

53
test-app/ARM-stm32h5-ns.ld 100644
View File

@ -0,0 +1,53 @@
MEMORY
{
FLASH (rx) : ORIGIN = @WOLFBOOT_TEST_APP_ADDRESS@, LENGTH = @WOLFBOOT_TEST_APP_SIZE@
RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x20000
}
SECTIONS
{
.text :
{
_start_text = .;
. = ALIGN(8);
KEEP(*(.isr_vector))
. = ALIGN(8);
*(.init)
*(.fini)
*(.text*)
*(.rodata*)
. = ALIGN(8);
_end_text = .;
} > FLASH
.edidx :
{
. = ALIGN(4);
*(.ARM.exidx*)
} > FLASH
_stored_data = .;
.data : AT (_stored_data)
{
_start_data = .;
KEEP(*(.data*))
. = ALIGN(8);
KEEP(*(.ramcode))
. = ALIGN(8);
_end_data = .;
} > RAM
.bss :
{
_start_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(8);
_end_bss = .;
_end = .;
} > RAM
}
PROVIDE(_start_heap = _end);
PROVIDE(_end_stack = ORIGIN(RAM) + LENGTH(RAM));

53
test-app/ARM-stm32h5.ld 100644
View File

@ -0,0 +1,53 @@
MEMORY
{
FLASH (rx) : ORIGIN = @WOLFBOOT_TEST_APP_ADDRESS@, LENGTH = @WOLFBOOT_TEST_APP_SIZE@
RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 64K /* Run in lowmem */
}
SECTIONS
{
.text :
{
_start_text = .;
. = ALIGN(8);
KEEP(*(.isr_vector))
. = ALIGN(8);
*(.init)
*(.fini)
*(.text*)
*(.rodata*)
. = ALIGN(8);
_end_text = .;
} > FLASH
.edidx :
{
. = ALIGN(4);
*(.ARM.exidx*)
} > FLASH
_stored_data = .;
.data : AT (_stored_data)
{
_start_data = .;
KEEP(*(.data*))
. = ALIGN(8);
KEEP(*(.ramcode))
. = ALIGN(8);
_end_data = .;
} > RAM
.bss :
{
_start_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(8);
_end_bss = .;
_end = .;
} > RAM
}
PROVIDE(_start_heap = _end);
PROVIDE(_end_stack = ORIGIN(RAM) + LENGTH(RAM));

6
test-app/ARM-stm32u5-ns.ld
View File

@ -20,6 +20,12 @@ SECTIONS
_end_text = .;
} > FLASH
.edidx :
{
. = ALIGN(4);
*(.ARM.exidx*)
} > FLASH
_stored_data = .;
.data : AT (_stored_data)

6
test-app/ARM-stm32u5.ld
View File

@ -20,6 +20,12 @@ SECTIONS
_end_text = .;
} > FLASH
.edidx :
{
. = ALIGN(4);
*(.ARM.exidx*)
} > FLASH
_stored_data = .;
.data : AT (_stored_data)

22
test-app/Makefile
View File

@ -6,7 +6,7 @@
TARGET?=none
ARCH?=ARM
MCUXPRESSO_CMSIS?=$(MCUXPRESSO)/CMSIS
CFLAGS+=-I.
CFLAGS+=-I. -I..
CFLAGS+=-I./wcs
DEBUG?=1
DELTA_DATA_SIZE?=2000
@ -56,6 +56,8 @@ ifeq ($(DEBUG_UART),1)
endif
ifeq ($(TZEN),1)
CFLAGS+=-DNONSECURE_APP
CFLAGS+=-I./
APP_OBJS+=../hal/$(TARGET)_ns.o
ifeq ($(WOLFCRYPT_TZ),1)
APP_OBJS+=../src/wc_secure_calls.o
@ -151,6 +153,19 @@ ifeq ($(TARGET),stm32l5)
APP_OBJS+=../hal/uart/uart_drv_$(UART_TARGET).o
endif
ifeq ($(TARGET),stm32h5)
ifeq ($(TZEN),1)
LSCRIPT_TEMPLATE=ARM-stm32h5-ns.ld
APP_OBJS+=wcs/wolfcrypt_secure.o
else
LSCRIPT_TEMPLATE=ARM-stm32h5.ld
endif
CFLAGS+=-mcpu=cortex-m33 -ffunction-sections -fdata-sections -fno-common
LDFLAGS+=-mcpu=cortex-m33
LDFLAGS+=-Wl,-gc-sections -Wl,-Map=image.map
CFLAGS+=-I..
endif
ifeq ($(TARGET),stm32u5)
ifeq ($(TZEN),1)
LSCRIPT_TEMPLATE=ARM-stm32u5-ns.ld
@ -369,6 +384,9 @@ delta-extra-data: image.bin
@echo "\t[CC-$(ARCH)] $@"
$(Q)$(CC) $(CFLAGS) -c $(OUTPUT_FLAG) $@ ../src/libwolfboot.c
../hal/$(TARGET)_ns.o: ../hal/$(TARGET).c FORCE
$(Q)$(CC) $(CFLAGS) -c -o $(@) ../hal/$(TARGET).c -DNONSECURE_APP
%.o:%.c
@echo "\t[CC-$(ARCH)] $@"
$(Q)$(CC) $(CFLAGS) -c $(OUTPUT_FLAG) $@ $^
@ -399,6 +417,8 @@ $(LSCRIPT): $(LSCRIPT_TEMPLATE) FORCE
> $(@)
$(Q)rm -f .app-size .entry-point .wolfboot-offset .partition-size .header-size
FORCE:
.PHONY: FORCE clean

130
test-app/app_stm32h5.c 100644
View File

@ -0,0 +1,130 @@
/* app_stm32h5.c
*
* Test bare-metal application.
*
* Copyright (C) 2024 wolfSSL Inc.
*
* This file is part of wolfBoot.
*
* wolfBoot is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* wolfBoot is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
*/
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include "system.h"
#include "hal.h"
#include "wolfboot/wolfboot.h"
#define LED_BOOT_PIN (4) /* PG4 - Nucleo - Red Led */
#define LED_USR_PIN (0) /* PB0 - Nucleo - Green Led */
#define LED_USR2_PIN (4) /* PF4 - Nucleo - Orange Led */
/*Non-Secure */
#define RCC_BASE (0x44020C00) /* RM0481 - Table 3 */
#define GPIOG_BASE 0x42021800
#define GPIOB_BASE 0x42020400
#define GPIOF_BASE 0x42021400
#define GPIOG_MODER (*(volatile uint32_t *)(GPIOG_BASE + 0x00))
#define GPIOG_PUPDR (*(volatile uint32_t *)(GPIOG_BASE + 0x0C))
#define GPIOG_BSRR (*(volatile uint32_t *)(GPIOG_BASE + 0x18))
#define GPIOB_MODER (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
#define GPIOB_PUPDR (*(volatile uint32_t *)(GPIOB_BASE + 0x0C))
#define GPIOB_BSRR (*(volatile uint32_t *)(GPIOB_BASE + 0x18))
#define GPIOF_MODER (*(volatile uint32_t *)(GPIOF_BASE + 0x00))
#define GPIOF_PUPDR (*(volatile uint32_t *)(GPIOF_BASE + 0x0C))
#define GPIOF_BSRR (*(volatile uint32_t *)(GPIOF_BASE + 0x18))
#define RCC_AHB2ENR1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C ))
#define GPIOG_AHB2ENR1_CLOCK_ER (1 << 6)
#define GPIOF_AHB2ENR1_CLOCK_ER (1 << 5)
#define GPIOB_AHB2ENR1_CLOCK_ER (1 << 1)
static void boot_led_on(void)
{
uint32_t reg;
uint32_t pin = LED_BOOT_PIN;
RCC_AHB2ENR1_CLOCK_ER|= GPIOG_AHB2ENR1_CLOCK_ER;
/* Delay after an RCC peripheral clock enabling */
reg = RCC_AHB2ENR1_CLOCK_ER;
reg = GPIOG_MODER & ~(0x03 << (pin * 2));
GPIOG_MODER = reg | (1 << (pin * 2));
GPIOG_PUPDR &= ~(0x03 << (pin * 2));
GPIOG_BSRR |= (1 << (pin));
}
static void boot_led_off(void)
{
GPIOG_BSRR |= (1 << (LED_BOOT_PIN + 16));
}
void usr_led_on(void)
{
uint32_t reg;
uint32_t pin = LED_USR_PIN;
RCC_AHB2ENR1_CLOCK_ER|= GPIOB_AHB2ENR1_CLOCK_ER;
/* Delay after an RCC peripheral clock enabling */
reg = RCC_AHB2ENR1_CLOCK_ER;
reg = GPIOB_MODER & ~(0x03 << (pin * 2));
GPIOB_MODER = reg | (1 << (pin * 2));
GPIOB_PUPDR &= ~(0x03 << (pin * 2));
GPIOB_BSRR |= (1 << (pin));
}
void usr_led_off(void)
{
GPIOB_BSRR |= (1 << (LED_USR_PIN + 16));
}
void usr2_led_on(void)
{
uint32_t reg;
uint32_t pin = LED_USR2_PIN;
RCC_AHB2ENR1_CLOCK_ER|= GPIOF_AHB2ENR1_CLOCK_ER;
/* Delay after an RCC peripheral clock enabling */
reg = RCC_AHB2ENR1_CLOCK_ER;
reg = GPIOF_MODER & ~(0x03 << (pin * 2));
GPIOF_MODER = reg | (1 << (pin * 2));
GPIOF_PUPDR &= ~(0x03 << (pin * 2));
GPIOF_BSRR |= (1 << (pin));
}
void usr2_led_off(void)
{
GPIOF_BSRR |= (1 << (LED_USR2_PIN + 16));
}
void main(void)
{
hal_init();
boot_led_on();
usr_led_on();
boot_led_off();
if (wolfBoot_current_firmware_version() > 1)
usr2_led_on();
while(1)
;
}