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Fixed stm32h7.c hal write from app

pull/92/head
Daniele Lacamera 2020-11-20 12:59:51 +01:00
parent 95a75627ef
commit 2394c7424e
3 changed files with 63 additions and 0 deletions
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14
hal/stm32h7.c
View File

@ -99,6 +99,7 @@
#define FLASH_BASE (0x52002000) //RM0433 - Table 8 #define FLASH_BASE (0x52002000) //RM0433 - Table 8
#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00)) //RM0433 - 3.9.1 - FLASH_ACR #define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00)) //RM0433 - 3.9.1 - FLASH_ACR
#define FLASH_OPTSR_CUR (*(volatile uint32_t *)(FLASH_BASE + 0x1C))
/*bank 1 */ /*bank 1 */
#define FLASH_KEYR1 (*(volatile uint32_t *)(FLASH_BASE + 0x04)) //RM0433 - 3.9.2 - FLASH_KEYR 1 #define FLASH_KEYR1 (*(volatile uint32_t *)(FLASH_BASE + 0x04)) //RM0433 - 3.9.2 - FLASH_KEYR 1
@ -140,6 +141,8 @@
#define FLASH_CR_PG (1 << 1) #define FLASH_CR_PG (1 << 1)
#define FLASH_CR2_SPSS2 (1 << 14) #define FLASH_CR2_SPSS2 (1 << 14)
#define FLASH_OPTSR_CUR_BSY (1 << 0)
#define FLASH_CR_SNB_SHIFT 8 //SNB bits 10:8 #define FLASH_CR_SNB_SHIFT 8 //SNB bits 10:8
#define FLASH_CR_SNB_MASK 0x7 //SNB bits 10:8 - 3 bits #define FLASH_CR_SNB_MASK 0x7 //SNB bits 10:8 - 3 bits
@ -153,6 +156,12 @@ static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
FLASH_ACR = (reg & ~FLASH_ACR_LATENCY_MASK) | waitstates ; FLASH_ACR = (reg & ~FLASH_ACR_LATENCY_MASK) | waitstates ;
} }
static RAMFUNCTION void flash_wait_last(void)
{
while((FLASH_OPTSR_CUR & FLASH_OPTSR_CUR_BSY))
;
}
static RAMFUNCTION void flash_wait_complete(uint8_t bank) static RAMFUNCTION void flash_wait_complete(uint8_t bank)
{ {
if(bank==0) if(bank==0)
@ -202,6 +211,7 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
} }
while (i < len) { while (i < len) {
flash_wait_last();
flash_clear_errors(0); flash_clear_errors(0);
flash_clear_errors(1); flash_clear_errors(1);
flash_program_on(bank); flash_program_on(bank);
@ -224,9 +234,13 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
} }
while ((off < 32) && (i < len)) while ((off < 32) && (i < len))
vbytes[off++] = data[i++]; vbytes[off++] = data[i++];
ISB();
DSB();
for (ii = 0; ii < 8; ii++) { for (ii = 0; ii < 8; ii++) {
dst[ii] = val[ii]; dst[ii] = val[ii];
} }
ISB();
DSB();
} }
flash_wait_complete(bank); flash_wait_complete(bank);
flash_program_off(bank); flash_program_off(bank);

45
test-app/ARM-stm32h7.ld 100644
View File

@ -0,0 +1,45 @@
MEMORY
{
FLASH (rx) : ORIGIN = ##WOLFBOOT_TEST_APP_ADDRESS##, LENGTH = ##WOLFBOOT_TEST_APP_SIZE##
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* mapping TCM only */
}
SECTIONS
{
.text :
{
_start_text = .;
KEEP(*(.isr_vector))
*(.init)
*(.fini)
*(.text*)
*(.rodata*)
. = ALIGN(4);
_end_text = .;
} > FLASH
_stored_data = .;
.data : AT (_stored_data)
{
_start_data = .;
KEEP(*(.data*))
. = ALIGN(4);
KEEP(*(.ramcode))
. = ALIGN(4);
_end_data = .;
} > RAM
.bss (NOLOAD) :
{
_start_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
_end_bss = .;
_end = .;
} > RAM
}
PROVIDE(_start_heap = _end);
PROVIDE(_end_stack = ORIGIN(RAM) + LENGTH(RAM));

4
test-app/Makefile
View File

@ -63,6 +63,10 @@ ifeq ($(TARGET),stm32f7)
CFLAGS+=-DDUALBANK_SWAP CFLAGS+=-DDUALBANK_SWAP
endif endif
ifeq ($(TARGET),stm32h7)
LSCRIPT_TEMPLATE=ARM-stm32h7.ld
endif
ifeq ($(TARGET),stm32l5) ifeq ($(TARGET),stm32l5)
ifeq ($(TZEN),1) ifeq ($(TZEN),1)
LSCRIPT_TEMPLATE=ARM-stm32l5-ns.ld LSCRIPT_TEMPLATE=ARM-stm32l5-ns.ld