mirror of https://github.com/wolfSSL/wolfBoot.git
Fixed stm32h7.c hal write from app
parent
95a75627ef
commit
2394c7424e
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@ -99,6 +99,7 @@
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#define FLASH_BASE (0x52002000) //RM0433 - Table 8
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#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00)) //RM0433 - 3.9.1 - FLASH_ACR
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#define FLASH_OPTSR_CUR (*(volatile uint32_t *)(FLASH_BASE + 0x1C))
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/*bank 1 */
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#define FLASH_KEYR1 (*(volatile uint32_t *)(FLASH_BASE + 0x04)) //RM0433 - 3.9.2 - FLASH_KEYR 1
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@ -140,6 +141,8 @@
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#define FLASH_CR_PG (1 << 1)
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#define FLASH_CR2_SPSS2 (1 << 14)
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#define FLASH_OPTSR_CUR_BSY (1 << 0)
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#define FLASH_CR_SNB_SHIFT 8 //SNB bits 10:8
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#define FLASH_CR_SNB_MASK 0x7 //SNB bits 10:8 - 3 bits
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@ -153,6 +156,12 @@ static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
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FLASH_ACR = (reg & ~FLASH_ACR_LATENCY_MASK) | waitstates ;
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}
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static RAMFUNCTION void flash_wait_last(void)
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{
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while((FLASH_OPTSR_CUR & FLASH_OPTSR_CUR_BSY))
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;
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}
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static RAMFUNCTION void flash_wait_complete(uint8_t bank)
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{
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if(bank==0)
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@ -202,6 +211,7 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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}
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while (i < len) {
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flash_wait_last();
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flash_clear_errors(0);
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flash_clear_errors(1);
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flash_program_on(bank);
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@ -224,9 +234,13 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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}
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while ((off < 32) && (i < len))
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vbytes[off++] = data[i++];
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ISB();
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DSB();
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for (ii = 0; ii < 8; ii++) {
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dst[ii] = val[ii];
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}
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ISB();
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DSB();
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}
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flash_wait_complete(bank);
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flash_program_off(bank);
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@ -0,0 +1,45 @@
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MEMORY
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{
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FLASH (rx) : ORIGIN = ##WOLFBOOT_TEST_APP_ADDRESS##, LENGTH = ##WOLFBOOT_TEST_APP_SIZE##
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* mapping TCM only */
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}
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SECTIONS
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{
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.text :
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{
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_start_text = .;
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KEEP(*(.isr_vector))
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*(.init)
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*(.fini)
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*(.text*)
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*(.rodata*)
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. = ALIGN(4);
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_end_text = .;
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} > FLASH
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_stored_data = .;
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.data : AT (_stored_data)
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{
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_start_data = .;
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KEEP(*(.data*))
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. = ALIGN(4);
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KEEP(*(.ramcode))
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. = ALIGN(4);
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_end_data = .;
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} > RAM
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.bss (NOLOAD) :
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{
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_start_bss = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_end_bss = .;
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_end = .;
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} > RAM
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}
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PROVIDE(_start_heap = _end);
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PROVIDE(_end_stack = ORIGIN(RAM) + LENGTH(RAM));
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@ -63,6 +63,10 @@ ifeq ($(TARGET),stm32f7)
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CFLAGS+=-DDUALBANK_SWAP
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endif
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ifeq ($(TARGET),stm32h7)
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LSCRIPT_TEMPLATE=ARM-stm32h7.ld
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endif
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ifeq ($(TARGET),stm32l5)
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ifeq ($(TZEN),1)
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LSCRIPT_TEMPLATE=ARM-stm32l5-ns.ld
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