From 248fd985b3ccf56a28e3575e196001a41865801d Mon Sep 17 00:00:00 2001 From: Alex Lanzano Date: Fri, 16 May 2025 12:29:08 -0400 Subject: [PATCH] Update stm32f4 test-app to use config options to setup clock and uart Allows the pll clock to be configured using the config macros instead of being hard coded. --- test-app/app_stm32f4.c | 122 ++++++++++++++++++++++++++--------------- test-app/system.c | 18 ++++-- 2 files changed, 90 insertions(+), 50 deletions(-) diff --git a/test-app/app_stm32f4.c b/test-app/app_stm32f4.c index 7097f1cc..d105104d 100644 --- a/test-app/app_stm32f4.c +++ b/test-app/app_stm32f4.c @@ -34,14 +34,15 @@ #ifdef TARGET_stm32f4 -#define UART1 (0x40011000) - -#define UART1_SR (*(volatile uint32_t *)(UART1)) -#define UART1_DR (*(volatile uint32_t *)(UART1 + 0x04)) -#define UART1_BRR (*(volatile uint32_t *)(UART1 + 0x08)) -#define UART1_CR1 (*(volatile uint32_t *)(UART1 + 0x0c)) -#define UART1_CR2 (*(volatile uint32_t *)(UART1 + 0x10)) +#ifndef CLOCK_SPEED +#define CLOCK_SPEED (168000000) +#endif +/* Common UART Config */ +#if !defined(USE_UART1) && !defined(USE_UART3) +#define USE_UART3 +#endif +#define UART_PIN_AF 7 #define UART_CR1_UART_ENABLE (1 << 13) #define UART_CR1_SYMBOL_LEN (1 << 12) #define UART_CR1_PARITY_ENABLED (1 << 10) @@ -53,21 +54,52 @@ #define UART_SR_RX_NOTEMPTY (1 << 5) -#define CLOCK_SPEED (168000000) +/* Common GPIO Config */ +#define GPIO_MODE_AF (2) -#define APB2_CLOCK_ER (*(volatile uint32_t *)(0x40023844)) -#define UART1_APB2_CLOCK_ER (1 << 4) +/* UART1 Config */ +#ifdef USE_UART1 +#define UART_RX_PIN 7 +#define UART_TX_PIN 6 -#define AHB1_CLOCK_ER (*(volatile uint32_t *)(0x40023830)) -#define GPIOB_AHB1_CLOCK_ER (1 << 1) +#define UART1 (0x40011000) +#define UART_SR (*(volatile uint32_t *)(UART1)) +#define UART_DR (*(volatile uint32_t *)(UART1 + 0x04)) +#define UART_BRR (*(volatile uint32_t *)(UART1 + 0x08)) +#define UART_CR1 (*(volatile uint32_t *)(UART1 + 0x0c)) +#define UART_CR2 (*(volatile uint32_t *)(UART1 + 0x10)) + +#define UART_CLOCK_ER (*(volatile uint32_t *)(0x40023844)) +#define UART_CLOCK_ER_VAL (1 << 4) + +#define GPIO_CLOCK_ER (*(volatile uint32_t *)(0x40023830)) +#define GPIO_CLOCK_ER_VAL (1 << 1) #define GPIOB_BASE 0x40020400 +#define GPIO_MODE (*(volatile uint32_t *)(GPIOB_BASE + 0x00)) +#define GPIO_AF (*(volatile uint32_t *)(GPIOB_BASE + 0x20)) +#endif -#define GPIOB_MODE (*(volatile uint32_t *)(GPIOB_BASE + 0x00)) -#define GPIOB_AFL (*(volatile uint32_t *)(GPIOB_BASE + 0x20)) -#define GPIOB_AFH (*(volatile uint32_t *)(GPIOB_BASE + 0x24)) -#define UART1_PIN_AF 7 -#define UART1_RX_PIN 7 -#define UART1_TX_PIN 6 +/* UART3 Config */ +#ifdef USE_UART3 +#define UART_RX_PIN 9 +#define UART_TX_PIN 8 + +#define UART3 (0x40004800) +#define UART_SR (*(volatile uint32_t *)(UART3)) +#define UART_DR (*(volatile uint32_t *)(UART3 + 0x04)) +#define UART_BRR (*(volatile uint32_t *)(UART3 + 0x08)) +#define UART_CR1 (*(volatile uint32_t *)(UART3 + 0x0c)) +#define UART_CR2 (*(volatile uint32_t *)(UART3 + 0x10)) + +#define UART_CLOCK_ER (*(volatile uint32_t *)(0x40023840)) +#define UART_CLOCK_ER_VAL (1 << 18) + +#define GPIO_CLOCK_ER (*(volatile uint32_t *)(0x40023830)) +#define GPIO_CLOCK_ER_VAL (1 << 3) +#define GPIOD_BASE 0x40020c00 +#define GPIO_MODE (*(volatile uint32_t *)(GPIOD_BASE + 0x00)) +#define GPIO_AF (*(volatile uint32_t *)(GPIOD_BASE + 0x20)) +#endif #define MSGSIZE 16 #define PAGESIZE (256) @@ -100,26 +132,26 @@ void uart_write(const char c) { uint32_t reg; do { - reg = UART1_SR; + reg = UART_SR; } while ((reg & UART_SR_TX_EMPTY) == 0); - UART1_DR = c; + UART_DR = c; } static void uart_pins_setup(void) { uint32_t reg; - AHB1_CLOCK_ER |= GPIOB_AHB1_CLOCK_ER; + GPIO_CLOCK_ER |= GPIO_CLOCK_ER_VAL; /* Set mode = AF */ - reg = GPIOB_MODE & ~ (0x03 << (UART1_RX_PIN * 2)); - GPIOB_MODE = reg | (2 << (UART1_RX_PIN * 2)); - reg = GPIOB_MODE & ~ (0x03 << (UART1_TX_PIN * 2)); - GPIOB_MODE = reg | (2 << (UART1_TX_PIN * 2)); + reg = GPIO_MODE & ~ (0x03 << (UART_RX_PIN * 2)); + GPIO_MODE = reg | (2 << (UART_RX_PIN * 2)); + reg = GPIO_MODE & ~ (0x03 << (UART_TX_PIN * 2)); + GPIO_MODE = reg | (2 << (UART_TX_PIN * 2)); /* Alternate function: use low pins (6 and 7) */ - reg = GPIOB_AFL & ~(0xf << ((UART1_TX_PIN) * 4)); - GPIOB_AFL = reg | (UART1_PIN_AF << ((UART1_TX_PIN) * 4)); - reg = GPIOB_AFL & ~(0xf << ((UART1_RX_PIN) * 4)); - GPIOB_AFL = reg | (UART1_PIN_AF << ((UART1_RX_PIN) * 4)); + reg = GPIO_AF & ~(0xf << ((UART_TX_PIN) * 4)); + GPIO_AF = reg | (UART_PIN_AF << ((UART_TX_PIN) * 4)); + reg = GPIO_AF & ~(0xf << ((UART_RX_PIN) * 4)); + GPIO_AF = reg | (UART_PIN_AF << ((UART_RX_PIN) * 4)); } int uart_setup(uint32_t bitrate, uint8_t data, char parity, uint8_t stop) @@ -128,40 +160,40 @@ int uart_setup(uint32_t bitrate, uint8_t data, char parity, uint8_t stop) /* Enable pins and configure for AF7 */ uart_pins_setup(); /* Turn on the device */ - APB2_CLOCK_ER |= UART1_APB2_CLOCK_ER; + UART_CLOCK_ER |= UART_CLOCK_ER_VAL; /* Configure for TX + RX */ - UART1_CR1 |= (UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE); + UART_CR1 |= (UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE); /* Configure clock */ - UART1_BRR = CLOCK_SPEED / bitrate; + UART_BRR = CLOCK_SPEED / bitrate; /* Configure data bits */ if (data == 8) - UART1_CR1 &= ~UART_CR1_SYMBOL_LEN; + UART_CR1 &= ~UART_CR1_SYMBOL_LEN; else - UART1_CR1 |= UART_CR1_SYMBOL_LEN; + UART_CR1 |= UART_CR1_SYMBOL_LEN; /* Configure parity */ switch (parity) { case 'O': - UART1_CR1 |= UART_CR1_PARITY_ODD; + UART_CR1 |= UART_CR1_PARITY_ODD; /* fall through to enable parity */ case 'E': - UART1_CR1 |= UART_CR1_PARITY_ENABLED; + UART_CR1 |= UART_CR1_PARITY_ENABLED; break; default: - UART1_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD); + UART_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD); } /* Set stop bits */ - reg = UART1_CR2 & ~UART_CR2_STOPBITS; + reg = UART_CR2 & ~UART_CR2_STOPBITS; if (stop > 1) - UART1_CR2 = reg & (2 << 12); + UART_CR2 = reg & (2 << 12); else - UART1_CR2 = reg; + UART_CR2 = reg; /* Turn on uart */ - UART1_CR1 |= UART_CR1_UART_ENABLE; + UART_CR1 |= UART_CR1_UART_ENABLE; return 0; } @@ -171,9 +203,9 @@ char uart_read(void) char c; volatile uint32_t reg; do { - reg = UART1_SR; + reg = UART_SR; } while ((reg & UART_SR_RX_NOTEMPTY) == 0); - c = (char)(UART1_DR & 0xff); + c = (char)(UART_DR & 0xff); return c; } @@ -215,7 +247,7 @@ void main(void) { flash_set_waitstates(); clock_config(); led_pwm_setup(); - pwm_init(CPU_FREQ, 0); + pwm_init(CLOCK_SPEED, 0); /* Dim the led by altering the PWM duty-cicle * in isr_tim2 (timer.c) @@ -224,7 +256,7 @@ void main(void) { * to the blue led increases/decreases making a pulse * effect. */ - timer_init(CPU_FREQ, 1, 50); + timer_init(CLOCK_SPEED, 1, 50); uart_setup(115200, 8, 'N', 1); memset(page, 0xFF, PAGESIZE); asm volatile ("cpsie i"); diff --git a/test-app/system.c b/test-app/system.c index a49b04f8..799bd2da 100644 --- a/test-app/system.c +++ b/test-app/system.c @@ -57,12 +57,20 @@ #define RCC_PRESCALER_DIV_4 9 -/* STM32F4-Discovery, 168 MHz */ +/* STM32F4 */ #ifdef TARGET_stm32f4 -# define PLLM 8 -# define PLLN 336 -# define PLLP 2 -# define PLLQ 7 +# if defined(STM32_PLLM) && defined(STM32_PLLN) && \ + defined(STM32_PLLP) && defined(STM32_PLLQ) +# define PLLM STM32_PLLM +# define PLLN STM32_PLLN +# define PLLP STM32_PLLP +# define PLLQ STM32_PLLQ +# else +# define PLLM 8 +# define PLLN 336 +# define PLLP 2 +# define PLLQ 7 +# endif # define PLLR 0 # define TARGET_FLASH_WAITSTATES 5 #endif