mirror of https://github.com/wolfSSL/wolfBoot.git
Make Stm32 SPI driver more generic to reuse on other STM32 platforms
Daniele Lacamera
parent
453a07bd7b
commit
25455744b6
4
Makefile
4
Makefile
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@ -95,7 +95,7 @@ ifeq ($(SPI_FLASH),1)
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EXT_FLASH=1
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CFLAGS+= -DSPI_FLASH=1
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OBJS+= src/spi_flash.o
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WOLFCRYPT_OBJS+=hal/spi/spi_drv_$(TARGET).o
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WOLFCRYPT_OBJS+=hal/spi/spi_drv_$(SPI_TARGET).o
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endif
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ifeq ($(EXT_FLASH),1)
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@ -132,7 +132,7 @@ OBJS += lib/wolfTPM/src/tpm2.o \
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lib/wolfTPM/src/tpm2_tis.o \
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lib/wolfTPM/src/tpm2_wrap.o \
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src/ecc256_pub_key.o \
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hal/spi/spi_drv_$(TARGET).o
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hal/spi/spi_drv_$(SPI_TARGET).o
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CFLAGS+=-DWOLFTPM_SLB9670 -DWOLFTPM2_NO_WOLFCRYPT -DSIZEOF_LONG=4 -Ilib/wolfTPM \
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-DMAX_COMMAND_SIZE=1024 -DMAX_RESPONSE_SIZE=1024 -DWOLFTPM2_MAX_BUFFER=1500 -DMAX_SESSION_NUM=1 -DMAX_DIGEST_BUFFER=973 \
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-DWOLFTPM_SMALL_STACK
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9
arch.mk
9
arch.mk
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@ -10,6 +10,9 @@ endif
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# Default flash offset
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ARCH_FLASH_OFFSET=0x0
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# Default SPI driver name
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SPI_TARGET=$(TARGET)
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## ARM
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ifeq ($(ARCH),ARM)
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CROSS_COMPILE:=arm-none-eabi-
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@ -32,10 +35,12 @@ ifeq ($(ARCH),ARM)
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ifeq ($(TARGET),stm32f7)
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ARCH_FLASH_OFFSET=0x08000000
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SPI_TARGET=stm32
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endif
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ifeq ($(TARGET),stm32h7)
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ARCH_FLASH_OFFSET=0x08000000
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SPI_TARGET=stm32
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endif
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## Cortex-M CPU
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@ -102,8 +107,12 @@ OBJCOPY:=$(CROSS_COMPILE)objcopy
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SIZE:=$(CROSS_COMPILE)size
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BOOT_IMG?=test-app/image.bin
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ifeq ($(TARGET),stm32f4)
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SPI_TARGET=stm32
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endif
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ifeq ($(TARGET),stm32wb)
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SPI_TARGET=stm32
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ifneq ($(PKA),0)
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ECC_EXTRA_OBJS+= $(STM32CUBE)/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.o ./lib/wolfssl/wolfcrypt/src/port/st/stm32.o
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ECC_EXTRA_CFLAGS+=-DWOLFSSL_STM32_PKA -I$(STM32CUBE)/Drivers/STM32WBxx_HAL_Driver/Inc \
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@ -0,0 +1,171 @@
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/* spi_drv.h
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*
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* Driver for the SPI back-end of the SPI_FLASH module.
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*
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* Example implementation for stm32F4, using SPI1.
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*
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* Pinout: see spi_drv_stm32.h
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*
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* Copyright (C) 2019 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include "spi_drv.h"
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#include "spi_drv_stm32.h"
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void spi_cs_off(int pin)
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{
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SPI_PIO_CS_BSRR |= (1 << pin);
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while(!(SPI_PIO_CS_ODR & (1 << pin)))
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;
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}
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void spi_cs_on(int pin)
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{
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SPI_PIO_CS_BSRR |= (1 << (pin + 16));
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while(SPI_PIO_CS_ODR & (1 << pin))
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;
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}
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static void spi_flash_pin_setup(void)
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{
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uint32_t reg;
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RCC_GPIO_CLOCK_ER |= SPI_PIO_CS_CEN;
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reg = SPI_PIO_CS_MODE & ~ (0x03 << (SPI_CS_FLASH * 2));
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SPI_PIO_CS_MODE = reg | (1 << (SPI_CS_FLASH * 2));
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reg = SPI_PIO_CS_PUPD & ~(0x03 << (SPI_CS_FLASH * 2));
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SPI_PIO_CS_PUPD = reg | (0x01 << (SPI_CS_FLASH * 2));
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reg = SPI_PIO_CS_OSPD & ~(0x03 << (SPI_CS_FLASH * 2));
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SPI_PIO_CS_OSPD |= (0x03 << (SPI_CS_FLASH * 2));
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spi_cs_off(SPI_CS_FLASH);
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}
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static void spi_tpm2_pin_setup(void)
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{
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#ifdef WOLFTPM2_NO_WOLFCRYPT
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uint32_t reg;
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RCC_GPIO_CLOCK_ER |= SPI_PIO_CS_EN;
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reg = SPI_PIO_CS_MODE & ~ (0x03 << (SPI_CS_TPM * 2));
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SPI_PIO_CS_MODE = reg | (1 << (SPI_CS_TPM * 2));
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reg = SPI_PIO_CS_PUPD & ~(0x03 << (SPI_CS_TPM * 2));
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SPI_PIO_CS_PUPD = reg | (0x01 << (SPI_CS_TPM * 2));
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reg = SPI_PIO_CS_OSPD & ~(0x03 << (SPI_CS_TPM * 2));
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SPI_PIO_CS_OSPD |= (0x03 << (SPI_CS_TPM * 2));
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spi_cs_off(SPI_CS_TPM);
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#endif
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}
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static void spi1_pins_setup(void)
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{
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uint32_t reg;
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RCC_GPIO_CLOCK_ER |= SPI_PIO_CEN;
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/* Set mode = AF */
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reg = SPI_PIO_MODE & ~ (0x03 << (SPI1_CLOCK_PIN * 2));
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SPI_PIO_MODE = reg | (2 << (SPI1_CLOCK_PIN * 2));
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reg = SPI_PIO_MODE & ~ (0x03 << (SPI1_MOSI_PIN * 2));
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SPI_PIO_MODE = reg | (2 << (SPI1_MOSI_PIN * 2));
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reg = SPI_PIO_MODE & ~ (0x03 << (SPI1_MISO_PIN * 2));
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SPI_PIO_MODE = reg | (2 << (SPI1_MISO_PIN * 2));
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/* Alternate function: use low pins (5,6,7) */
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reg = SPI_PIO_AFL & ~(0xf << ((SPI1_CLOCK_PIN) * 4));
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SPI_PIO_AFL = reg | (SPI1_PIN_AF << ((SPI1_CLOCK_PIN) * 4));
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reg = SPI_PIO_AFL & ~(0xf << ((SPI1_MOSI_PIN) * 4));
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SPI_PIO_AFL = reg | (SPI1_PIN_AF << ((SPI1_MOSI_PIN) * 4));
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reg = SPI_PIO_AFL & ~(0xf << ((SPI1_MISO_PIN) * 4));
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SPI_PIO_AFL = reg | (SPI1_PIN_AF << ((SPI1_MISO_PIN) * 4));
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}
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static void spi_pins_release(void)
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{
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uint32_t reg;
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/* Set mode = 0 */
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SPI_PIO_MODE &= ~ (0x03 << (SPI1_CLOCK_PIN * 2));
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SPI_PIO_MODE &= ~ (0x03 << (SPI1_MOSI_PIN * 2));
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SPI_PIO_MODE &= ~ (0x03 << (SPI1_MISO_PIN * 2));
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/* Alternate function clear */
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SPI_PIO_AFL &= ~(0xf << ((SPI1_CLOCK_PIN) * 4));
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SPI_PIO_AFL &= ~(0xf << ((SPI1_MOSI_PIN) * 4));
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SPI_PIO_AFL &= ~(0xf << ((SPI1_MISO_PIN) * 4));
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/* Floating */
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SPI_PIO_PUPD &= ~ (0x03 << (SPI1_CLOCK_PIN * 2));
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SPI_PIO_PUPD &= ~ (0x03 << (SPI1_MOSI_PIN * 2));
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SPI_PIO_PUPD &= ~ (0x03 << (SPI1_MISO_PIN * 2));
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/* Release CS */
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SPI_PIO_CS_MODE &= ~ (0x03 << (SPI_CS_FLASH * 2));
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SPI_PIO_CS_PUPD &= ~ (0x03 << (SPI_CS_TPM * 2));
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}
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static void spi1_reset(void)
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{
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APB2_CLOCK_RST |= SPI1_APB2_CLOCK_ER_VAL;
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APB2_CLOCK_RST &= ~SPI1_APB2_CLOCK_ER_VAL;
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}
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uint8_t spi_read(void)
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{
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volatile uint32_t reg;
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do {
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reg = SPI1_SR;
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} while(!(reg & SPI_SR_RX_NOTEMPTY));
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return (uint8_t)SPI1_DR;
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}
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void spi_write(const char byte)
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{
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int i;
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volatile uint32_t reg;
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do {
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reg = SPI1_SR;
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} while ((reg & SPI_SR_TX_EMPTY) == 0);
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SPI1_DR = byte;
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do {
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reg = SPI1_SR;
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} while ((reg & SPI_SR_TX_EMPTY) == 0);
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}
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void spi_init(int polarity, int phase)
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{
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static int initialized = 0;
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if (!initialized) {
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initialized++;
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spi1_pins_setup();
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spi_flash_pin_setup();
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spi_tpm2_pin_setup();
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APB2_CLOCK_ER |= SPI1_APB2_CLOCK_ER_VAL;
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spi1_reset();
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SPI1_CR1 = SPI_CR1_MASTER | (5 << 3) | (polarity << 1) | (phase << 0);
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SPI1_CR2 |= SPI_CR2_SSOE;
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SPI1_CR1 |= SPI_CR1_SPI_EN;
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}
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}
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void spi_release(void)
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{
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spi1_reset();
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SPI1_CR2 &= ~SPI_CR2_SSOE;
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SPI1_CR1 = 0;
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spi_pins_release();
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}
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@ -0,0 +1,129 @@
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#ifndef SPI_DRV_STM32_H_INCLUDED
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#define SPI_DRV_STM32_H_INCLUDED
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#include <stdint.h>
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/** SPI settings **/
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#define SPI1 (0x40013000)/* SPI1 base address */
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#define SPI1_APB2_CLOCK_ER_VAL (1 << 12)
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#define CEN_GPIOA (1 << 0)
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#define CEN_GPIOB (1 << 1)
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#define CEN_GPIOC (1 << 2)
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#define CEN_GPIOD (1 << 3)
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#define CEN_GPIOE (1 << 4)
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#ifdef PLATFORM_stm32f4
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(0x40023844))
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#define APB2_CLOCK_RST (*(volatile uint32_t *)(0x40023824))
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#define CLOCK_SPEED (168000000)
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#define RCC_GPIO_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
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#define GPIOA_BASE (0x40020000)
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#define GPIOB_BASE (0x40020400)
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#define GPIOC_BASE (0x40020800)
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#define GPIOD_BASE (0x40020C00)
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#define GPIOE_BASE (0x40021000)
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#define SPI_GPIO GPIOB_BASE
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#define SPI_CS_GPIO GPIOB_BASE
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#define SPI_PIO_BASE GPIOB_BASE
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#define SPI_CS_PIO_BASE GPIOE_BASE
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#define SPI_CS_FLASH 1 /* Flash CS connected to GPIOE1 */
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#define SPI_CS_TPM 0 /* TPM CS connected to GPIOE0 */
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#define SPI1_PIN_AF 5 /* Alternate function for SPI pins */
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#define SPI1_CLOCK_PIN 3 /* SPI_SCK: PB3 */
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#define SPI1_MISO_PIN 4 /* SPI_MISO PB4 */
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#define SPI1_MOSI_PIN 5 /* SPI_MOSI PB5 */
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#endif
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#ifdef PLATFORM_stm32wb
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(0x58000060))
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#define APB2_CLOCK_RST (*(volatile uint32_t *)(0x58000040))
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#define SPI_GPIO GPIOA_BASE
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#define RCC_GPIO_CLOCK_ER (*(volatile uint32_t *)(0x5800004C))
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#define GPIOA_BASE (0x48000000)
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#define GPIOB_BASE (0x48000400)
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#define GPIOC_BASE (0x48000800)
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#define GPIOD_BASE (0x48000C00)
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#define SPI_CS_GPIO GPIOA_BASE
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#define SPI_CS_FLASH 4 /* Flash CS connected to GPIOA4 */
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#define SPI_CS_TPM 0 /* TPM CS connected to GPIOA0 */
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#define SPI1_PIN_AF 5 /* Alternate function for SPI pins */
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#define SPI1_CLOCK_PIN 5 /* SPI_SCK: PA5 */
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#define SPI1_MISO_PIN 6 /* SPI_MISO PA6 */
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#define SPI1_MOSI_PIN 7 /* SPI_MOSI PA7 */
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#endif
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#define SPI_PIO_BASE SPI_GPIO
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#define SPI_CS_PIO_BASE SPI_CS_GPIO
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#if (SPI_GPIO == GPIOA_BASE)
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# define SPI_PIO_CEN CEN_GPIOA
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#elif (SPI_GPIO == GPIOB_BASE)
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# define SPI_PIO_CEN CEN_GPIOB
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#elif (SPI_GPIO == GPIOC_BASE)
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# define SPI_PIO_CEN CEN_GPIOC
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#elif (SPI_GPIO == GPIOD_BASE)
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# define SPI_PIO_CEN CEN_GPIOD
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#elif (SPI_GPIO == GPIOE_BASE)
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# define SPI_PIO_CEN CEN_GPIOE
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#endif
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#if (SPI_CS_GPIO == GPIOA_BASE)
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# define SPI_PIO_CS_CEN CEN_GPIOA
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#elif (SPI_CS_GPIO == GPIOB_BASE)
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# define SPI_PIO_CS_CEN CEN_GPIOB
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#elif (SPI_CS_GPIO == GPIOC_BASE)
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# define SPI_PIO_CS_CEN CEN_GPIOC
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#elif (SPI_CS_GPIO == GPIOD_BASE)
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# define SPI_PIO_CS_CEN CEN_GPIOD
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#elif (SPI_CS_GPIO == GPIOE_BASE)
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# define SPI_PIO_CS_CEN CEN_GPIOE
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#endif
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#define SPI1_CR1 (*(volatile uint32_t *)(SPI1))
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#define SPI1_CR2 (*(volatile uint32_t *)(SPI1 + 0x04))
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#define SPI1_SR (*(volatile uint32_t *)(SPI1 + 0x08))
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#define SPI1_DR (*(volatile uint32_t *)(SPI1 + 0x0c))
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#define SPI_CR1_CLOCK_PHASE (1 << 0)
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#define SPI_CR1_CLOCK_POLARITY (1 << 1)
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#define SPI_CR1_MASTER (1 << 2)
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#define SPI_CR1_BAUDRATE (0x07 << 3)
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#define SPI_CR1_SPI_EN (1 << 6)
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#define SPI_CR1_LSBFIRST (1 << 7)
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#define SPI_CR1_SSI (1 << 8)
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#define SPI_CR1_SSM (1 << 9)
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#define SPI_CR1_16BIT_FORMAT (1 << 11)
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#define SPI_CR1_TX_CRC_NEXT (1 << 12)
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#define SPI_CR1_HW_CRC_EN (1 << 13)
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#define SPI_CR1_BIDIOE (1 << 14)
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#define SPI_CR2_SSOE (1 << 2)
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#define SPI_SR_RX_NOTEMPTY (1 << 0)
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#define SPI_SR_TX_EMPTY (1 << 1)
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#define SPI_SR_BUSY (1 << 7)
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#define SPI_PIO_MODE (*(volatile uint32_t *)(SPI_PIO_BASE + 0x00))
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#define SPI_PIO_AFL (*(volatile uint32_t *)(SPI_PIO_BASE + 0x20))
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#define SPI_PIO_AFH (*(volatile uint32_t *)(SPI_PIO_BASE + 0x24))
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#define SPI_PIO_OSPD (*(volatile uint32_t *)(SPI_PIO_BASE + 0x08))
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#define SPI_PIO_PUPD (*(volatile uint32_t *)(SPI_PIO_BASE + 0x0c))
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#define SPI_PIO_BSRR (*(volatile uint32_t *)(SPI_PIO_BASE + 0x18))
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#define SPI_PIO_CS_MODE (*(volatile uint32_t *)(SPI_CS_PIO_BASE + 0x00))
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#define SPI_PIO_CS_AFL (*(volatile uint32_t *)(SPI_CS_PIO_BASE + 0x20))
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#define SPI_PIO_CS_AFH (*(volatile uint32_t *)(SPI_CS_PIO_BASE + 0x24))
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#define SPI_PIO_CS_OSPD (*(volatile uint32_t *)(SPI_CS_PIO_BASE + 0x08))
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#define SPI_PIO_CS_PUPD (*(volatile uint32_t *)(SPI_CS_PIO_BASE + 0x0c))
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#define SPI_PIO_CS_BSRR (*(volatile uint32_t *)(SPI_CS_PIO_BASE + 0x18))
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#define SPI_PIO_CS_ODR (*(volatile uint32_t *)(SPI_CS_PIO_BASE + 0x14))
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#define GPIO_MODE_AF (2)
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#endif
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@ -30,8 +30,8 @@
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#define SPI_DRV_H_INCLUDED
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#include <stdint.h>
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#ifdef PLATFORM_stm32f4
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#include "hal/spi/spi_drv_stm32f4.h"
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#if defined(PLATFORM_stm32f4) || defined(PLATFORM_stm32f7) || defined(PLATFORM_stm32wb)
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#include "hal/spi/spi_drv_stm32.h"
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#endif
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void spi_init(int polarity, int phase);
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@ -40,7 +40,7 @@ endif
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ifeq ($(SPI_FLASH),1)
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CFLAGS+=-DSPI_FLASH
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APP_OBJS+=../hal/spi/spi_drv_$(TARGET).o ../src/spi_flash.o
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APP_OBJS+=../hal/spi/spi_drv_$(SPI_TARGET).o ../src/spi_flash.o
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endif
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ifeq ($(TARGET),kinetis)
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