mirror of https://github.com/wolfSSL/wolfBoot.git
Peer review fixes
David Garske
Daniele Lacamera
parent
980022de13
commit
284a1d5eb9
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@ -18,9 +18,9 @@ V?=0
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SPMATH?=1
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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# Flash layout for dual-bank (2x512KB, 8KB pages):
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# Flash layout for dual-bank (2x512KB, 4KB pages):
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# Bank 1 (0x08000000): wolfBoot (64KB) + BOOT partition (448KB)
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# Bank 2 (0x08080000): UPDATE partition (448KB) + SWAP (8KB)
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# Bank 2 (0x08080000): UPDATE partition (448KB) + SWAP (4KB)
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# Future: DUALBANK_SWAP=1 eliminates swap and uses HW bank-swap
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WOLFBOOT_SECTOR_SIZE?=0x1000
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WOLFBOOT_PARTITION_SIZE?=0x70000
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@ -1713,8 +1713,8 @@ arm-none-eabi-gdb
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The STM32U3 family (for example the STM32U385RG on NUCLEO-U385RG-Q) is a
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Cortex-M33 part **without TrustZone**, so the port is single-image only
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(no `-tz` or `-ns` variants). 1 MB internal flash, 256 KB SRAM, 8 KB
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pages, 128-bit (quad-word) flash write quantum.
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(no `-tz` or `-ns` variants). 1 MB internal flash, 256 KB SRAM, 4 KB
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pages, 64-bit (double-word) flash write quantum.
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### Flash layout (stm32u3.config)
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@ -1764,17 +1764,11 @@ The test app blinks LD2 (PA5): slow on v1, fast on v2 (post-update).
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### Testing an Update
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Sign the test application as version 2 and write the update trigger
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magic (`pBOOT`) at the tail of the partition:
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Sign the test application as version 2, build the update image with the
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`pBOOT` trigger magic, and flash it:
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```sh
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tools/keytools/sign --ecc384 --sha384 test-app/image.bin \
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wolfboot_signing_private_key.der 2
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echo -n "pBOOT" > trigger_magic.bin
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./tools/bin-assemble/bin-assemble \
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update.bin \
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0x0 test-app/image_v2_signed.bin \
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0x6FFFB trigger_magic.bin
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./tools/scripts/prepare_update_u3.sh 2
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STM32_Programmer_CLI -c port=SWD reset=HWrst \
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-d update.bin 0x08080000 -v -rst
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```
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@ -20,7 +20,7 @@
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*/
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/* STM32U3 family (e.g. NUCLEO-U385RG-Q). Cortex-M33 without TrustZone.
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* Always dual-bank 1 MB flash (2 x 512 KB), 8 KB pages, 64-bit
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* Always dual-bank 1 MB flash (2 x 512 KB), 4 KB pages, 64-bit
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* (double-word) write quantum.
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* No traditional PLL -- MSIS switches directly between MSIRC1 (24 MHz)
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* and MSIRC0 (96 MHz).
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@ -37,8 +37,12 @@
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static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
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{
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uint32_t reg = FLASH_ACR;
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if ((reg & FLASH_ACR_LATENCY_MASK) != waitstates)
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if ((reg & FLASH_ACR_LATENCY_MASK) != waitstates) {
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FLASH_ACR = (reg & ~FLASH_ACR_LATENCY_MASK) | waitstates;
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/* RM: read-back to confirm LATENCY accepted before clock switch */
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while ((FLASH_ACR & FLASH_ACR_LATENCY_MASK) != waitstates)
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;
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}
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}
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static RAMFUNCTION void flash_wait_complete(void)
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@ -83,7 +87,9 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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/* RM step 6: write first word, then second word */
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dst[i >> 2] = dword[0];
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ISB();
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dst[(i >> 2) + 1] = dword[1];
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ISB();
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/* RM step 8: wait for BSY clear */
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flash_wait_complete();
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@ -103,15 +109,7 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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void RAMFUNCTION hal_flash_unlock(void)
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{
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flash_wait_complete();
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/* Unlock both NS and Secure flash controllers */
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if ((FLASH_NS_CR & FLASH_CR_LOCK) != 0) {
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FLASH_NS_KEYR = FLASH_KEY1;
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DMB();
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FLASH_NS_KEYR = FLASH_KEY2;
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DMB();
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while ((FLASH_NS_CR & FLASH_CR_LOCK) != 0)
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;
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}
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/* Unlock NS flash controller (TZEN=0, secure unlock not needed) */
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if ((FLASH_NS_CR & FLASH_CR_LOCK) != 0) {
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FLASH_NS_KEYR = FLASH_KEY1;
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DMB();
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@ -196,13 +194,6 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
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return 0;
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}
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static void RAMFUNCTION stm32u3_reboot(void)
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{
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AIRCR = AIRCR_SYSRESETREQ | AIRCR_VKEY;
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while (1)
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;
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}
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/* --- UART: USART1 on PA9 (TX) / PA10 (RX), AF7 --- */
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#define USART1_BASE (0x40013800U)
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@ -335,7 +326,7 @@ void hal_init(void)
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#if defined(DEBUG_UART) && defined(__WOLFBOOT)
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uart_init();
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uart_write("wolfBoot HAL Init\n", 18);
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uart_write("wolfBoot HAL Init\n", sizeof("wolfBoot HAL Init\n") - 1);
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#endif
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}
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@ -360,9 +351,8 @@ void RAMFUNCTION hal_cache_invalidate(void)
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return;
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if ((ICACHE_SR & ICACHE_SR_BUSYF) == 0)
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ICACHE_CR |= ICACHE_CR_CACHEINV;
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if (ICACHE_SR & ICACHE_SR_BUSYF) {
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while ((ICACHE_SR & ICACHE_SR_BSYENDF) == 0)
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;
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}
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/* Wait unconditionally for invalidation to complete */
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while ((ICACHE_SR & ICACHE_SR_BSYENDF) == 0)
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;
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ICACHE_SR |= ICACHE_SR_BSYENDF;
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}
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@ -20,7 +20,7 @@
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*/
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/* STM32U3 family (e.g. STM32U385RG on NUCLEO-U385RG-Q).
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* Cortex-M33, no TrustZone. 1 MB dual-bank flash (2 × 512 KB, 8 KB pages).
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* Cortex-M33, no TrustZone. 1 MB dual-bank flash (2 × 512 KB, 4 KB pages).
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* Reference: RM0487, stm32u385xx.h from STM32Cube_FW_U3_V1.3.0.
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*
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* Peripheral base addresses differ from STM32U5:
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@ -66,7 +66,7 @@
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#define RCC_ICSCR1_MSISDIV_2 (1) /* /2 */
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#define RCC_ICSCR1_MSISDIV_4 (2) /* /4 */
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#define RCC_ICSCR1_MSISDIV_8 (3) /* /8 */
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/* MSIS RC source: bit 31 MSISSEL — 0 = MSIRC1 (24 MHz), 1 = MSIRC0 (96 MHz) */
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/* MSIS RC source: bit 31 MSISSEL — 0 = MSIRC0 (96 MHz), 1 = MSIRC1 (24 MHz) */
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#define RCC_ICSCR1_MSISSEL (1u << 31)
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#define RCC_CFGR1 (*(volatile uint32_t *)(RCC_BASE + 0x1C))
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@ -130,7 +130,7 @@
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#define FLASH_NS_SR (*(volatile uint32_t *)(FLASH_BASE + 0x20))
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#define FLASH_NS_CR (*(volatile uint32_t *)(FLASH_BASE + 0x28))
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/* Secure flash registers — required for erase/write even with TZEN=0 */
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/* Secure flash registers (unused when TZEN=0, kept for reference) */
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#define FLASH_SKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x0C))
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#define FLASH_SSR (*(volatile uint32_t *)(FLASH_BASE + 0x24))
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#define FLASH_SCR (*(volatile uint32_t *)(FLASH_BASE + 0x2C))
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@ -83,7 +83,10 @@ static void busy_delay(uint32_t count)
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void main(void)
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{
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uint32_t version;
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uint32_t v;
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uint32_t on_ticks, off_ticks;
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char num[4];
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int idx = 0;
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hal_init();
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led_init();
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@ -93,12 +96,14 @@ void main(void)
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version = wolfBoot_current_firmware_version();
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{
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char v = '0' + (char)(version & 0x7F);
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char msg[] = "App version: X\r\n";
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msg[13] = v;
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uart_write(msg, sizeof(msg) - 1);
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}
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v = version;
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if (v >= 100) { num[idx++] = '0' + (v / 100); v %= 100; }
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if (v >= 10 || idx > 0) { num[idx++] = '0' + (v / 10); v %= 10; }
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num[idx++] = '0' + v;
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num[idx] = '\0';
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uart_write("App version: ", sizeof("App version: ") - 1);
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uart_write(num, idx);
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uart_write("\r\n", 2);
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/* v1: slow blink. v2+: fast blink. */
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if (version >= 2) {
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