From 28e29cb20b5888ea9e3f67eab7e6bfdc2df6bdde Mon Sep 17 00:00:00 2001
From: Daniele Lacamera <dan@danielinux.net>
Date: Wed, 20 May 2020 12:19:16 +0200
Subject: [PATCH] Don't update clock settings before staging.

(mentioned in docs/Targets.md)
---
 docs/Targets.md | 5 +++++
 hal/psoc6.c     | 1 -
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/docs/Targets.md b/docs/Targets.md
index 845b55bb..5cc24681 100644
--- a/docs/Targets.md
+++ b/docs/Targets.md
@@ -573,6 +573,11 @@ wolfBoot uses the following components to access peripherals on the PSoC:
 Cypress provides a [customized OpenOCD](https://github.com/cypresssemiconductorco/Openocd) for programming the flash and
 debugging.
 
+
+### Clock settings
+
+wolfBoot configures PLL1 to run at 100 MHz and is driving `CLK_FAST`, `CLK_PERI`, and `CLK_SLOW` at that frequency.
+
 #### Build configuration
 
 The following configuration has been tested on the PSoC CY8CKIT-62S2-43012:
diff --git a/hal/psoc6.c b/hal/psoc6.c
index 81265c1b..2299cb38 100644
--- a/hal/psoc6.c
+++ b/hal/psoc6.c
@@ -98,7 +98,6 @@ void hal_init(void)
 
 void hal_prepare_boot(void)
 {
-    /* TODO: how to restore boot-default clock speed? */
 }
 
 #endif