max32666: fix boot-time CPU and cache configuration

Discovered while working on custom board, but generic to MAX32666. All
three reproduce behavior the MSDK adopts by default.

- Set VTOR to wolfBoot's vector table. The boot ROM leaves VTOR pointing
  to 0, and flash is not aliased at address 0, so any fault while
  wolfBoot runs was handled by the ROM's handlers instead of wolfBoot's.

- Wait for the ICC invalidation to complete before setting the enable
  bit. The cache was previously enabled while the invalidation was still
  in progress (taken from MSDK).

- Disable the ICC read buffer through the TME registers.

hal/max32666.c

@@ -105,8 +105,9 @@ static void RAMFUNCTION icc_disable(void)
 
 static void RAMFUNCTION icc_enable(void)
 {
-    /* Invalidate and re-enable cache */
+    /* Invalidate cache, wait for completion, then re-enable */
     ICC0_INVALIDATE = 1;
+    while (!(ICC0_CTRL & ICC_CTRL_RDY)) {}
     ICC0_CTRL |= ICC_CTRL_EN;
     while (!(ICC0_CTRL & ICC_CTRL_RDY)) {}
 }
@@ -325,6 +326,14 @@ void hal_init(void)
     FLC0_CLKDIV = FLC_CLKDIV_VALUE;
     FLC1_CLKDIV = FLC_CLKDIV_VALUE;
 
+    /* Point VTOR at our vector table so faults hit our handlers */
+    *(volatile uint32_t *)0xE000ED08 = 0x10000000;
+
+    /* Disable the ICC read buffer via TME before enabling the cache */
+    TME_CTRL = 1;
+    SIR_TRIM_ICC = SIR_TRIM_ICC_RB_DIS;
+    TME_CTRL = 0;
+
     /* Enable instruction cache */
     icc_enable();
 

hal/max32666.h

@@ -170,6 +170,11 @@
 #define ICC_CTRL_EN             (1UL << 0)          /* Cache enable */
 #define ICC_CTRL_RDY            (1UL << 16)         /* Cache ready */
 
+/* Test mode / trim registers */
+#define TME_CTRL                (*(volatile uint32_t *)0x40000C00UL)
+#define SIR_TRIM_ICC            (*(volatile uint32_t *)0x4000040CUL)
+#define SIR_TRIM_ICC_RB_DIS     (1UL << 6)          /* Read buffer disable */
+
 /* ============== WDT - Watchdog Timer ============== */
 /* MSDK: wdt_regs.h */
 #define WDT0_BASE               0x40003000UL