From 322d1b3a36e6cc74ea735ea6990e960034c7159c Mon Sep 17 00:00:00 2001 From: David Garske Date: Fri, 29 Sep 2023 15:12:30 -0700 Subject: [PATCH] Refactor DDR law setup for use with stage 2 as stack. --- config/examples/nxp-t2080.config | 1 - hal/nxp_p1021.c | 115 ++++++++++++++----------------- hal/nxp_ppc.h | 11 ++- hal/nxp_t1024.c | 36 ++-------- hal/nxp_t1024.ld | 16 ++--- hal/nxp_t1024_stage1.ld | 9 +-- hal/nxp_t2080.c | 30 ++------ src/boot_ppc.c | 18 +++++ src/boot_ppc_start.S | 29 ++++---- src/update_ram.c | 23 +++++-- 10 files changed, 137 insertions(+), 151 deletions(-) diff --git a/config/examples/nxp-t2080.config b/config/examples/nxp-t2080.config index fb12a390..190b99bd 100644 --- a/config/examples/nxp-t2080.config +++ b/config/examples/nxp-t2080.config @@ -14,7 +14,6 @@ UART_FLASH?=0 ALLOW_DOWNGRADE?=0 NVM_FLASH_WRITEONCE?=0 WOLFBOOT_VERSION?=0 -V?=1 NO_MPU?=0 SPMATH?=0 SPMATHALL?=1 diff --git a/hal/nxp_p1021.c b/hal/nxp_p1021.c index d9709628..7796a30a 100644 --- a/hal/nxp_p1021.c +++ b/hal/nxp_p1021.c @@ -348,7 +348,6 @@ enum elbc_amask_sizes { /* DDR */ /* DDR3: 512MB, 333.333 MHz (666.667 MT/s) */ -#define DDR_SIZE (512 * 1024 * 1024) #define DDR_CS0_BNDS_VAL 0x0000001F #define DDR_CS0_CONFIG_VAL 0x80014202 #define DDR_CS_CONFIG_2_VAL 0x00000000 @@ -633,18 +632,6 @@ void hal_espi_deinit(void) } #endif /* ENABLE_ESPI */ - -static void set_law(uint8_t idx, uint32_t addr, uint32_t trgt_id, - uint32_t law_sz) -{ - set32(LAWAR(idx), 0); /* reset */ - set32(LAWBAR(idx), addr >> 12); - set32(LAWAR(idx), LAWAR_ENABLE | LAWAR_TRGT_ID(trgt_id) | law_sz); - - /* Read back so that we sync the writes */ - (void)get32(LAWAR(idx)); -} - /* ---- DUART Driver ---- */ #ifdef DEBUG_UART @@ -841,7 +828,7 @@ static int hal_flash_init(void) uint32_t flash_id[1] = {0}; /* eLBC - NAND Flash */ - set_law(4, FLASH_BASE_ADDR, LAW_TRGT_ELBC, LAW_SIZE_1MB); + set_law(4, 0, FLASH_BASE_ADDR, LAW_TRGT_ELBC, LAW_SIZE_1MB, 1); #ifdef BOOT_ROM_ADDR /* if this code is executing from BOOT ROM we cannot init eLBC yet */ @@ -904,62 +891,64 @@ static void hal_ddr_init(void) #ifdef ENABLE_DDR uint32_t reg; + /* Map LAW for DDR */ + set_law(6, 0, DDR_ADDRESS, LAW_TRGT_DDR, LAW_SIZE_512MB, 0); + /* If DDR is not already enabled */ - if ((get32(DDR_SDRAM_CFG) & DDR_SDRAM_CFG_MEM_EN) == 0) { - /* Map LAW for DDR */ - set_law(6, DDR_ADDRESS, LAW_TRGT_DDR, LAW_SIZE_512MB); + if ((get32(DDR_SDRAM_CFG) & DDR_SDRAM_CFG_MEM_EN)) { + return; + } - /* Setup DDR CS (chip select) bounds */ - set32(DDR_CS_BNDS(0), DDR_CS0_BNDS_VAL); - set32(DDR_CS_CONFIG(0), DDR_CS0_CONFIG_VAL); - set32(DDR_CS_CONFIG_2(0), DDR_CS_CONFIG_2_VAL); + /* Setup DDR CS (chip select) bounds */ + set32(DDR_CS_BNDS(0), DDR_CS0_BNDS_VAL); + set32(DDR_CS_CONFIG(0), DDR_CS0_CONFIG_VAL); + set32(DDR_CS_CONFIG_2(0), DDR_CS_CONFIG_2_VAL); - /* DDR SDRAM timing configuration */ - set32(DDR_TIMING_CFG_3, DDR_TIMING_CFG_3_VAL); - set32(DDR_TIMING_CFG_0, DDR_TIMING_CFG_0_VAL); - set32(DDR_TIMING_CFG_1, DDR_TIMING_CFG_1_VAL); - set32(DDR_TIMING_CFG_2, DDR_TIMING_CFG_2_VAL); + /* DDR SDRAM timing configuration */ + set32(DDR_TIMING_CFG_3, DDR_TIMING_CFG_3_VAL); + set32(DDR_TIMING_CFG_0, DDR_TIMING_CFG_0_VAL); + set32(DDR_TIMING_CFG_1, DDR_TIMING_CFG_1_VAL); + set32(DDR_TIMING_CFG_2, DDR_TIMING_CFG_2_VAL); - set32(DDR_SDRAM_MODE, DDR_SDRAM_MODE_VAL); - set32(DDR_SDRAM_MODE_2, DDR_SDRAM_MODE_2_VAL); - set32(DDR_SDRAM_MD_CNTL, DDR_SDRAM_MD_CNTL_VAL); - set32(DDR_SDRAM_INTERVAL, DDR_SDRAM_INTERVAL_VAL); - set32(DDR_DATA_INIT, DDR_DATA_INIT_VAL); - set32(DDR_SDRAM_CLK_CNTL, DDR_SDRAM_CLK_CNTL_VAL); - set32(DDR_TIMING_CFG_4, DDR_TIMING_CFG_4_VAL); - set32(DDR_TIMING_CFG_5, DDR_TIMING_CFG_5_VAL); - set32(DDR_ZQ_CNTL, DDR_ZQ_CNTL_VAL); - set32(DDR_WRLVL_CNTL, DDR_WRLVL_CNTL_VAL); + set32(DDR_SDRAM_MODE, DDR_SDRAM_MODE_VAL); + set32(DDR_SDRAM_MODE_2, DDR_SDRAM_MODE_2_VAL); + set32(DDR_SDRAM_MD_CNTL, DDR_SDRAM_MD_CNTL_VAL); + set32(DDR_SDRAM_INTERVAL, DDR_SDRAM_INTERVAL_VAL); + set32(DDR_DATA_INIT, DDR_DATA_INIT_VAL); + set32(DDR_SDRAM_CLK_CNTL, DDR_SDRAM_CLK_CNTL_VAL); + set32(DDR_TIMING_CFG_4, DDR_TIMING_CFG_4_VAL); + set32(DDR_TIMING_CFG_5, DDR_TIMING_CFG_5_VAL); + set32(DDR_ZQ_CNTL, DDR_ZQ_CNTL_VAL); + set32(DDR_WRLVL_CNTL, DDR_WRLVL_CNTL_VAL); - set32(DDR_SR_CNTR, 0); - set32(DDR_SDRAM_RCW_1, 0); - set32(DDR_SDRAM_RCW_2, 0); + set32(DDR_SR_CNTR, 0); + set32(DDR_SDRAM_RCW_1, 0); + set32(DDR_SDRAM_RCW_2, 0); - set32(DDR_DDRCDR_1, DDR_DDRCDR_1_VAL); + set32(DDR_DDRCDR_1, DDR_DDRCDR_1_VAL); - set32(DDR_SDRAM_CFG_2, DDR_SDRAM_CFG_2_VAL); - set32(DDR_INIT_ADDR, 0); - set32(DDR_INIT_EXT_ADDR, 0); - set32(DDR_DDRCDR_2, DDR_DDRCDR_2_VAL); + set32(DDR_SDRAM_CFG_2, DDR_SDRAM_CFG_2_VAL); + set32(DDR_INIT_ADDR, 0); + set32(DDR_INIT_EXT_ADDR, 0); + set32(DDR_DDRCDR_2, DDR_DDRCDR_2_VAL); - /* Set values, but do not enable the DDR yet */ - set32(DDR_SDRAM_CFG, ((DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN))); - asm volatile("sync;isync"); + /* Set values, but do not enable the DDR yet */ + set32(DDR_SDRAM_CFG, ((DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN))); + asm volatile("sync;isync"); - /* busy wait for ~500us */ - udelay(500); + /* busy wait for ~500us */ + udelay(500); - /* Enable controller */ - reg = get32(DDR_SDRAM_CFG) & ~DDR_SDRAM_CFG_BI; - set32(DDR_SDRAM_CFG, reg | DDR_SDRAM_CFG_MEM_EN); - asm volatile("sync;isync"); + /* Enable controller */ + reg = get32(DDR_SDRAM_CFG) & ~DDR_SDRAM_CFG_BI; + set32(DDR_SDRAM_CFG, reg | DDR_SDRAM_CFG_MEM_EN); + asm volatile("sync;isync"); - /* Wait for data initialization to complete */ - while (get32(DDR_SDRAM_CFG_2) & DDR_SDRAM_CFG_2_D_INIT) { - /* busy wait loop - throttle polling */ - udelay(1); - } + /* Wait for data initialization to complete */ + while (get32(DDR_SDRAM_CFG_2) & DDR_SDRAM_CFG_2_D_INIT) { + /* busy wait loop - throttle polling */ + udelay(1); } #endif /* ENABLE_DDR */ } @@ -983,10 +972,10 @@ void hal_early_init(void) static int hal_pcie_init(void) { /* Map LAW for PCIe */ - set_law(0, CONFIG_SYS_PCIE1_MEM_PHYS, LAW_TRGT_PCIE1, LAW_SIZE_512MB), - set_law(1, CONFIG_SYS_PCIE1_IO_PHYS, LAW_TRGT_PCIE1, LAW_SIZE_64KB), - set_law(2, CONFIG_SYS_PCIE2_MEM_PHYS, LAW_TRGT_PCIE2, LAW_SIZE_512MB), - set_law(3, CONFIG_SYS_PCIE2_IO_PHYS, LAW_TRGT_PCIE2, LAW_SIZE_64KB), + set_law(0, 0, CONFIG_SYS_PCIE1_MEM_PHYS, LAW_TRGT_PCIE1, LAW_SIZE_512MB, 1), + set_law(1, 0, CONFIG_SYS_PCIE1_IO_PHYS, LAW_TRGT_PCIE1, LAW_SIZE_64KB, 1), + set_law(2, 0, CONFIG_SYS_PCIE2_MEM_PHYS, LAW_TRGT_PCIE2, LAW_SIZE_512MB, 1), + set_law(3, 0, CONFIG_SYS_PCIE2_IO_PHYS, LAW_TRGT_PCIE2, LAW_SIZE_64KB, 1), /* Map TLB for PCIe */ set_tlb(1, 2, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, 0, @@ -1011,7 +1000,7 @@ static int hal_pcie_init(void) static int hal_cpld_init(void) { /* Setup Local Access Window (LAW) for CPLD/BCSR */ - set_law(5, BCSR_BASE, LAW_TRGT_ELBC, LAW_SIZE_256KB); + set_law(5, 0, BCSR_BASE, LAW_TRGT_ELBC, LAW_SIZE_256KB, 1); /* Setup TLB MMU (Translation Lookaside Buffer) for CPLD/BCSR */ set_tlb(1, 8, BCSR_BASE, BCSR_BASE, 0, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256K, 1); diff --git a/hal/nxp_ppc.h b/hal/nxp_ppc.h index 76f9743f..15f756d3 100644 --- a/hal/nxp_ppc.h +++ b/hal/nxp_ppc.h @@ -32,6 +32,7 @@ #define CCSRBAR_SIZE BOOKE_PAGESZ_1M #define ENABLE_DDR + #define DDR_SIZE (512 * 1024 * 1024) /* Memory used for transferring blocks to/from NAND. * Maps to eLBC FCM internal 8KB region (by hardware) */ @@ -85,6 +86,7 @@ #endif #define ENABLE_DDR + #define DDR_SIZE (2048ULL * 1024ULL * 1024ULL) #define FLASH_BASE_ADDR 0xEC000000 #define FLASH_BASE_PHYS_HIGH 0xFULL @@ -120,6 +122,7 @@ #define ENABLE_INTERRUPTS #define ENABLE_DDR + #define DDR_SIZE (8192 * 1024 * 1024) #define FLASH_BASE_ADDR 0xE8000000 #define FLASH_BASE_PHYS_HIGH 0x0ULL @@ -300,9 +303,9 @@ /* T1024/T2080 LAW - Local Access Window (Memory Map) - RM 2.4 */ #define LAWBAR_BASE(n) (0xC00 + (n * 0x10)) - #define LAWBARH(n) *((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x0)) - #define LAWBARL(n) *((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x4)) - #define LAWAR(n) *((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x8)) + #define LAWBARH(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x0)) + #define LAWBARL(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x4)) + #define LAWAR(n) ((volatile uint32_t*)(CCSRBAR + LAWBAR_BASE(n) + 0x8)) #define LAWAR_ENABLE (1<<31) #define LAWAR_TRGT_ID(id) (id<<20) @@ -623,6 +626,8 @@ extern void set_tlb(uint8_t tlb, uint8_t esel, uint32_t epn, uint32_t rpn, uint8_t iprot); extern void disable_tlb1(uint8_t esel); extern void flush_cache(uint32_t start_addr, uint32_t size); +extern void set_law(uint8_t idx, uint32_t addr_h, uint32_t addr_l, + uint32_t trgt_id, uint32_t law_sz, int reset); /* from hal/nxp_*.c */ extern void uart_init(void); diff --git a/hal/nxp_t1024.c b/hal/nxp_t1024.c index 9c430eb6..95e7f2d5 100644 --- a/hal/nxp_t1024.c +++ b/hal/nxp_t1024.c @@ -419,8 +419,6 @@ enum ifc_amask_sizes { /* DDR4 - 2GB */ /* 1600 MT/s (64-bit, CL=12, ECC on) */ -#define DDR_SIZE (2048ULL * 1024ULL * 1024ULL) - #define DDR_CS0_BNDS_VAL 0x0000007F #define DDR_CS1_BNDS_VAL 0x008000BF #define DDR_CS2_BNDS_VAL 0x0100013F @@ -612,22 +610,10 @@ static void udelay(uint32_t delay_us) wait_ticks(delay_us * DELAY_US); } -static void set_law(uint8_t idx, uint32_t addr_h, uint32_t addr_l, - uint32_t trgt_id, uint32_t law_sz) -{ - LAWAR(idx) = 0; /* reset */ - LAWBARH(idx) = addr_h; - LAWBARL(idx) = addr_l; - LAWAR(idx) = (LAWAR_ENABLE | LAWAR_TRGT_ID(trgt_id) | law_sz); - - /* Read back so that we sync the writes */ - (void)LAWAR(idx); -} - static void law_init(void) { /* Buffer Manager (BMan) (control) - probably not required */ - set_law(3, 0xF, 0xF4000000, LAW_TRGT_BMAN, LAW_SIZE_32MB); + set_law(3, 0xF, 0xF4000000, LAW_TRGT_BMAN, LAW_SIZE_32MB, 1); } @@ -876,14 +862,14 @@ static void hal_ddr_init(void) #ifdef ENABLE_DDR uint32_t reg; + /* Map LAW for DDR */ + set_law(15, 0, DDR_ADDRESS, LAW_TRGT_DDR_1, LAW_SIZE_2GB, 0); + /* If DDR is already enabled then just return */ - if (get32(DDR_SDRAM_CFG) & DDR_SDRAM_CFG_MEM_EN) { + if ((get32(DDR_SDRAM_CFG) & DDR_SDRAM_CFG_MEM_EN)) { return; } - /* Map LAW for DDR */ - set_law(15, 0, DDR_ADDRESS, LAW_TRGT_DDR_1, LAW_SIZE_2GB); - /* Set early for clock / pin */ set32(DDR_SDRAM_CLK_CNTL, DDR_SDRAM_CLK_CNTL_VAL); @@ -945,7 +931,7 @@ static void hal_ddr_init(void) set32(DDR_SDRAM_RCW_5, 0); set32(DDR_SDRAM_RCW_6, 0); set32(DDR_DDRCDR_1, DDR_DDRCDR_1_VAL); - set32(DDR_SDRAM_CFG_2, DDR_SDRAM_CFG_2_VAL); + set32(DDR_SDRAM_CFG_2, (DDR_SDRAM_CFG_2_VAL | DDR_SDRAM_CFG_2_D_INIT)); set32(DDR_INIT_ADDR, 0); set32(DDR_INIT_EXT_ADDR, 0); set32(DDR_DDRCDR_2, DDR_DDRCDR_2_VAL); @@ -1001,14 +987,6 @@ static void hal_ddr_init(void) /* Errata A-009663 - Write real precharge interval */ set32(DDR_SDRAM_INTERVAL, DDR_SDRAM_INTERVAL_VAL); #endif - - /* DDR - TBL=1, Entry 12/13 */ - set_tlb(1, 12, DDR_ADDRESS, DDR_ADDRESS, 0, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, - 0, BOOKE_PAGESZ_1G, 1); - set_tlb(1, 13, DDR_ADDRESS + 0x40000000, DDR_ADDRESS + 0x40000000, 0, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, - 0, BOOKE_PAGESZ_1G, 1); #endif } @@ -1067,7 +1045,7 @@ static void hal_cpld_init(void) /* IFC - CPLD */ set_law(2, CPLD_BASE_PHYS_HIGH, CPLD_BASE, - LAW_TRGT_IFC, LAW_SIZE_4KB); + LAW_TRGT_IFC, LAW_SIZE_4KB, 1); /* CPLD - TBL=1, Entry 11 */ set_tlb(1, 11, CPLD_BASE, CPLD_BASE, CPLD_BASE_PHYS_HIGH, diff --git a/hal/nxp_t1024.ld b/hal/nxp_t1024.ld index 36fc9ea8..06baab81 100644 --- a/hal/nxp_t1024.ld +++ b/hal/nxp_t1024.ld @@ -2,9 +2,6 @@ OUTPUT_ARCH( "powerpc" ) ENTRY( _reset ) -HEAP_SIZE = 4K; /* heap not used */ -STACK_SIZE = 128K; - MEMORY { /* DDR4 - 2GB (offset by destination address and 4KB boot region) */ @@ -14,8 +11,8 @@ MEMORY /* L1 SRAM - 16KB */ L1RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 0x4000 - /* L2 SRAM - 160KB */ - L2RAM (rwx) : ORIGIN = 0xFDFC0000, LENGTH = 0x28000 + /* Platform SRAM - 160KB */ + PSRAM (rwx) : ORIGIN = 0xFDFC0000, LENGTH = 0x28000 } SECTIONS @@ -82,9 +79,10 @@ SECTIONS } +/* DDR heap/stack */ PROVIDE(_start_heap = _end); +PROVIDE(_end_stack = ORIGIN(DRAM) + (LENGTH(DRAM))); -/* If relocated to DDR already then use stack end from DDR */ -/* If debugging and DDR is not ready, use L1 or L2 */ -PROVIDE(_end_stack = _end + HEAP_SIZE + STACK_SIZE ); -/* PROVIDE(_end_stack = ORIGIN(L2RAM) + (LENGTH(L2RAM)) ); */ +/* Platform SRAM heap/stack */ +/* PROVIDE(_start_heap = ORIGIN(PSRAM)); */ +/* PROVIDE(_end_stack = ORIGIN(PSRAM) + (LENGTH(PSRAM))); */ diff --git a/hal/nxp_t1024_stage1.ld b/hal/nxp_t1024_stage1.ld index 5a03c142..49f39bb1 100644 --- a/hal/nxp_t1024_stage1.ld +++ b/hal/nxp_t1024_stage1.ld @@ -21,8 +21,8 @@ MEMORY /* L1 SRAM - 16KB */ L1RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 0x4000 - /* L2 SRAM - 160KB */ - L2RAM (rwx) : ORIGIN = 0xFDFC0000, LENGTH = 0x28000 + /* Platform SRAM - 160KB */ + PSRAM (rwx) : ORIGIN = 0xFDFC0000, LENGTH = 0x28000 /* DDR - 2GB: Start at 16MB to avoid using 0x0 (NULL) addresses */ DRAM (rwx) : ORIGIN = 0x1000000, LENGTH = 0x7FFFFFFF - 0x1000000 @@ -105,5 +105,6 @@ SECTIONS } -PROVIDE(_start_heap = ORIGIN(L2RAM)); -PROVIDE(_end_stack = ORIGIN(L2RAM) + (LENGTH(L2RAM)) ); +/* Platform SRAM heap/stack */ +PROVIDE(_start_heap = ORIGIN(PSRAM)); +PROVIDE(_end_stack = ORIGIN(PSRAM) + (LENGTH(PSRAM))); diff --git a/hal/nxp_t2080.c b/hal/nxp_t2080.c index 0c3b6ccc..dc344474 100644 --- a/hal/nxp_t2080.c +++ b/hal/nxp_t2080.c @@ -176,7 +176,6 @@ enum ifc_amask_sizes { /* DDR */ /* NAII 68PPC2 - 8GB discrete DDR3 IM8G08D3EBDG-15E */ /* 1333.333 MT/s data rate 8 GiB (DDR3, 64-bit, CL=9, ECC on) */ -#define DDR_SIZE (8192 * 1024 * 1024) #define DDR_N_RANKS 2 #define DDR_RANK_DENS 0x100000000 #define DDR_SDRAM_WIDTH 64 @@ -339,29 +338,17 @@ void uart_write(const char* buf, uint32_t sz) } #endif /* DEBUG_UART */ -static void set_law(uint8_t idx, uint32_t addr_h, uint32_t addr_l, - uint32_t trgt_id, uint32_t law_sz) -{ - LAWAR(idx) = 0; /* reset */ - LAWBARH(idx) = addr_h; - LAWBARL(idx) = addr_l; - LAWAR(idx) = (LAWAR_ENABLE | LAWAR_TRGT_ID(trgt_id) | law_sz); - - /* Read back so that we sync the writes */ - (void)LAWAR(idx); -} - void law_init(void) { /* Buffer Manager (BMan) (control) - probably not required */ - set_law(3, 0xF, 0xF4000000, LAW_TRGT_BMAN, LAW_SIZE_32MB); + set_law(3, 0xF, 0xF4000000, LAW_TRGT_BMAN, LAW_SIZE_32MB, 1); } static void hal_flash_init(void) { /* IFC - NOR Flash */ /* LAW is also set in boot_ppc_start.S:flash_law */ - set_law(1, FLASH_BASE_PHYS_HIGH, FLASH_BASE, LAW_TRGT_IFC, LAW_SIZE_128MB); + set_law(1, FLASH_BASE_PHYS_HIGH, FLASH_BASE, LAW_TRGT_IFC, LAW_SIZE_128MB, 1); /* NOR IFC Flash Timing Parameters */ IFC_FTIM0(0) = (IFC_FTIM0_NOR_TACSE(4) | \ @@ -388,6 +375,9 @@ static void hal_flash_init(void) static void hal_ddr_init(void) { #ifdef ENABLE_DDR + /* Map LAW for DDR */ + set_law(4, 0, 0, LAW_TRGT_DDR_1, LAW_SIZE_2GB, 0); + /* If DDR is already enabled then just return */ if (DDR_SDRAM_CFG & DDR_SDRAM_CFG_MEM_EN) { return; @@ -455,16 +445,8 @@ static void hal_ddr_init(void) DDR_SDRAM_CFG |= DDR_SDRAM_CFG_MEM_EN; asm volatile("sync;isync"); - /* Map LAW for DDR */ - set_law(4, 0, 0, LAW_TRGT_DDR_1, LAW_SIZE_2GB); - /* Wait for data initialization is complete */ while ((DDR_SDRAM_CFG_2 & DDR_SDRAM_CFG_2_D_INIT)); - - /* DDR - TBL=1, Entry 19 */ - set_tlb(1, 19, DDR_ADDRESS, DDR_ADDRESS, 0, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, BOOKE_PAGESZ_2G, 1); #endif } @@ -498,7 +480,7 @@ static void hal_cpld_init(void) /* IFC - CPLD */ set_law(2, CPLD_BASE_PHYS_HIGH, CPLD_BASE, - LAW_TRGT_IFC, LAW_SIZE_4KB); + LAW_TRGT_IFC, LAW_SIZE_4KB, 1); /* CPLD - TBL=1, Entry 17 */ set_tlb(1, 17, CPLD_BASE, CPLD_BASE, CPLD_BASE_PHYS_HIGH, diff --git a/src/boot_ppc.c b/src/boot_ppc.c index f965a842..6440daf8 100644 --- a/src/boot_ppc.c +++ b/src/boot_ppc.c @@ -82,6 +82,24 @@ void invalidate_tlb(int tlb) mtspr(MMUCSR0, 0x2); } +void set_law(uint8_t idx, uint32_t addr_h, uint32_t addr_l, uint32_t trgt_id, + uint32_t law_sz, int reset) +{ + if (reset) + set32(LAWAR(idx), 0); /* reset */ + #ifdef CORE_E500 + (void)addr_h; /* not used */ + set32(LAWBAR(idx), addr_l >> 12); + #else + set32(LAWBARH(idx), addr_h); + set32(LAWBARL(idx), addr_l); + #endif + set32(LAWAR(idx), LAWAR_ENABLE | LAWAR_TRGT_ID(trgt_id) | law_sz); + + /* Read back so that we sync the writes */ + (void)get32(LAWAR(idx)); +} + void __attribute((weak)) hal_early_init(void) { diff --git a/src/boot_ppc_start.S b/src/boot_ppc_start.S index 74a7ea5e..9ce6f2e4 100644 --- a/src/boot_ppc_start.S +++ b/src/boot_ppc_start.S @@ -479,8 +479,9 @@ flash_tlb: #endif /* CORE_E5500 || CORE_E6500 */ #endif /* FLASH_BASE_ADDR */ -/* Enable use of the DDR if available (like 2nd stage) */ -#if defined(CORE_E500) && defined(ENABLE_DDR) +/* Enable use of the DDR (like 2nd stage) so it can be used for stack */ +#ifdef ENABLE_DDR + #ifdef CORE_E500 #ifdef BUILD_LOADER_STAGE1 /* use cache inhibited for first stage loader to avoid * L1 cache as SRAM issues */ @@ -488,17 +489,21 @@ flash_tlb: #else #define DDR_WING (MAS2_G) #endif + #else + #define DDR_WING (MAS2_M) + #endif - /* DDR - TBL=1, Entry 11 and 12, Super X/R/W, IG, TS=0, 512MB */ - set_tlb(1, 11, - DDR_ADDRESS, DDR_ADDRESS, 0, - MAS3_SX | MAS3_SW | MAS3_SR, DDR_WING, 0, - BOOKE_PAGESZ_256M, 0, r3); - set_tlb(1, 12, - DDR_ADDRESS + (256*1024*1024), DDR_ADDRESS + (256*1024*1024), 0, - MAS3_SX | MAS3_SW | MAS3_SR, DDR_WING, 0, - BOOKE_PAGESZ_256M, 0, r3); -#endif /* CORE_E500 && ENABLE_DDR */ + /* Map initial DDR, but can be adjusted later in hal_ddr_init() */ + /* DDR - TBL=1, Entry 12/13 */ + set_tlb(1, 12, DDR_ADDRESS, DDR_ADDRESS, 0, + MAS3_SX | MAS3_SW | MAS3_SR, DDR_WING, + 0, BOOKE_PAGESZ_1G, 1, r3); + #if DDR_SIZE > 0x40000000 + set_tlb(1, 13, DDR_ADDRESS + 0x40000000, DDR_ADDRESS + 0x40000000, 0, + MAS3_SX | MAS3_SW | MAS3_SR, DDR_WING, + 0, BOOKE_PAGESZ_1G, 1, r3); + #endif +#endif /* ENABLE_DDR */ #ifdef INITIAL_SRAM_ADDR init_sram_law: diff --git a/src/update_ram.c b/src/update_ram.c index 0b984332..a8fe2649 100644 --- a/src/update_ram.c +++ b/src/update_ram.c @@ -48,6 +48,17 @@ extern uint32_t dts_load_addr; #endif #ifdef WOLFBOOT_USE_RAMBOOT +/* requires/assumes inputs and size to be 4-byte aligned */ +static void memcpy32(void *dst, const void *src, size_t n) +{ + size_t i; + const uint32_t *s = (const uint32_t*)src; + uint32_t *d = (uint32_t*)dst; + for (i = 0; i < n/4; i++) { + d[i] = s[i]; + } +} + /* Function to load image from flash to ram */ int wolfBoot_ramboot(struct wolfBoot_image *img, uint8_t *src, uint8_t *dst) { @@ -55,8 +66,8 @@ int wolfBoot_ramboot(struct wolfBoot_image *img, uint8_t *src, uint8_t *dst) uint32_t img_size; /* read header into RAM */ - wolfBoot_printf("Loading header %d bytes to %p\n", - IMAGE_HEADER_SIZE, dst); + wolfBoot_printf("Loading header %d bytes from %p to %p\n", + IMAGE_HEADER_SIZE, src, dst); #if defined(EXT_FLASH) && defined(NO_XIP) ret = ext_flash_read((uintptr_t)src, dst, IMAGE_HEADER_SIZE); if (ret != IMAGE_HEADER_SIZE){ @@ -64,7 +75,7 @@ int wolfBoot_ramboot(struct wolfBoot_image *img, uint8_t *src, uint8_t *dst) return -1; } #else - memcpy(dst, src, IMAGE_HEADER_SIZE); + memcpy32(dst, src, IMAGE_HEADER_SIZE); #endif /* check for valid header and version */ @@ -78,8 +89,8 @@ int wolfBoot_ramboot(struct wolfBoot_image *img, uint8_t *src, uint8_t *dst) img_size = wolfBoot_image_size((uint8_t*)dst); /* Read the entire image into RAM */ - wolfBoot_printf("Loading image %d bytes to %p\n", - img_size, dst + IMAGE_HEADER_SIZE); + wolfBoot_printf("Loading image %d bytes from %p to %p\n", + img_size, src + IMAGE_HEADER_SIZE, dst + IMAGE_HEADER_SIZE); #if defined(EXT_FLASH) && defined(NO_XIP) ret = ext_flash_read((uintptr_t)src + IMAGE_HEADER_SIZE, dst + IMAGE_HEADER_SIZE, img_size); @@ -88,7 +99,7 @@ int wolfBoot_ramboot(struct wolfBoot_image *img, uint8_t *src, uint8_t *dst) return -1; } #else - memcpy(dst + IMAGE_HEADER_SIZE, src + IMAGE_HEADER_SIZE, img_size); + memcpy32(dst + IMAGE_HEADER_SIZE, src + IMAGE_HEADER_SIZE, img_size); #endif /* mark image as no longer external */