mirror of https://github.com/wolfSSL/wolfBoot.git
Implement port for STM32WBA. Bump wolfHAL lib to latest
Alex Lanzano
Daniele Lacamera
parent
221f2db787
commit
337dabf2f2
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@ -704,6 +704,12 @@ jobs:
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config-file: ./config/examples/stm32wb.config
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make-args: WOLFHAL=1 BOARD=stm32wb_nucleo
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stm32wba_wolfhal_test:
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uses: ./.github/workflows/test-build.yml
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with:
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arch: arm
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config-file: ./config/examples/stm32wba.config
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# TODO: ti-tms570lc435.config requires F021 Flash API (Windows installer only)
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# ti_tms570lc435_test:
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# uses: ./.github/workflows/test-build-ti-hercules.yml
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6
arch.mk
6
arch.mk
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@ -243,6 +243,12 @@ ifeq ($(ARCH),ARM)
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endif
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endif
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ifeq ($(TARGET),stm32wba)
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CORTEX_M33=1
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ARCH_FLASH_OFFSET=0x08000000
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SPI_TARGET=stm32
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endif
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ifeq ($(TARGET),stm32l5)
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CORTEX_M33=1
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CFLAGS+=-Ihal
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@ -0,0 +1,19 @@
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# STM32WBA55CG Nucleo, wolfBoot on the wolfHAL backend.
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#
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# Flash: 1 MB at 0x08000000, 8 KB pages, 128-bit (16-byte) aligned writes.
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# Non-secure / flat mode (the wolfHAL stm32wba flash driver uses the NS
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# flash registers). Bootloader occupies the first 64 KB; two 128 KB
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# partitions plus an 8 KB swap follow.
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TARGET=stm32wba
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BOARD=stm32wba55cg_nucleo
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WOLFHAL=1
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ARCH=ARM
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SIGN=ECC256
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HASH=SHA256
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NO_MPU=1
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WOLFBOOT_SECTOR_SIZE=0x2000
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WOLFBOOT_PARTITION_SIZE=0x20000
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WOLFBOOT_PARTITION_BOOT_ADDRESS=0x08010000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS=0x08030000
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WOLFBOOT_PARTITION_SWAP_ADDRESS=0x08050000
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NVM_FLASH_WRITEONCE=1
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@ -0,0 +1,133 @@
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/* board.c
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*
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* STM32WBA55CG Nucleo board configuration using upstream wolfHAL drivers.
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* Flash/Gpio/Uart singletons are instantiated by the driver .c files from
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* the WHAL_CFG_* initializer macros in board.h; board.c uses the
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* BOARD_*_DEV handles for the rest. RCC is header-inlined and hardcodes
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* its base — no dev pointer needed.
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*
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* Clock target: HSE32 -> PLL1 (M=1, N=25, R=3) -> SYSCLK = 100 MHz, which
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* requires PWR voltage scaling Range 1 and 3 flash wait states (RM0493).
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stddef.h>
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#include "hal.h"
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#include "board.h"
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/* Flash clock gate — enabled before raising the wait-state count. */
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static const whal_Stm32wba_Rcc_PeriphClk g_flashClock = {WHAL_STM32WBA55_FLASH_CLOCK};
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#ifdef DEBUG_UART
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/* GPIO ports A (LED PA9, USART1 RX PA8) and B (USART1 TX PB12) plus USART1. */
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static const whal_Stm32wba_Rcc_PeriphClk g_periphClks[] = {
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{WHAL_STM32WBA55_GPIOA_CLOCK},
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{WHAL_STM32WBA55_GPIOB_CLOCK},
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{WHAL_STM32WBA55_USART1_CLOCK},
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};
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#define PERIPH_CLK_COUNT (sizeof(g_periphClks) / sizeof(g_periphClks[0]))
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#endif
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/*
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* Switch PWR voltage scaling to Range 1 (required for >16 MHz operation).
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* After reset the device is in Range 2 (max 16 MHz). Must switch to Range 1
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* before configuring PLL or increasing SYSCLK.
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*
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* PWR base: 0x46020800, PWR_VOSR offset 0x00C
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* bit 16 VOS: 0=Range2, 1=Range1
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* bit 15 VOSRDY: read-only, 1 when stable
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*/
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#define PWR_BASE 0x46020800
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#define PWR_VOSR_REG 0x00C
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#define PWR_VOSR_VOS_Msk (1UL << 16)
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#define PWR_VOSR_VOSRDY_Msk (1UL << 15)
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static void set_vos_range1(void)
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{
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whal_Reg_Update(PWR_BASE, PWR_VOSR_REG, PWR_VOSR_VOS_Msk, PWR_VOSR_VOS_Msk);
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while (!(whal_Reg_Read(PWR_BASE, PWR_VOSR_REG) & PWR_VOSR_VOSRDY_Msk))
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;
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}
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/* HSE32 -> PLL1 (M=1, N=25, R=3 -> 100 MHz) -> SYSCLK */
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static void pll_clock_on(void)
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{
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/* Enable PWR clock so the PWR registers are accessible, then move to
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* voltage Range 1 (Range 2 after reset caps SYSCLK at 16 MHz). */
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static const whal_Stm32wba_Rcc_PeriphClk pwrClock = {WHAL_STM32WBA55_PWR_CLOCK};
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whal_Stm32wba_Rcc_EnablePeriphClk(&pwrClock);
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set_vos_range1();
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/* Enable flash clock and set latency before increasing clock speed.
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* 100 MHz @ 3.3V needs 3 wait states (RM0493 Table 69). */
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whal_Stm32wba_Rcc_EnablePeriphClk(&g_flashClock);
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whal_Stm32wba_Flash_Ext_SetLatency(BOARD_FLASH_DEV, 3);
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/* AHB5 max 32 MHz: prescale 100 MHz / 4 = 25 MHz (0b101 = div 4). */
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whal_Stm32wba_Rcc_SetHpre5(5);
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whal_Stm32wba_Rcc_EnableOsc(
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&(whal_Stm32wba_Rcc_OscCfg){WHAL_STM32WBA_RCC_HSE32_CFG});
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whal_Stm32wba_Rcc_EnablePll1(&(whal_Stm32wba_Rcc_Pll1Cfg){
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.clkSrc = WHAL_STM32WBA_RCC_PLL1SRC_HSE32,
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.rge = WHAL_STM32WBA_RCC_PLL1RGE_8_16,
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.m = 1, .n = 25, .r = 3, .q = 0, .p = 0,
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});
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whal_Stm32wba_Rcc_SetSysClock(WHAL_STM32WBA_RCC_SYSCLK_SRC_PLL1);
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}
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static void pll_clock_off(void)
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{
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whal_Stm32wba_Rcc_SetSysClock(WHAL_STM32WBA_RCC_SYSCLK_SRC_HSI16);
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whal_Stm32wba_Rcc_DisablePll1();
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whal_Stm32wba_Rcc_DisableOsc(
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&(whal_Stm32wba_Rcc_OscCfg){WHAL_STM32WBA_RCC_HSE32_CFG});
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whal_Stm32wba_Flash_Ext_SetLatency(BOARD_FLASH_DEV, 1);
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}
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void hal_init(void)
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{
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pll_clock_on();
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whal_Flash_Init(BOARD_FLASH_DEV);
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#ifdef DEBUG_UART
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for (size_t i = 0; i < PERIPH_CLK_COUNT; i++) {
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whal_Stm32wba_Rcc_EnablePeriphClk(&g_periphClks[i]);
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}
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whal_Gpio_Init(BOARD_GPIO_DEV);
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whal_Uart_Init(BOARD_UART_DEV);
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#endif
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}
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void hal_prepare_boot(void)
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{
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#ifdef DEBUG_UART
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whal_Uart_Deinit(BOARD_UART_DEV);
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whal_Gpio_Deinit(BOARD_GPIO_DEV);
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for (size_t i = PERIPH_CLK_COUNT; i-- > 0; ) {
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whal_Stm32wba_Rcc_DisablePeriphClk(&g_periphClks[i]);
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}
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#endif
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whal_Flash_Deinit(BOARD_FLASH_DEV);
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pll_clock_off();
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}
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@ -0,0 +1,117 @@
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/* board.h
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*
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* STM32WBA55CG Nucleo wolfHAL board header. Provides the WHAL_CFG_*_DEV
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* initializer macros that the upstream chip drivers use to instantiate the
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* device singletons (in their own .c file), plus the BOARD_X_DEV handles
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* that the wolfBoot adapter (hal/wolfhal.c) and board.c pass into the
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* wolfHAL API.
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*
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* The STM32WBA GPIO/UART peripherals are register-compatible with the
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* STM32WB; the upstream stm32wba_{gpio,uart}.c TUs simply include the
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* stm32wb implementation. The alias headers bridge the names: the GPIO
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* alias maps WHAL_CFG_STM32WB_GPIO_DEV onto the WBA-named macro below,
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* while the UART driver consumes WHAL_CFG_STM32WB_UART_DEV directly (the
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* UART alias header bridges only the singleton symbol). Flash is a native
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* STM32WBA driver and uses the WBA-named macro.
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef WOLFHAL_BOARD_H
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#define WOLFHAL_BOARD_H
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#include <wolfHAL/wolfHAL.h>
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#include <wolfHAL/platform/st/stm32wba55cg.h>
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#include <wolfHAL/clock/stm32wba_rcc.h>
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#include <wolfHAL/flash/stm32wba_flash.h>
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#include <wolfHAL/gpio/stm32wba_gpio.h>
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#include <wolfHAL/uart/stm32wba_uart.h>
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/* GPIO pin indices used by the runtime-addressable pinCfg table. */
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enum {
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BOARD_LED_PIN,
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BOARD_UART_TX_PIN,
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BOARD_UART_RX_PIN,
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BOARD_PIN_COUNT,
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};
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/* Singletons owned by the upstream driver .c files. Declared here so a
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* handle could take their address in the future; the SINGLE_INSTANCE /
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* DIRECT_API_MAPPING drivers read their static singleton directly and
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* ignore the passed dev pointer. (whal_Stm32wba_{Gpio,Uart}_Dev are
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* macro-aliased onto the whal_Stm32wb_* symbols by the alias headers.) */
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extern const whal_Flash whal_Stm32wba_Flash_Dev;
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extern const whal_Gpio whal_Stm32wba_Gpio_Dev;
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extern const whal_Uart whal_Stm32wba_Uart_Dev;
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/* Device handles passed into the wolfHAL API. The direct-mapped /
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* single-instance drivers ignore the dev pointer and read from their
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* static singleton, so the INTERNAL_DEV sentinel is sufficient. */
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#define BOARD_GPIO_DEV WHAL_INTERNAL_DEV
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#define BOARD_UART_DEV WHAL_INTERNAL_DEV
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#define BOARD_FLASH_DEV WHAL_INTERNAL_DEV
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/* Flash singleton initializer — instantiated by stm32wba_flash.c.
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* STM32WBA55: 1 MB flash at 0x08000000, 8 KB pages, 128-bit writes. */
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#define WHAL_CFG_STM32WBA_FLASH_DEV { \
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.base = WHAL_STM32WBA55_FLASH_BASE, \
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.cfg = (void *)&(const whal_Stm32wba_Flash_Cfg){ \
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.startAddr = 0x08000000, \
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.size = 0x100000, \
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}, \
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}
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/* GPIO singleton initializer — consumed by the stm32wb gpio driver via
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* the WHAL_CFG_STM32WB_GPIO_DEV alias in stm32wba_gpio.h. */
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#define WHAL_CFG_STM32WBA_GPIO_DEV { \
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.base = WHAL_STM32WBA55_GPIO_BASE, \
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.cfg = (void *)&(const whal_Stm32wba_Gpio_Cfg){ \
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.pinCfg = (const whal_Stm32wba_Gpio_PinCfg[BOARD_PIN_COUNT]){ \
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/* LED: PA9 (LD2, green), output push-pull, low speed, pull-up */ \
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[BOARD_LED_PIN] = WHAL_STM32WBA_GPIO_PIN( \
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WHAL_STM32WBA_GPIO_PORT_A, 9, WHAL_STM32WBA_GPIO_MODE_OUT, \
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WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_LOW, \
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WHAL_STM32WBA_GPIO_PULL_UP, 0), \
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/* USART1 TX: PB12, AF7 */ \
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[BOARD_UART_TX_PIN] = WHAL_STM32WBA_GPIO_PIN( \
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WHAL_STM32WBA_GPIO_PORT_B, 12, WHAL_STM32WBA_GPIO_MODE_ALTFN, \
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WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_FAST, \
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WHAL_STM32WBA_GPIO_PULL_UP, 7), \
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/* USART1 RX: PA8, AF7 */ \
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[BOARD_UART_RX_PIN] = WHAL_STM32WBA_GPIO_PIN( \
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WHAL_STM32WBA_GPIO_PORT_A, 8, WHAL_STM32WBA_GPIO_MODE_ALTFN, \
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WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_FAST, \
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WHAL_STM32WBA_GPIO_PULL_UP, 7), \
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}, \
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.pinCount = BOARD_PIN_COUNT, \
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}, \
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}
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/* UART singleton initializer — instantiated by stm32wb_uart.c (included by
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* stm32wba_uart.c) when WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE is defined.
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* The UART alias header does not bridge the CFG macro, so the WB name is
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* used directly here. USART1 is clocked from SYSCLK (PLL1 = 100 MHz). */
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#define WHAL_CFG_STM32WB_UART_DEV { \
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.base = WHAL_STM32WBA55_USART1_BASE, \
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.cfg = (void *)&(const whal_Stm32wba_Uart_Cfg){ \
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.brr = WHAL_STM32WBA_UART_BRR(100000000, 115200), \
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}, \
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}
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#endif /* WOLFHAL_BOARD_H */
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@ -0,0 +1,42 @@
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ARCH_FLASH_OFFSET=0x08000000
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LSCRIPT_IN=hal/stm32wba.ld
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CFLAGS+=-DWHAL_CFG_NO_TIMEOUT
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# Upstream wolfHAL drivers from lib/wolfHAL/src/. wolfBoot's hal_flash_*
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# contract is satisfied by hal/wolfhal.c (added automatically because
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# WOLFHAL=1) calling whal_Flash_*.
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#
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# Direct API mapping binds each driver's functions straight to the
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# top-level whal_* symbols (no vtable dispatch source compiled).
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# Flash is a native STM32WBA driver — it checks the WBA-prefixed flag.
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CFLAGS+=-DWHAL_CFG_STM32WBA_FLASH_DIRECT_API_MAPPING
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# GPIO/UART reuse the STM32WB implementation (the stm32wba_*.c TUs include
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# stm32wb_*.c). The UART wrapper forwards its WBA flags to the WB names, so
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# it takes the WBA-prefixed flags. The GPIO wrapper does NOT forward, so the
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# underlying stm32wb_gpio.c must be given the WB-prefixed flag directly.
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CFLAGS+=-DWHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING
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CFLAGS+=-DWHAL_CFG_STM32WBA_UART_DIRECT_API_MAPPING
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# UART is single-instance — reads its singleton from board.h instead of the
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# passed dev pointer.
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CFLAGS+=-DWHAL_CFG_STM32WBA_UART_SINGLE_INSTANCE
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WOLFHAL_OBJS+=$(WOLFHAL_ROOT)/src/reg.o
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WOLFHAL_OBJS+=$(WOLFHAL_ROOT)/src/flash/stm32wba_flash.o
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ifeq ($(DEBUG_UART),1)
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WOLFHAL_OBJS+=$(WOLFHAL_ROOT)/src/gpio/stm32wba_gpio.o
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WOLFHAL_OBJS+=$(WOLFHAL_ROOT)/src/uart/stm32wba_uart.o
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endif
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OBJS+=$(WOLFHAL_OBJS)
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APP_OBJS+=$(WOLFHAL_OBJS)
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# With RAM_CODE=1, place the flash driver in RAM so erase/program runs while
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# the same flash bank is being modified.
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ifeq ($(RAM_CODE),1)
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WOLFHAL_FLASH_EXCLUDE_TEXT=*(EXCLUDE_FILE(*stm32wba_flash.o) .text*)
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WOLFHAL_FLASH_EXCLUDE_RODATA=*(EXCLUDE_FILE(*stm32wba_flash.o) .rodata*)
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WOLFHAL_FLASH_RAM_SECTIONS=*stm32wba_flash.o(.text* .rodata*)
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endif
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@ -0,0 +1,50 @@
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = @BOOTLOADER_PARTITION_SIZE@
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
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}
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SECTIONS
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{
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.text :
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{
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_start_text = .;
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KEEP(*(.isr_vector))
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@WOLFHAL_FLASH_EXCLUDE_TEXT@
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@WOLFHAL_FLASH_EXCLUDE_RODATA@
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. = ALIGN(4);
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_end_text = .;
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} > FLASH
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.edidx :
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{
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. = ALIGN(4);
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*(.ARM.exidx*)
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} > FLASH
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_stored_data = .;
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.data : AT (_stored_data)
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{
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_start_data = .;
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KEEP(*(.data*))
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. = ALIGN(4);
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KEEP(*(.ramcode))
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@WOLFHAL_FLASH_RAM_SECTIONS@
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. = ALIGN(4);
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_end_data = .;
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} > RAM
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.bss (NOLOAD) :
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{
|
||||
_start_bss = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_end_bss = .;
|
||||
__bss_end__ = .;
|
||||
_end = .;
|
||||
} > RAM
|
||||
. = ALIGN(4);
|
||||
}
|
||||
|
||||
END_STACK = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
|
@ -1 +1 @@
|
|||
Subproject commit 2bc2938b0bbcc977177153a7f38393710702bf70
|
||||
Subproject commit 4744f20c0ad0304f093859ad72b39fc86dcae72b
|
||||
Loading…
Reference in New Issue