mirror of https://github.com/wolfSSL/wolfBoot.git
Reverted hal_flash_ functions moved to static
parent
02bfe8a6a1
commit
34652ffebf
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@ -37,7 +37,7 @@ static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
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while ((FLASH_ACR & FLASH_ACR_LATENCY_MASK) != waitstates);
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while ((FLASH_ACR & FLASH_ACR_LATENCY_MASK) != waitstates);
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}
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}
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static void RAMFUNCTION hal_flash_wait_complete(void)
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void RAMFUNCTION hal_flash_wait_complete(uint8_t bank)
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{
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{
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while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
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while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
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;
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;
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@ -48,7 +48,7 @@ static void RAMFUNCTION hal_flash_wait_complete(void)
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}
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}
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static void RAMFUNCTION hal_flash_wait_buffer_empty(void)
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static void RAMFUNCTION hal_flash_wait_buffer_empty(uint8_t bank)
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{
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{
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while ((FLASH_SR & FLASH_SR_DBNE) == FLASH_SR_DBNE)
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while ((FLASH_SR & FLASH_SR_DBNE) == FLASH_SR_DBNE)
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;
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;
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@ -96,7 +96,7 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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dst[i >> 2] = dword[0];
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dst[i >> 2] = dword[0];
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ISB();
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ISB();
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dst[(i >> 2) + 1] = dword[1];
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dst[(i >> 2) + 1] = dword[1];
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hal_flash_wait_complete();
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hal_flash_wait_complete(0);
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if ((*sr & FLASH_SR_EOP) != 0)
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if ((*sr & FLASH_SR_EOP) != 0)
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*sr |= FLASH_SR_EOP;
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*sr |= FLASH_SR_EOP;
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*cr &= ~FLASH_CR_PG;
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*cr &= ~FLASH_CR_PG;
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@ -110,7 +110,7 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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void RAMFUNCTION hal_flash_unlock(void)
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void RAMFUNCTION hal_flash_unlock(void)
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{
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{
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hal_flash_wait_complete();
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hal_flash_wait_complete(0);
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if ((FLASH_CR & FLASH_CR_LOCK) != 0) {
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if ((FLASH_CR & FLASH_CR_LOCK) != 0) {
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FLASH_KEYR = FLASH_KEY1;
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FLASH_KEYR = FLASH_KEY1;
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DMB();
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DMB();
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@ -123,14 +123,14 @@ void RAMFUNCTION hal_flash_unlock(void)
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void RAMFUNCTION hal_flash_lock(void)
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void RAMFUNCTION hal_flash_lock(void)
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{
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{
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hal_flash_wait_complete();
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hal_flash_wait_complete(0);
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if ((FLASH_CR & FLASH_CR_LOCK) == 0)
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if ((FLASH_CR & FLASH_CR_LOCK) == 0)
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FLASH_CR |= FLASH_CR_LOCK;
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FLASH_CR |= FLASH_CR_LOCK;
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}
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}
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void RAMFUNCTION hal_flash_opt_unlock(void)
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void RAMFUNCTION hal_flash_opt_unlock(void)
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{
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{
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hal_flash_wait_complete();
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hal_flash_wait_complete(0);
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if ((FLASH_OPTCR & FLASH_OPTCR_OPTLOCK) != 0) {
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if ((FLASH_OPTCR & FLASH_OPTCR_OPTLOCK) != 0) {
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FLASH_OPTKEYR = FLASH_OPTKEY1;
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FLASH_OPTKEYR = FLASH_OPTKEY1;
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DMB();
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DMB();
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@ -145,7 +145,7 @@ void RAMFUNCTION hal_flash_opt_unlock(void)
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void RAMFUNCTION hal_flash_opt_lock(void)
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void RAMFUNCTION hal_flash_opt_lock(void)
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{
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{
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FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT;
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FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT;
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hal_flash_wait_complete();
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hal_flash_wait_complete(0);
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if ((FLASH_OPTCR & FLASH_OPTCR_OPTLOCK) == 0)
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if ((FLASH_OPTCR & FLASH_OPTCR_OPTLOCK) == 0)
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FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
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FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
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}
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}
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@ -187,7 +187,7 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
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FLASH_CR = reg;
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FLASH_CR = reg;
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DMB();
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DMB();
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FLASH_CR |= FLASH_CR_STRT;
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FLASH_CR |= FLASH_CR_STRT;
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hal_flash_wait_complete();
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hal_flash_wait_complete(0);
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}
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}
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/* If the erase operation is completed, disable the associated bits */
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/* If the erase operation is completed, disable the associated bits */
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FLASH_CR &= ~FLASH_CR_SER ;
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FLASH_CR &= ~FLASH_CR_SER ;
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@ -446,8 +446,8 @@ int hal_flash_otp_write(uint32_t flashAddress, const void* data, uint16_t length
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return -1;
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return -1;
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}
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}
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hal_flash_wait_complete();
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hal_flash_wait_complete(0);
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hal_flash_wait_buffer_empty();
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hal_flash_wait_buffer_empty(0);
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hal_flash_unlock();
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hal_flash_unlock();
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hal_flash_clear_errors(0);
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hal_flash_clear_errors(0);
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@ -456,7 +456,7 @@ int hal_flash_otp_write(uint32_t flashAddress, const void* data, uint16_t length
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length = (length / 2 * 2);
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length = (length / 2 * 2);
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while (idx < length && flashAddress <= FLASH_OTP_END-1) {
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while (idx < length && flashAddress <= FLASH_OTP_END-1) {
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hal_flash_wait_complete();
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hal_flash_wait_complete(0);
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/* Set PG bit */
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/* Set PG bit */
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FLASH_CR |= FLASH_CR_PG;
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FLASH_CR |= FLASH_CR_PG;
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/* Program an OTP word (32 bits) */
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/* Program an OTP word (32 bits) */
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