WolfSSL
/
wolfBoot
mirror of https://github.com/wolfSSL/wolfBoot.git
1
0
Fork 0
Code Issues Releases Wiki Activity

zynq: add ZYNQMP_PHY_OP_DELAY step for PHY post-reset settle time

pull/863/head
David Garske 2026-08-20 12:31:05 -04:00 committed by Daniele Lacamera
parent 1a13fba827
commit 359fda6102
2 changed files with 13 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
hal/zynq.c
View File

@ -1998,6 +1998,11 @@ void hal_delay_ms(uint64_t ms)
}
}
/* Fallback if CNTFRQ_EL0 is unset (no ATF/BL31); ZynqMP counter is 100 MHz */
#ifndef ZYNQMP_TIMER_CLK_FREQ
#define ZYNQMP_TIMER_CLK_FREQ 100000000ULL
#endif
uint64_t hal_timer_ms(void)
{
uint64_t val;
@ -2005,6 +2010,9 @@ uint64_t hal_timer_ms(void)
unsigned long cntpct;
asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
/* AArch64 UDIV by 0 yields 0, which would hang hal_delay_ms() */
if (cntfrq == 0)
cntfrq = ZYNQMP_TIMER_CLK_FREQ;
val = cntpct * 1000;
val /= cntfrq;
return val;
@ -2169,6 +2177,9 @@ static void zynq_phy_init(void)
(int)steps[i].arg0, (int)rval);
}
break;
case ZYNQMP_PHY_OP_DELAY:
hal_delay_ms(steps[i].arg1);
break;
default:
break;
}

2
hal/zynq.h
View File

@ -501,6 +501,8 @@
#define ZYNQMP_PHY_OP_GPIO 0 /* write arg1 to ZYNQMP_PHY_GPIO_ADDR */
#define ZYNQMP_PHY_OP_WR 1 /* MDIO write: reg=arg0, val=arg1 */
#define ZYNQMP_PHY_OP_RD 2 /* MDIO read: reg=arg0 (arg1 ignored) */
#define ZYNQMP_PHY_OP_DELAY 3 /* delay arg1 ms, max 65535 (arg0
* ignored); e.g. PHY reset settle */
/* Default sequence: read the PHY ID registers (2, 3) as a diagnostic. With
* DEBUG_UART=1 this prints the ID and confirms MDIO reached the PHY. Override