Updated NVM_CACHE_SIZE to match different configurations.

Progress on psoc6 HAL, fixed memory mapping and test app

Makefile

@@ -141,6 +141,9 @@ endif
 
 ifeq ($(NVM_FLASH_WRITEONCE),1)
   CFLAGS+= -DNVM_FLASH_WRITEONCE
+  ifneq ($(NVM_CACHE_SIZE),)
+    CFLAGS+= -DNVM_CACHE_SIZE=$(NVM_CACHE_SIZE)
+  endif
 endif
 
 

arch.mk

@@ -159,15 +159,18 @@ ifeq ($(TARGET),psoc6)
 					 $(CYPRESS_PDL)/drivers/source/cy_ipc_drv.o \
 					 $(CYPRESS_PDL)/drivers/source/cy_device.o \
 					 $(CYPRESS_PDL)/drivers/source/cy_sysclk.o \
+					 $(CYPRESS_PDL)/drivers/source/cy_sysint.o \
+					 $(CYPRESS_PDL)/drivers/source/cy_syslib.o \
 					 $(CYPRESS_PDL)/drivers/source/cy_ble_clk.o \
-					 $(CYPRESS_PDL)/devices/templates/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.o \
+					 $(CYPRESS_PDL)/drivers/source/cy_wdt.o \
-					 $(CYPRESS_PDL)/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.o
+					 $(CYPRESS_PDL)/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.o \
+					$(CYPRESS_TARGET_LIB)/COMPONENT_CM0P/system_psoc6_cm0plus.o
     PKA_EXTRA_CFLAGS+=-I$(CYPRESS_PDL)/drivers/include/ \
 		-I$(CYPRESS_PDL)/devices/psoc6/psoc63/include/ \
 		-I$(CYPRESS_PDL)/devices/include \
 		-I$(CYPRESS_PDL)/cmsis/include \
-		-I$(CYPRESS_PDL)/core-lib/include \
+		-I$(CYPRESS_TARGET_LIB) \
-		-I$(CYPRESS_PDL)/devices/templates/COMPONENT_MTB \
+		-I$(CYPRESS_CORE_LIB)/include \
 	    -DCY8C6248FNI_S2D43
     ARCH_FLASH_OFFSET=0x10000000
 endif

hal/psoc6.c

@@ -27,17 +27,78 @@
 
 #include "cy_flash.h"
 #include "cy_syspm.h"
+#include "cy_sysclk.h"
+#include "cy_syslib.h"
 #include "cy_ipc_drv.h"
 
+#define ROW_SIZE (0x200)
+#define CPU_FREQ (100000000)
+
 #ifndef NVM_FLASH_WRITEONCE
 #   error "wolfBoot psoc6 HAL: no WRITEONCE support detected. Please define NVM_FLASH_WRITEONCE"
 #endif
 
+#if (NVM_CACHE_SIZE != ROW_SIZE)
+#   error "Wrong NVM_CACHE_SIZE specified for this platform. Please set NVM_CACHE_SIZE to match ROW_SIZE"
+#endif
 
 #ifdef __WOLFBOOT
+/* Replace Cy_SysLib_DelayUs with a custom call that does not use SysTick
+ * (required by Cy_SysClk_PllEnable)
+ */
+
+#if 0
+void Cy_SysLib_DelayUs(uint16_t delay_us)
+{
+    volatile unsigned int i;
+    uint32_t cycles = ((CPU_FREQ / 1000000)) * delay_us;
+    for (i = 0; i < cycles; i++) {
+        asm volatile("nop");
+    }
+}
+#endif
+
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
+{
+    .feedbackDiv = 100,
+    .referenceDiv = 2,
+    .outputDiv = 4,
+    .lfMode = false,
+    .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+};
+
 void hal_init(void)
 {
-    /* TODO: how to set clock full speed? */
+    SystemInit();
+#if 0
+    /*Set clock path 1 source to IMO, this feeds PLL1*/
+    Cy_SysClk_ClkPathSetSource(1U, CY_SYSCLK_CLKPATH_IN_IMO);
+
+    /*Set the input for CLK_HF0 to the output of the PLL, which is on clock path 1*/
+    Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+    Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+
+    /*Set divider for CM4 clock to 0, might be able to lower this to save power if needed*/
+    Cy_SysClk_ClkFastSetDivider(0U);
+    /*Set divider for peripheral and CM0 clock to 0 - This must be 0 to get fastest clock to CM0*/
+    Cy_SysClk_ClkPeriSetDivider(0U);
+    /*Set divider for CM0 clock to 0*/
+    Cy_SysClk_ClkSlowSetDivider(0U);
+
+    /*Configure PLL for 100 MHz*/
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
+    {
+        while(1)
+            ;
+    }
+    /*Enable PLL*/
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
+    {
+        while(1)
+            ;
+    }
+#endif
+    Cy_Flash_Init();
 }
 
 void hal_prepare_boot(void)
@@ -47,11 +108,20 @@ void hal_prepare_boot(void)
 
 #endif
 
+
+/* Only Row-aligned writes allowed. This is guaranteed by wolfBoot if NVM_CACHE is
+ * in use (via NVM_FLASH_WRITEONCE=1), as unaligned writes become cached.
+ */
 int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
 {
-    if (len != WOLFBOOT_SECTOR_SIZE)
+    if (len < NVM_CACHE_SIZE)
         return -1;
-    Cy_Flash_WriteRow(address,(const uint32_t *) data);
+    while (len) {
+        Cy_Flash_WriteRow(address, (const uint32_t *) data);
+        len -= NVM_CACHE_SIZE;
+        if ((len > 0) && (len < NVM_CACHE_SIZE))
+            return -1;
+    }
     return 0;
 }
 
@@ -67,12 +137,16 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
 {
     int start = -1, end = -1;
     uint32_t end_address;
-    uint32_t p;
+    uint32_t p = (uint32_t)address;
     if (len == 0)
         return -1;
-    end_address = address + len - 1;
+    end_address = address + len;
-    for (p = address; p < end_address; p += WOLFBOOT_SECTOR_SIZE) {
+    /* Assume NVM_CACHE_SIZE is always defined for this platform 
+     * (see #error statements above)
+     * */
+    while ((end_address - p) >= NVM_CACHE_SIZE) {
         Cy_Flash_EraseRow(p);
+        p += NVM_CACHE_SIZE;
     }
     return 0;
 }

hal/psoc6.ld

@@ -10,6 +10,7 @@ SECTIONS
     .text :
     {
         _start_text = .;
+        __Vectors = .;
         KEEP(*(.isr_vector))
         . = ALIGN(0x400);
         *(.text*)
@@ -46,8 +47,10 @@ SECTIONS
         _end_bss = .;
         __bss_end__ = .;
         _end = .;
+        __ramVectors = .;
     } > RAM
     . = ALIGN(4);
 }
 
 END_STACK = ORIGIN(RAM) + LENGTH(RAM);
+

include/wolfboot/wolfboot.h

@@ -34,6 +34,12 @@
 #endif
 #define IMAGE_HEADER_OFFSET (2 * sizeof(uint32_t))
 
+#ifdef NVM_FLASH_WRITEONCE
+#   define FLASHBUFFER_SIZE NVM_CACHE_SIZE
+#else
+#   define FLASHBUFFER_SIZE IMAGE_HEADER_SIZE
+#endif
+
 #define WOLFBOOT_MAGIC          0x464C4F57 /* WOLF */
 #define WOLFBOOT_MAGIC_TRAIL    0x544F4F42 /* BOOT */
 
@@ -111,4 +117,5 @@ int wolfBoot_dualboot_candidate(void);
 #   error "No valid hash algorithm defined!"
 #endif
 
+
 #endif /* !WOLFBOOT_H */

src/boot_arm.c

@@ -97,8 +97,12 @@ void RAMFUNCTION do_boot(const uint32_t *app_offset)
 #ifndef NO_VTOR
     /* Disable interrupts */
     asm volatile("cpsid i");
-    /* Update IV */
+    #ifdef PLATFORM_psoc6
-    VTOR = ((uint32_t)app_offset);
+        VTOR = (((uint32_t)(app_offset)) - ARCH_FLASH_OFFSET);
+    #else
+        /* Update IV */
+        VTOR = ((uint32_t)app_offset);
+    #endif
 #endif
 
     /* Get stack pointer, entry point */

src/libwolfboot.c

@@ -39,9 +39,14 @@ uint32_t ext_cache;
 #define PART_UPDATE_ENDFLAGS ((WOLFBOOT_PARTITION_UPDATE_ADDRESS + WOLFBOOT_PARTITION_SIZE) - TRAILER_SKIP)
 
 #ifdef NVM_FLASH_WRITEONCE
+
+#ifndef NVM_CACHE_SIZE
+    #error "Please define NVM_CACHE_SIZE for this flash model"
+#endif
+
 #include <stddef.h>
 extern void *memcpy(void *dst, const void *src, size_t n);
-static uint8_t NVM_CACHE[WOLFBOOT_SECTOR_SIZE];
+static uint8_t NVM_CACHE[NVM_CACHE_SIZE];
 int RAMFUNCTION hal_trailer_write(uint32_t addr, uint8_t val) {
     uint32_t addr_align = addr & (~(WOLFBOOT_SECTOR_SIZE - 1));
     uint32_t addr_off = addr & (WOLFBOOT_SECTOR_SIZE - 1);

src/loader.c

@@ -32,8 +32,6 @@ static volatile const uint32_t __attribute__((used)) wolfboot_version = WOLFBOOT
 extern void (** const IV_RAM)(void);
 #endif
 
-#define FLASHBUFFER_SIZE 256
-
 #ifndef DUALBANK_SWAP
 static int wolfBoot_copy_sector(struct wolfBoot_image *src, struct wolfBoot_image *dst, uint32_t sector)
 {

src/update_flash.c

@@ -28,7 +28,6 @@
 #include "spi_flash.h"
 #include "wolfboot/wolfboot.h"
 
-#define FLASHBUFFER_SIZE 256
 
 #ifdef RAM_CODE
 extern unsigned int _start_text;

test-app/ARM-psoc6.ld

@@ -0,0 +1,55 @@
+MEMORY
+{
+    FLASH (rx) : ORIGIN = ##WOLFBOOT_TEST_APP_ADDRESS##, LENGTH = ##WOLFBOOT_TEST_APP_SIZE##
+    RAM (rwx)  : ORIGIN = 0x08000000, LENGTH = 64K
+}
+
+SECTIONS
+{
+
+    .text :
+    {
+        _start_text = .;
+        KEEP(*(.isr_vector))
+        . = ALIGN(0x400);
+        *(.text*)
+        *(.rodata*)
+        *(.init*)
+        *(.fini*)
+        . = ALIGN(4);
+        _end_text = .;
+    } > FLASH
+
+    .edidx :
+    {
+        . = ALIGN(4);
+        *(.ARM.exidx*)
+    } > FLASH
+
+    _stored_data = .;
+
+    .data : AT (_stored_data)
+    {
+        _start_data = .;
+        KEEP(*(.data*))
+        . = ALIGN(4);
+        _end_data = .;
+    } > RAM
+
+    .bss (NOLOAD) :
+    {
+        _start_bss = .;
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _end_bss = .;
+        __bss_end__ = .;
+        _end = .;
+    } > RAM
+    . = ALIGN(4);
+}
+
+END_STACK = ORIGIN(RAM) + LENGTH(RAM);
+PROVIDE(_start_heap = _end);
+PROVIDE(_end_stack  = ORIGIN(RAM) + LENGTH(RAM));

test-app/Makefile

@@ -46,6 +46,10 @@ ifeq ($(TARGET),stm32f7)
   LSCRIPT_TEMPLATE=ARM-stm32f7.ld
   CFLAGS+=-DDUALBANK_SWAP
 endif
+ifeq ($(TARGET),psoc6)
+  LSCRIPT_TEMPLATE=ARM-psoc6.ld
+endif
+
 LDFLAGS:=$(CFLAGS) -T $(LSCRIPT) -Wl,-gc-sections -Wl,-Map=image.map
 
 ifeq ($(EXT_FLASH),1)

tools/config.mk

@@ -10,7 +10,9 @@ ifeq ($(ARCH),)
   MCUXPRESSO_CMSIS?=$(MCUXPRESSO)/CMSIS
   FREEDOM_E_SDK?=$(HOME)/src/freedom-e-sdk
   STM32CUBE?=$(HOME)/STM32Cube/Repository/STM32Cube_FW_WB_V1.3.0
-  CYPRESS_PDL?=$(HOME)/src/Cypress-Peripheral-Driver-Library-v3.0.1
+  CYPRESS_PDL?=$(HOME)/src/psoc6pdl
+  CYPRESS_TARGET_LIB?=$(HOME)/src/TARGET_CY8CKIT-062S2-43012
+  CYPRESS_CORE_LIB?=$(HOME)/src/cypress-core-lib
   DEBUG?=0
   VTOR?=1
   CORTEX_M0?=0
@@ -21,6 +23,7 @@ ifeq ($(ARCH),)
   UART_FLASH?=0
   ALLOW_DOWNGRADE?=0
   NVM_FLASH_WRITEONCE?=0
+  NVM_CACHE_SIZE=512
   WOLFBOOT_VERSION?=0
   V?=0
   SPMATH?=1
@@ -42,8 +45,9 @@ endif
 
 
 CONFIG_VARS:= ARCH TARGET SIGN HASH MCUXPRESSO MCUXPRESSO_CPU MCUXPRESSO_DRIVERS \
-	MCUXPRESSO_CMSIS FREEDOM_E_SDK STM32CUBE CYPRESS_PDL DEBUG VTOR CORTEX_M0 NO_ASM EXT_FLASH \
+	MCUXPRESSO_CMSIS FREEDOM_E_SDK STM32CUBE CYPRESS_PDL CYPRESS_CORE_LIB CYPRESS_TARGET_LIB DEBUG VTOR \
-	SPI_FLASH NO_XIP UART_FLASH ALLOW_DOWNGRADE NVM_FLASH_WRITEONCE WOLFBOOT_VERSION V \
+	CORTEX_M0 NO_ASM EXT_FLASH SPI_FLASH NO_XIP UART_FLASH ALLOW_DOWNGRADE NVM_FLASH_WRITEONCE \
+	NVM_CACHE_SIZE WOLFBOOT_VERSION V \
 	SPMATH RAM_CODE DUALBANK_SWAP IMAGE_HEADER_SIZE PKA WOLFTPM \
 	WOLFBOOT_PARTITION_SIZE WOLFBOOT_SECTOR_SIZE  \
 	WOLFBOOT_PARTITION_BOOT_ADDRESS WOLFBOOT_PARTITION_UPDATE_ADDRESS \