mirror of https://github.com/wolfSSL/wolfBoot.git
Add support for fixing up the Ethernet MAC using device serial number (matches U-Boot behavior).
David Garske
Daniele Lacamera
parent
46677d76e7
commit
4673c8272d
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@ -1094,7 +1094,8 @@ set architecture riscv:rv64
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### PolarFire Example Boot Output
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```
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wolfBoot Version: 2.7.0 (Dec 29 2025 11:34:01)
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wolfBoot Version: 2.7.0 (Dec 31 2025 15:33:35)
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Disk encryption enabled
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Reading MBR...
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Found GPT PTE at sector 1
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Found valid boot signature in MBR
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@ -1111,12 +1112,13 @@ disk0.p3 (7_65AFFE00h@ 0_8900000)
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Total partitions on disk0: 4
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Checking primary OS image in 0,1...
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Checking secondary OS image in 0,2...
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Versions, A:1 B:1
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Versions, A:1 B:0
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Load address 0x8E000000
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Attempting boot from P:A
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Boot partition: 0x801FFD80 (sz 19767004, ver 0x1, type 0x601)
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Loading image from disk...done. (846 ms)
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Boot partition: 0x8E000000 (sz 19767004, ver 0x1, type 0x601)
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Boot partition: 0x801FFD90 (sz 19767004, ver 0x0, type 0x0)
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Loading image from disk...done. (877 ms)
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Decrypting image...done. (2894 ms)
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Boot partition: 0x8E000000 (sz 19767004, ver 0x0, type 0x0)
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Checking image integrity...done. (1507 ms)
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Verifying image signature...done. (68 ms)
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Firmware Valid.
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@ -1128,6 +1130,11 @@ Image fdt-1: 0x8A000000 (19897 bytes)
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Loading DTS: 0x8A000000 -> 0x8A000000 (19897 bytes)
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Invalid elf, falling back to raw binary
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Booting at 80200000
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FDT: Version 17, Size 19897
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FDT: Set chosen (13840), bootargs=earlycon root=/dev/mmcblk0p4 rootwait uio_pdrv_genirq.of_id=generic-uio
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FDT: Device serial: 219A437C-6AE1F1C2-8EDC4324-685B2288
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FDT: MAC0 = 00:04:A3:5B:22:88
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FDT: MAC1 = 00:04:A3:5B:22:89
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[ 0.000000] Linux version 6.12.22-linux4microchip+fpga-2025.07-g032a7095303a (oe-user@oe-host) (riscv64-oe-linux-gcc (GCC) 13.3.0, GNU ld (GNU Binutils) 2.42.0.20240723) #1 SMP Tue Jul 22 10:04:20 UTC 2025
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[ 0.000000] Machine model: Microchip PolarFire-SoC VIDEO Kit
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[ 0.000000] SBI specification v1.0 detected
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@ -1193,7 +1200,6 @@ Benchmark complete
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### PolarFire TODO
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* Add support for reading serial number and modifying ethernet MAC in device tree
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* Add support for QSPI NOR flash
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* Add support for full HSS replacement using wolfboot
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- Machine level assembly startup
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154
hal/mpfs250.c
154
hal/mpfs250.c
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@ -56,6 +56,89 @@ void hal_init(void)
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LIBWOLFBOOT_VERSION_STRING,__DATE__, __TIME__);
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}
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/* ============================================================================
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* System Controller Mailbox Functions
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*
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* The MPFS system controller provides various system services via a mailbox
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* interface. Commands are sent by writing the opcode to the control register
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* and responses are read from the mailbox RAM.
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* ============================================================================ */
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/**
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* mpfs_scb_mailbox_busy - Check if the system controller mailbox is busy
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*
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* Returns: non-zero if busy, 0 if ready
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*/
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static int mpfs_scb_mailbox_busy(void)
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{
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return (SCBCTRL_REG(SERVICES_SR_OFFSET) & SERVICES_SR_BUSY_MASK);
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}
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/**
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* mpfs_read_serial_number - Read the device serial number via system services
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* @serial: Buffer to store the 16-byte device serial number
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*
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* This function sends a serial number request (opcode 0x00) to the system
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* controller and reads the 16-byte response from the mailbox RAM.
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*
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* Returns: 0 on success, negative error code on failure
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*/
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static int mpfs_read_serial_number(uint8_t *serial)
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{
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uint32_t cmd, status;
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int i, timeout;
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if (serial == NULL) {
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return -1;
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}
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/* Check if mailbox is busy */
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if (mpfs_scb_mailbox_busy()) {
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wolfBoot_printf("SCB mailbox busy\n");
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return -2;
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}
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/* Send serial number request command (opcode 0x00)
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* Command format: [31:16] = opcode, [0] = request bit */
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cmd = (SYS_SERV_CMD_SERIAL_NUMBER << SERVICES_CR_COMMAND_SHIFT) |
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SERVICES_CR_REQ_MASK;
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SCBCTRL_REG(SERVICES_CR_OFFSET) = cmd;
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/* Wait for request bit to clear (command accepted) */
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timeout = 10000;
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while ((SCBCTRL_REG(SERVICES_CR_OFFSET) & SERVICES_CR_REQ_MASK) && timeout > 0) {
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timeout--;
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}
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if (timeout == 0) {
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wolfBoot_printf("SCB mailbox request timeout\n");
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return -3;
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}
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/* Wait for busy bit to clear (command completed) */
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timeout = 10000;
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while (mpfs_scb_mailbox_busy() && timeout > 0) {
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timeout--;
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}
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if (timeout == 0) {
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wolfBoot_printf("SCB mailbox busy timeout\n");
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return -4;
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}
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/* Check status (upper 16 bits of status register) */
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status = (SCBCTRL_REG(SERVICES_SR_OFFSET) >> SERVICES_SR_STATUS_SHIFT) & 0xFFFF;
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if (status != 0) {
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wolfBoot_printf("SCB mailbox error: 0x%x\n", status);
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return -5;
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}
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/* Read serial number from mailbox RAM (16 bytes) */
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for (i = 0; i < DEVICE_SERIAL_NUMBER_SIZE; i++) {
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serial[i] = SCBMBOX_BYTE(i);
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}
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return 0;
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}
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/* Linux kernel command line arguments */
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#ifndef LINUX_BOOTARGS
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#ifndef LINUX_BOOTARGS_ROOT
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@ -66,10 +149,17 @@ void hal_init(void)
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"earlycon root="LINUX_BOOTARGS_ROOT" rootwait uio_pdrv_genirq.of_id=generic-uio"
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#endif
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/* Microchip OUI (Organizationally Unique Identifier) for MAC address */
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#define MICROCHIP_OUI_0 0x00
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#define MICROCHIP_OUI_1 0x04
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#define MICROCHIP_OUI_2 0xA3
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int hal_dts_fixup(void* dts_addr)
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{
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int off, ret;
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struct fdt_header *fdt = (struct fdt_header *)dts_addr;
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uint8_t device_serial_number[DEVICE_SERIAL_NUMBER_SIZE];
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uint8_t mac_addr[6];
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/* Verify FDT header */
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ret = fdt_check_header(dts_addr);
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@ -96,8 +186,68 @@ int hal_dts_fixup(void* dts_addr)
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fdt_fixup_str(fdt, off, "chosen", "bootargs", LINUX_BOOTARGS);
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}
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/* TODO: Consider additional FDT fixups:
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* ethernet0: local-mac-address {0x00, 0x04, 0xA3, SERIAL2, SERIAL1, SERIAL0} */
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/* Read device serial number from system controller */
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ret = mpfs_read_serial_number(device_serial_number);
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if (ret != 0) {
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wolfBoot_printf("FDT: Failed to read serial number (%d)\n", ret);
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/* Continue without setting MAC addresses */
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return 0;
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}
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wolfBoot_printf("FDT: Device serial: %02x%02x%02x%02x-%02x%02x%02x%02x-"
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"%02x%02x%02x%02x-%02x%02x%02x%02x\n",
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device_serial_number[15], device_serial_number[14],
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device_serial_number[13], device_serial_number[12],
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device_serial_number[11], device_serial_number[10],
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device_serial_number[9], device_serial_number[8],
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device_serial_number[7], device_serial_number[6],
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device_serial_number[5], device_serial_number[4],
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device_serial_number[3], device_serial_number[2],
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device_serial_number[1], device_serial_number[0]);
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/* Build MAC address: Microchip OUI + lower 3 bytes of serial number
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* Format: {0x00, 0x04, 0xA3, serial[2], serial[1], serial[0]} */
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mac_addr[0] = MICROCHIP_OUI_0;
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mac_addr[1] = MICROCHIP_OUI_1;
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mac_addr[2] = MICROCHIP_OUI_2;
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mac_addr[3] = device_serial_number[2];
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mac_addr[4] = device_serial_number[1];
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mac_addr[5] = device_serial_number[0];
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wolfBoot_printf("FDT: MAC0 = %02x:%02x:%02x:%02x:%02x:%02x\n",
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mac_addr[0], mac_addr[1], mac_addr[2],
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mac_addr[3], mac_addr[4], mac_addr[5]);
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/* Set local-mac-address for ethernet@20110000 (mac0) */
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off = fdt_find_node_offset(fdt, -1, "ethernet@20110000");
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if (off >= 0) {
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ret = fdt_setprop(fdt, off, "local-mac-address", mac_addr, 6);
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if (ret != 0) {
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wolfBoot_printf("FDT: Failed to set mac0 address (%d)\n", ret);
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}
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}
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else {
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wolfBoot_printf("FDT: ethernet@20110000 not found\n");
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}
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/* Set local-mac-address for ethernet@20112000 (mac1)
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* Use MAC address + 1 for the second interface */
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mac_addr[5] = device_serial_number[0] + 1;
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wolfBoot_printf("FDT: MAC1 = %02x:%02x:%02x:%02x:%02x:%02x\n",
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mac_addr[0], mac_addr[1], mac_addr[2],
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mac_addr[3], mac_addr[4], mac_addr[5]);
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off = fdt_find_node_offset(fdt, -1, "ethernet@20112000");
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if (off >= 0) {
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ret = fdt_setprop(fdt, off, "local-mac-address", mac_addr, 6);
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if (ret != 0) {
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wolfBoot_printf("FDT: Failed to set mac1 address (%d)\n", ret);
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}
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}
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else {
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wolfBoot_printf("FDT: ethernet@20112000 not found\n");
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}
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return 0;
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}
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@ -131,6 +131,39 @@
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* ============================================================================ */
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#define EMMC_SD_BASE 0x20008000UL
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/* ============================================================================
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* System Controller Mailbox
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* Control Base: 0x37020000
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* Mailbox RAM: 0x37020800
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*
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* Used for system services like reading the device serial number.
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* ============================================================================ */
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#define SCBCTRL_BASE 0x37020000UL
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#define SCBMBOX_BASE 0x37020800UL
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/* System Services Control and Status Register offsets (from SCBCTRL_BASE) */
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#define SERVICES_CR_OFFSET 0x50u
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#define SERVICES_SR_OFFSET 0x54u
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/* Control Register bits */
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#define SERVICES_CR_REQ_MASK 0x01u
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#define SERVICES_CR_COMMAND_SHIFT 16
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/* Status Register bits */
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#define SERVICES_SR_BUSY_MASK 0x02u
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#define SERVICES_SR_STATUS_SHIFT 16
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/* System Service command opcodes */
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#define SYS_SERV_CMD_SERIAL_NUMBER 0x00u
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/* Device serial number size in bytes */
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#define DEVICE_SERIAL_NUMBER_SIZE 16
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/* System Controller register access */
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#define SCBCTRL_REG(off) (*((volatile uint32_t*)(SCBCTRL_BASE + (off))))
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#define SCBMBOX_REG(off) (*((volatile uint32_t*)(SCBMBOX_BASE + (off))))
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#define SCBMBOX_BYTE(off) (*((volatile uint8_t*)(SCBMBOX_BASE + (off))))
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/* Crypto Engine: Athena F5200 TeraFire Crypto Processor (1x), 200 MHz */
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#define ATHENA_BASE (SYSREG_BASE + 0x125000)
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