mirror of https://github.com/wolfSSL/wolfBoot.git
[SAMA5D3] Port for 32bit Cortex-A
Daniele Lacamera
parent
03675979a4
commit
4cbfdf8cf1
4
Makefile
4
Makefile
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@ -130,6 +130,10 @@ ifeq ($(TARGET),nxp_t1024)
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MAIN_TARGET:=factory_wstage1.bin
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endif
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ifeq ($(TARGET),sama5d3)
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MAIN_TARGET:=wolfboot.bin
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endif
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ifeq ($(FLASH_OTP_KEYSTORE),1)
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MAIN_TARGET+=tools/keytools/otp/otp-keystore-primer.bin
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endif
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141
arch.mk
141
arch.mk
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@ -70,7 +70,6 @@ ifeq ($(ARCH),ARM)
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CROSS_COMPILE?=arm-none-eabi-
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CFLAGS+=-mthumb -mlittle-endian -mthumb-interwork -DARCH_ARM
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LDFLAGS+=-mthumb -mlittle-endian -mthumb-interwork
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OBJS+=src/boot_arm.o
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## Target specific configuration
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ifeq ($(TARGET),samr21)
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@ -176,88 +175,102 @@ ifeq ($(ARCH),ARM)
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SPI_TARGET=stm32
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endif
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## Cortex-M CPU
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ifeq ($(CORTEX_M33),1)
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CFLAGS+=-mcpu=cortex-m33 -DCORTEX_M33
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LDFLAGS+=-mcpu=cortex-m33
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ifeq ($(TZEN),1)
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OBJS+=hal/stm32_tz.o
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CFLAGS+=-mcmse
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ifeq ($(WOLFCRYPT_TZ),1)
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SECURE_OBJS+=./src/wc_callable.o
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SECURE_OBJS+=./lib/wolfssl/wolfcrypt/src/random.o
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CFLAGS+=-DWOLFCRYPT_SECURE_MODE
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SECURE_LDFLAGS+=-Wl,--cmse-implib -Wl,--out-implib=./src/wc_secure_calls.o
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endif
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endif # TZEN=1
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ifeq ($(NO_ASM),1)
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ifeq ($(SPMATH),1)
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ifeq ($(NO_ASM),1)
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
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else
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CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
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endif
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endif
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else
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ifeq ($(SPMATH),1)
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CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
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endif
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ifeq ($(TARGET),sama5d3)
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CORTEX_A5=1
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endif
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## Cortex CPU
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ifeq ($(CORTEX_A5),1)
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CFLAGS+=-mcpu=cortex-a5 -mtune=cortex-a5 -mfpu=vfpv4-d16 -static -z noexecstack
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LDLAGS+=-mcpu=cortex-a5 -mtune=cortex-a5 -mtune=cortex-a5 -mfpu=vfpv4-d16 -static -z noexecstack -Ttext 0x300000
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# Cortex-A uses boot_arm32.o
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OBJS+=src/boot_arm32.o src/boot_arm32_start.o
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
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else
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ifeq ($(CORTEX_M7),1)
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CFLAGS+=-mcpu=cortex-m7
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LDFLAGS+=-mcpu=cortex-m7
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ifeq ($(SPMATH),1)
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ifeq ($(NO_ASM),1)
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
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else
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CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
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# All others use boot_arm.o
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OBJS+=src/boot_arm.o
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ifeq ($(CORTEX_M33),1)
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CFLAGS+=-mcpu=cortex-m33 -DCORTEX_M33
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LDFLAGS+=-mcpu=cortex-m33
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ifeq ($(TZEN),1)
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OBJS+=hal/stm32_tz.o
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CFLAGS+=-mcmse
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ifeq ($(WOLFCRYPT_TZ),1)
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SECURE_OBJS+=./src/wc_callable.o
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SECURE_OBJS+=./lib/wolfssl/wolfcrypt/src/random.o
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CFLAGS+=-DWOLFCRYPT_SECURE_MODE
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SECURE_LDFLAGS+=-Wl,--cmse-implib -Wl,--out-implib=./src/wc_secure_calls.o
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endif
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endif
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else
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ifeq ($(CORTEX_M0),1)
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CFLAGS+=-mcpu=cortex-m0
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LDFLAGS+=-mcpu=cortex-m0
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endif # TZEN=1
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ifeq ($(NO_ASM),1)
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ifeq ($(SPMATH),1)
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ifeq ($(NO_ASM),1)
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
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else
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CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_THUMB_ASM
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_armthumb.o
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CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
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endif
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endif
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else
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ifeq ($(CORTEX_M3),1)
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CFLAGS+=-mcpu=cortex-m3
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LDFLAGS+=-mcpu=cortex-m3
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ifeq ($(SPMATH),1)
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CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
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endif
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endif
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else
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ifeq ($(CORTEX_M7),1)
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CFLAGS+=-mcpu=cortex-m7
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LDFLAGS+=-mcpu=cortex-m7
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ifeq ($(SPMATH),1)
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ifeq ($(NO_ASM),1)
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
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else
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CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
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endif
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endif
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else
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ifeq ($(CORTEX_M0),1)
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CFLAGS+=-mcpu=cortex-m0
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LDFLAGS+=-mcpu=cortex-m0
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ifeq ($(SPMATH),1)
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ifeq ($(NO_ASM),1)
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
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else
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CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_THUMB_ASM
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_armthumb.o
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endif
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endif
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else
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ifeq ($(CORTEX_M3),1)
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CFLAGS+=-mcpu=cortex-m3
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LDFLAGS+=-mcpu=cortex-m3
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ifeq ($(NO_ASM),1)
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ifeq ($(SPMATH),1)
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
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endif
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else
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ifeq ($(SPMATH),1)
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CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM -DWOLFSSL_SP_NO_UMAAL
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
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endif
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endif
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else
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# default Cortex M4
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CFLAGS+=-mcpu=cortex-m4
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LDFLAGS+=-mcpu=cortex-m4
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ifeq ($(NO_ASM),1)
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ifeq ($(SPMATH),1)
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
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endif
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else
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CFLAGS+=-fomit-frame-pointer # required with debug builds only
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ifeq ($(SPMATH),1)
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CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM -DWOLFSSL_SP_NO_UMAAL
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CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
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endif
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endif
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else
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# default Cortex M4
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CFLAGS+=-mcpu=cortex-m4
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LDFLAGS+=-mcpu=cortex-m4
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ifeq ($(NO_ASM),1)
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ifeq ($(SPMATH),1)
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
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endif
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else
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CFLAGS+=-fomit-frame-pointer # required with debug builds only
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ifeq ($(SPMATH),1)
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CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
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MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
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endif
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endif
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endif
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endif
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@ -8,6 +8,7 @@ This README describes configuration of supported targets.
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* [Cypress PSoC-6](#cypress-psoc-6)
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* [Infineon AURIX TC3xx](#infineon-aurix-tc3xx)
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* [Intel x86-64 Intel FSP](#intel-x86_64-with-intel-fsp-support)
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* [Microchip SAMA5D3](#microchip-sama5d3)
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* [Microchip SAME51](#microchip-same51)
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* [NXP Kinetis](#nxp-kinetis)
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* [NXP LPC54xxx](#nxp-lpc54xxx)
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@ -1405,6 +1406,51 @@ the monitor command sequence below:
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(gdb) mon psoc6 reset_halt
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```
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## Microchip SAMA5D3
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SAMA5D3 is a Cortex-A5 Microprocessor. The ATSAMA5D3-XPLAINED is the evaluation
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board used for wolfBoot port, which also equips a 2MB NAND flash. WolfBoot
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replaces the default first stage bootloader (at91bootstrap).
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### Building wolfBoot
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An example configuration file is provided.
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`cp config/examples/sama5d3.config .config`
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Run make to build wolfBoot.bin and the test application
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`make`
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### Programming wolfboot.bin into NAND flash
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To flash any firmware image into the device NVMs, you need the tool `sam-ba`,
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distributed by Microchip.
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This procedure has been tested using sam-ba v.3.8 using ATSAMA5D3-XPLAINED board,
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with JP6 (aka the `SPI_CS` jumper) removed, so the system boots from NAND by
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default.
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Step 1: install the tool, connect a J-Link device to the J24 JTAG connector then run the
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following command to activate "lowlevel" mode:
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`sam-ba -p j-link -b sama5d3-xplained -t 5 -a lowlevel`
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Step 2: erase the entire NAND flash:
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`sam-ba -p j-link -b sama5d3-xplained -t 5 -a nandflash -c erase`
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Step 3: program `wolfboot.bin` to the beginning of the flash:
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`sam-ba -p j-link -b sama5d3-xplained -t 5 -a nandflash -c writeboot:wolfboot.bin`
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### Programming the test application into NAND flash
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(TODO)
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## Microchip SAME51
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SAME51 is a Cortex-M4 microcontroller with a dual-bank, 1MB flash memory divided
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@ -0,0 +1,94 @@
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/* atsama5d3.c
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*
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* Copyright (C) 2024 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include <string.h>
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#include <target.h>
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#include "image.h"
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#ifndef ARCH_ARM
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# error "wolfBoot atsama5d3 HAL: wrong architecture selected. Please compile with ARCH=ARM."
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#endif
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#define TEST_ENCRYPT
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/* Fixed addresses */
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extern void *kernel_addr, *update_addr, *dts_addr;
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void* hal_get_primary_address(void)
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{
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return (void*)&kernel_addr;
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}
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void* hal_get_update_address(void)
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{
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return (void*)&update_addr;
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}
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void* hal_get_dts_address(void)
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{
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return (void*)&dts_addr;
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}
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void* hal_get_dts_update_address(void)
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{
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return NULL; /* Not yet supported */
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}
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/* QSPI functions */
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void qspi_init(uint32_t cpu_clock, uint32_t flash_freq)
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{
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}
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void zynq_init(uint32_t cpu_clock)
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{
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}
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/* public HAL functions */
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void hal_init(void)
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{
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}
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void hal_prepare_boot(void)
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{
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}
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int RAMFUNCTION hal_flash_write(uintptr_t address, const uint8_t *data, int len)
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{
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return 0;
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}
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void RAMFUNCTION hal_flash_unlock(void)
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{
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}
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void RAMFUNCTION hal_flash_lock(void)
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{
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}
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int RAMFUNCTION hal_flash_erase(uintptr_t address, int len)
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{
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return 0;
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}
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@ -0,0 +1,53 @@
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OUTPUT_FORMAT("elf32-littlearm")
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OUTPUT_ARCH(arm)
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MEMORY
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{
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DDR_MEM(rwx): ORIGIN = 0x00300000, LENGTH = 0x000100000
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}
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ENTRY(reset_vector_entry)
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SECTIONS
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{
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.text : {
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_start_text = .;
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*(.text)
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*(.rodata)
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*(.rodata*)
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. = ALIGN(4);
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*(.glue_7)
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. = ALIGN(4);
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*(.eh_frame)
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. = ALIGN(4);
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_end_text = . ;
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}
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/* collect all initialized .data sections */
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/* .data : AT ( ADDR (.text) + SIZEOF (.text) SIZEOF (.ARM.*) { */
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. = ALIGN(4);
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.dummy : {
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_edummy = .;
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}
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.data : AT (LOADADDR(.dummy)) {
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_start_data = .;
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*(.vectors)
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*(.data)
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_end_data = .;
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}
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/* collect all uninitialized .bss sections */
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.bss (NOLOAD) : {
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. = ALIGN(4);
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_start_bss = .;
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*(.bss)
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_end_bss = .;
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}
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}
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_romsize = _end_data - _start_text;
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_sramsize = _end_bss - _start_text;
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END_STACK = _start_text;
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_stack_top = ORIGIN(DDR_MEM) + LENGTH(DDR_MEM);
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end = .; /* define a global symbol marking the end of application */
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@ -0,0 +1,100 @@
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/* boot_arm32.c
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*
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* Bring up, vectors and do_boot for 32bit Cortex-A microprocessors.
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*
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* Copyright (C) 2024 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 3 of the License, or
|
||||
* (at your option) any later version.
|
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*
|
||||
* wolfBoot is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include "image.h"
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#include "loader.h"
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#include "wolfboot/wolfboot.h"
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extern unsigned int __bss_start__;
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extern unsigned int __bss_end__;
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static volatile unsigned int cpu_id;
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extern unsigned int *END_STACK;
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extern void main(void);
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void boot_entry_C(void)
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{
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register unsigned int *dst;
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/* Initialize the BSS section to 0 */
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dst = &__bss_start__;
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while (dst < (unsigned int *)&__bss_end__) {
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*dst = 0U;
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dst++;
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}
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/* Run wolfboot! */
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main();
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}
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/* This is the main loop for the bootloader.
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*
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* It performs the following actions:
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* - Call the application entry point
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*
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*/
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#ifdef MMU
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void RAMFUNCTION do_boot(const uint32_t *app_offset, const uint32_t* dts_offset)
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#else
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||||
void RAMFUNCTION do_boot(const uint32_t *app_offset)
|
||||
#endif
|
||||
{
|
||||
/* Set application address via r4 */
|
||||
asm volatile("mov r4, %0" : : "r"(app_offset));
|
||||
|
||||
#ifdef MMU
|
||||
/* Move the dts pointer to r5 (as first argument) */
|
||||
asm volatile("mov r5, %0" : : "r"(dts_offset));
|
||||
#else
|
||||
asm volatile("mov r5, 0");
|
||||
#endif
|
||||
|
||||
/* Zero registers r1, r2, r3 */
|
||||
asm volatile("mov r3, 0");
|
||||
asm volatile("mov r2, 0");
|
||||
asm volatile("mov r1, 0");
|
||||
|
||||
/* Move the dts pointer to r0 (as first argument) */
|
||||
asm volatile("mov r0, r5");
|
||||
|
||||
/* Unconditionally jump to app_entry at r4 */
|
||||
asm volatile("bx r4");
|
||||
}
|
||||
|
||||
#ifdef RAM_CODE
|
||||
|
||||
#define AIRCR *(volatile uint32_t *)(0xE000ED0C)
|
||||
#define AIRCR_VKEY (0r05FA << 16)
|
||||
#define AIRCR_SYSRESETREQ (1 << 2)
|
||||
|
||||
void RAMFUNCTION arch_reboot(void)
|
||||
{
|
||||
AIRCR = AIRCR_SYSRESETREQ | AIRCR_VKEY;
|
||||
while(1)
|
||||
;
|
||||
wolfBoot_panic();
|
||||
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/**
|
||||
* Arm32 (32bit Cortex-A) boot up
|
||||
* Copyright (C) 2024 wolfSSL Inc.
|
||||
*
|
||||
* This file is part of wolfBoot.
|
||||
*
|
||||
* wolfBoot is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* wolfBoot is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
|
||||
*/
|
||||
.section start
|
||||
.text
|
||||
|
||||
/* startup entry point */
|
||||
.globl reset_vector_entry
|
||||
.align 4
|
||||
reset_vector_entry:
|
||||
/* Exception vectors (should be a branch to be detected as a valid code by the rom */
|
||||
_exception_vectors:
|
||||
b isr_reset /* reset */
|
||||
b isr_empty /* Undefined Instruction */
|
||||
b isr_swi /* Software Interrupt */
|
||||
b isr_pabt /* Prefetch Abort */
|
||||
b dabt_vector /* Data Abort */
|
||||
.word _romsize /* Size of the binary for ROMCode loading */
|
||||
b isr_irq /* IRQ : read the AIC */
|
||||
b isr_fiq /* FIQ */
|
||||
|
||||
isr_empty:
|
||||
b isr_empty
|
||||
isr_swi:
|
||||
b isr_swi
|
||||
isr_pabt:
|
||||
b isr_pabt
|
||||
dabt_vector:
|
||||
subs pc, r14, #4 /* return */
|
||||
nop
|
||||
isr_rsvd:
|
||||
b isr_rsvd
|
||||
isr_irq:
|
||||
b isr_irq
|
||||
isr_fiq:
|
||||
b isr_fiq
|
||||
|
||||
|
||||
/* Reset handler procedure. Prepare the memory and call main() */
|
||||
isr_reset:
|
||||
/* Initialize the stack pointer */
|
||||
ldr sp,=_stack_top
|
||||
/* Save BootROM supplied boot source information to stack */
|
||||
push {r4}
|
||||
|
||||
/* Copy the data section */
|
||||
ldr r2, =_lp_data
|
||||
ldmia r2, {r1, r3, r4}
|
||||
1:
|
||||
cmp r3, r4
|
||||
ldrcc r2, [r1], #4
|
||||
strcc r2, [r3], #4
|
||||
bcc 1b
|
||||
|
||||
/* Zero bss area */
|
||||
adr r2, _lp_bss
|
||||
ldmia r2, {r3, r4}
|
||||
mov r2, #0
|
||||
1:
|
||||
cmp r3, r4
|
||||
strcc r2, [r3], #4
|
||||
bcc 1b
|
||||
|
||||
/* Jump to main() */
|
||||
ldr r4, = main
|
||||
mov lr, pc
|
||||
bx r4
|
||||
|
||||
/* main() should never return */
|
||||
_panic:
|
||||
b _panic
|
||||
|
||||
.align
|
||||
_lp_data:
|
||||
.word _start_data
|
||||
.word _end_data
|
||||
|
||||
_lp_bss:
|
||||
.word _start_bss
|
||||
.word _end_bss
|
||||
|
||||
Loading…
Reference in New Issue