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wolfBoot
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adjust UART settings and update readme

pull/714/head
Hideki Miyazaki 2026-03-12 13:48:16 +09:00 committed by Daniele Lacamera
parent fcf72e008c
commit 52223853c4
3 changed files with 25 additions and 6 deletions
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19
IDE/Renesas/e2studio/RA6M4/Readme.md
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@ -158,12 +158,29 @@ Key BSP settings configured above (`wolfBoot/ra_cfg/fsp_cfg/bsp/bsp_cfg.h`):
wolfBoot initialises the FACI HP directly; **no FSP flash stack (`g_flash0`) is required**.
To enable debug output over UART (SCI7, P613=TXD7, J23 connector), edit `wolfBoot/user_settings.h`:
#### 2-3) Enable Debug UART Output (optional)
Defining `DEBUG_UART` enables `wolfBoot_printf()` output over SCI7.
Edit `wolfBoot/user_settings.h` and uncomment both lines:
```c
#define DEBUG_UART
#define PRINTF_ENABLED
```
**UART channel and pin assignment (EK-RA6M4):**
| Signal | Port pin | Board connector | Note |
|:--|:--|:--|:--|
| TXD7 | P613 | J23 Pin2 (silk: TX►0) | Connect to RXD of USB-UART adapter |
| RXD7 | P614 | J23 Pin1 (silk: RX◄0) | Connect to TXD of USB-UART adapter |
| GND | — | J24 Pin7 | Common ground |
**Terminal settings:** 115200 bps, 8N1, no flow control.
> **Note**: SCI7 on RA6M4 uses **PCLKA (100 MHz)**, not PCLKB (50 MHz).
> The BRR value in `hal/renesas-ra.h` is calculated accordingly (`RA_PCLKA_SCI = 100000000U`).
#### 2-2) Modify wolfBoot hal_entry.c
`wolfBoot/src/hal_entry.c` is **not stored in the repository** (Renesas copyright, FSP-generated).

1
IDE/Renesas/e2studio/RA6M4/wolfBoot/user_settings.h
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@ -317,5 +317,4 @@
#define NVM_FLASH_WRITEONCE
/*#define DEBUG_UART*/
/*#define PRINTF_ENABLED*/
#endif /* !H_USER_SETTINGS_ */

11
hal/renesas-ra.h
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@ -125,17 +125,20 @@
#define PFS_PMR (1u << 16)
#define PFS_PDR (1u << 2)
#define PFS_PODR (1u << 0)
#define PFS_PSEL_SCI7 (0x05u << 24) /* PSEL=0x05: SCI1/3/5/7/9 odd channels */
#define PFS_PSEL_SCI7 (0x05u << 24) /* PSEL=0x05: SCI1/3/5/7/9 odd channels */
#define R_PMISC_PWPR REG8(0x40080D03UL)
#define PWPR_PFSWE (1u << 6)
#define PWPR_B0WI (1u << 7)
#ifndef DEBUG_BAUD_RATE
#define DEBUG_BAUD_RATE 115200U
#endif
#ifndef RA_PCLKB
#define RA_PCLKB 50000000U
/* SCI7 on RA6M4 is clocked by PCLKA (not PCLKB).
* Default EK-RA6M4 FSP config: PLL=200MHz, PCLKA Div/2 = 100MHz. */
#ifndef RA_PCLKA_SCI
#define RA_PCLKA_SCI 100000000U /* PCLKA = 100MHz */
#endif
#define SCI_BRR_VAL (RA_PCLKB / (8U * DEBUG_BAUD_RATE) - 1U)
/* BRR: BGDM=1, ABCS=1 -> divisor=8. 100MHz/(8*115200)-1 = 107 -> 115741bps */
#define SCI_BRR_VAL (RA_PCLKA_SCI / (8U * DEBUG_BAUD_RATE) - 1U)
/* --- Flash error codes (used by flash_check_error) --- */
typedef enum {
FLASH_OK = 0,