diff --git a/Makefile b/Makefile index 1e0c3c68..a39afe45 100644 --- a/Makefile +++ b/Makefile @@ -54,6 +54,11 @@ ifeq ($(TARGET),stm32l5) MAIN_TARGET:=wolfboot.bin test-app/image_v1_signed.bin endif +ifeq ($(TARGET),stm32u5) + # Don't build a contiguous image + MAIN_TARGET:=wolfboot.bin test-app/image_v1_signed.bin +endif + ifeq ($(TARGET),x86_64_efi) MAIN_TARGET:=wolfboot.efi endif diff --git a/arch.mk b/arch.mk index a9d2951d..e12fe0b6 100644 --- a/arch.mk +++ b/arch.mk @@ -124,6 +124,17 @@ ifeq ($(ARCH),ARM) endif endif + ifeq ($(TARGET),stm32u5) + CORTEX_M33=1 + CFLAGS+=-Ihal -DCORTEX_M33 + ARCH_FLASH_OFFSET=0x08000000 + ifeq ($(TZEN),1) + WOLFBOOT_ORIGIN=0x0C000000 + else + WOLFBOOT_ORIGIN=0x08000000 + endif + endif + ## Cortex-M CPU ifeq ($(CORTEX_M33),1) CFLAGS+=-mcpu=cortex-m33 diff --git a/config/examples/stm32u5-nonsecure-dualbank.config b/config/examples/stm32u5-nonsecure-dualbank.config new file mode 100644 index 00000000..8e511b05 --- /dev/null +++ b/config/examples/stm32u5-nonsecure-dualbank.config @@ -0,0 +1,26 @@ +ARCH?=ARM +TZEN?=0 +TARGET?=stm32u5 +SIGN?=ECC256 +HASH?=SHA256 +DEBUG?=1 +VTOR?=1 +CORTEX_M0?=0 +CORTEX_M33?=1 +NO_ASM?=0 +NO_MPU=1 +EXT_FLASH?=0 +SPI_FLASH?=0 +ALLOW_DOWNGRADE?=0 +NVM_FLASH_WRITEONCE?=1 +WOLFBOOT_VERSION?=1 +V?=0 +SPMATH?=1 +RAM_CODE?=0 +DUALBANK_SWAP?=1 +IMAGE_HEADER_SIZE?=256 +WOLFBOOT_PARTITION_SIZE?=0x38000 +WOLFBOOT_SECTOR_SIZE?=0x2000 +WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08008000 +WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08108000 +WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xFFFFFFFF \ No newline at end of file diff --git a/config/examples/stm32u5.config b/config/examples/stm32u5.config new file mode 100644 index 00000000..ecdd5912 --- /dev/null +++ b/config/examples/stm32u5.config @@ -0,0 +1,28 @@ +ARCH?=ARM +TZEN?=1 +TARGET?=stm32u5 +SIGN?=ECC256 +HASH?=SHA256 +DEBUG?=1 +VTOR?=1 +CORTEX_M0?=0 +CORTEX_M33?=1 +NO_ASM?=0 +NO_MPU=1 +EXT_FLASH?=0 +SPI_FLASH?=0 +ALLOW_DOWNGRADE?=0 +NVM_FLASH_WRITEONCE?=1 +WOLFBOOT_VERSION?=1 +V?=0 +SPMATH?=1 +RAM_CODE?=0 +DUALBANK_SWAP?=0 +IMAGE_HEADER_SIZE?=256 +WOLFBOOT_PARTITION_SIZE?=0x20000 +WOLFBOOT_SECTOR_SIZE?=0x2000 +WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08100000 +WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x817F000 +WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x81FE000 +FLAGS_HOME=0 +DISABLE_BACKUP=0 diff --git a/docs/Targets.md b/docs/Targets.md index 7905a710..006eef66 100644 --- a/docs/Targets.md +++ b/docs/Targets.md @@ -18,6 +18,7 @@ This README describes configuration of supported targets. * [STM32G0](#stm32g0) * [STM32H7](#stm32h7) * [STM32L5](#stm32l5) +* [STM32U5](#stm32u5) * [STM32L0](#stm32l0) * [STM32WB55](#stm32wb55) * [TI Hercules TMS570LC435](#ti-hercules-tms570lc435) @@ -103,11 +104,11 @@ Example 1MB partitioning on STM32L4 #### Example Description -The implementation shows how to switch from secure application to non-secure application -thanks to the system isolation performed to split the internal Flash and internal SRAM memories -into two halves: - - the first half for the secure application - - the second half for the non-secure application +The implementation shows how to switch from secure application to non-secure application, +thanks to the system isolation performed, which splits the internal Flash and internal +SRAM memories into two halves: + - the first half for secure application + - the second half for non-secure application #### Hardware and Software environment @@ -154,7 +155,7 @@ The flash memory is segmented into two different banks: - Bank 0: (0x08000000) - Bank 1: (0x08040000) -Bank 0 contains the bootloader at address 0x08000000, and the application at address 0x08008000. +Bank 0 contains the bootloader at address 0x08000000, and the application at address 0x08040000. When a valid image is available at the same offset in Bank 1, a candidate is selected for booting between the two valid images. A firmware update can be uploaded at address 0x08048000. @@ -200,7 +201,114 @@ arm-none-eabi-gdb add-symbol-file test-app/image.elf mon reset init ``` +## STM32U5 +### Scenario 1: TrustZone Enabled + +#### Example Description + +The implementation shows how to switch from secure application to non-secure application, +thanks to the system isolation performed, which splits the internal Flash and internal +SRAM memories into two halves: + - the first half for secure application + - the second half for non-secure application + +#### Hardware and Software environment + +- This example runs on STM32U585AII6Q devices with security enabled (TZEN=1). +- This example has been tested with STMicroelectronics B-U585I-IOT02A (MB1551) +- User Option Bytes requirement (with STM32CubeProgrammer tool - see below for instructions) + +``` +TZEN = 1 System with TrustZone-M enabled +DBANK = 1 Dual bank mode +SECWM1_PSTRT=0x0 SECWM1_PEND=0x7F All 128 pages of internal Flash Bank1 set as secure +SECWM2_PSTRT=0x1 SECWM2_PEND=0x0 No page of internal Flash Bank2 set as secure, hence Bank2 non-secure +``` + +- NOTE: STM32CubeProgrammer V2.8.0 or newer is required + +#### How to use it + +1. `cp ./config/examples/stm32u5.config .config` +2. `make TZEN=1` +3. Prepare board with option bytes configuration reported above + - `STM32_Programmer_CLI -c port=swd mode=hotplug -ob TZEN=1 DBANK=1` + - `STM32_Programmer_CLI -c port=swd mode=hotplug -ob SECWM1_PSTRT=0x0 SECWM1_PEND=0x7F SECWM2_PSTRT=0x1 SECWM2_PEND=0x0` +4. flash wolfBoot.bin to 0x0c00 0000 + - `STM32_Programmer_CLI -c port=swd -d ./wolfboot.bin 0x0C000000` +5. flash .\test-app\image_v1_signed.bin to 0x0804 0000 + - `STM32_Programmer_CLI -c port=swd -d ./test-app/image_v1_signed.bin 0x08100000` +6. RED LD9 will be on + +- NOTE: STM32_Programmer_CLI Default Locations +* Windows: `C:\Program Files\STMicroelectronics\STM32Cube\STM32CubeProgrammer\bin\STM32_Programmer_CLI.exe` +* Linux: `/usr/local/STMicroelectronics/STM32Cube/STM32CubeProgrammer/bin/STM32_Programmer_CLI` +* Mac OS/X: `/Applications/STMicroelectronics/STM32Cube/STM32CubeProgrammer/STM32CubeProgrammer.app/Contents/MacOs/bin/STM32_Programmer_CLI` + +### Scenario 2: TrustZone Disabled + +#### Example Description + +The implementation shows how to use STM32U5xx in DUAL_BANK mode, with TrustZone disabled. +The DUAL_BANK option is only available on this target when TrustZone is disabled (TZEN = 0). + +The flash memory is segmented into two different banks: + + - Bank 0: (0x08000000) + - Bank 1: (0x08100000) + +Bank 0 contains the bootloader at address 0x08000000, and the application at address 0x08100000. +When a valid image is available at the same offset in Bank 1, a candidate is selected for booting between the two valid images. +A firmware update can be uploaded at address 0x08108000. + +The example configuration is available in [/config/examples/stm32u5-nonsecure-dualbank.config](/config/examples/stm32u5-nonsecure-dualbank.config). + +To run flash `./test-app/image.bin` to `0x08000000`. + - `STM32_Programmer_CLI -c port=swd -d ./test-app/image.bin 0x08000000` + +Or program each partition using: +1. flash `wolfboot.bin` to 0x08000000: + - `STM32_Programmer_CLI -c port=swd -d ./wolfboot.elf` +2. flash `image_v1_signed.bin` to 0x08008000 + - `STM32_Programmer_CLI -c port=swd -d ./test-app/image_v1_signed.bin 0x08008000` + +RED LD9 will be on indicating successful boot () + +### Debugging + +Use `make DEBUG=1` and reload firmware. + +- STM32CubeIDE v.1.7.0 required +- Run the debugger via: + +Linux: + +``` +ST-LINK_gdbserver -d -cp /opt/st/stm32cubeide_1.3.0/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.linux64_1.3.0.202002181050/tools/bin -e -r 1 -p 3333` +``` + +Max OS/X: + +```sh +sudo ln -s /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.macos64_1.6.0.202101291314/tools/bin/native/mac_x64/libSTLinkUSBDriver.dylib /usr/local/lib/libSTLinkUSBDriver.dylib + +/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.macos64_1.6.0.202101291314/tools/bin/ST-LINK_gdbserver -d -cp ./Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.macos64_1.6.0.202101291314/tools/bin -e -r 1 -p 3333 +``` + +Win: + +``` +ST-LINK_gdbserver -d -cp C:\ST\STM32CubeIDE_1.7.0\STM32CubeIDE\plugins\com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.win32_2.0.0.202105311346\tools\bin -e -r 1 -p 3333` +``` +- Connect with arm-none-eabi-gdb + +wolfBoot has a .gdbinit to configure +``` +arm-none-eabi-gdb +add-symbol-file test-app/image.elf +mon reset init +``` ## STM32L0 diff --git a/hal/stm32l5_partition.h b/hal/stm32l5_partition.h index 017f20ea..8bbe6068 100644 --- a/hal/stm32l5_partition.h +++ b/hal/stm32l5_partition.h @@ -1,3 +1,24 @@ +/* stm32l5_partition.h + * + * Copyright (C) 2021 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + #ifndef STM32L5_PARTITION_H #define STM32L5_PARTITION_H diff --git a/hal/stm32u5.c b/hal/stm32u5.c new file mode 100644 index 00000000..a7dd8b05 --- /dev/null +++ b/hal/stm32u5.c @@ -0,0 +1,832 @@ +/* stm32u5.c + * + * Copyright (C) 2021 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#include +#include +#include +#include "stm32u5_partition.h" + +/* Assembly helpers */ +#define DMB() __asm__ volatile ("dmb") +#define ISB() __asm__ volatile ("isb") +#define DSB() __asm__ volatile ("dsb") + +/* STM32 U5 register configuration */ +/*** RCC ***/ +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/*Secure */ +#define RCC_BASE (0x56020C00) /* RM0456 - Table 4 */ +#else +/*Non-Secure */ +#define RCC_BASE (0x46020C00) /* RM0456 - Table 4 */ +#endif + +#define FLASH_SECURE_MMAP_BASE (0x0C000000) + +#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00)) /* RM0456 - Table 108 */ +#define RCC_CR_PLL3RDY (1 << 29) +#define RCC_CR_PLL3ON (1 << 28) +#define RCC_CR_PLL2RDY (1 << 27) +#define RCC_CR_PLL2ON (1 << 26) +#define RCC_CR_PLL1RDY (1 << 25) +#define RCC_CR_PLL1ON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +#define RCC_CR_HSIRDY (1 << 10) +#define RCC_CR_HSION (1 << 8) +#define RCC_CR_MSIPLLEN (1 << 3) +#define RCC_CR_MSIRDY (1 << 2) +#define RCC_CR_MSISON (1 << 0) + +#define RCC_CFGR1 (*(volatile uint32_t *)(RCC_BASE + 0x1C)) /* RM0456 - Table 108 */ +#define RCC_CFGR1_SWS (1 << 2) + +/*** APB1&2 PRESCALER ***/ +#define RCC_APB_PRESCALER_DIV_NONE 0x0 /* 0xx: HCLK not divided */ + +/*** AHB PRESCALER ***/ + #define RCC_AHB_PRESCALER_DIV_NONE 0x0 /* 0xxx: SYSCLK not divided */ + +#define RCC_CFGR_SW_MSI 0x0 +#define RCC_CFGR_SW_HSI16 0x1 +#define RCC_CFGR_SW_HSE 0x2 +#define RCC_CFGR_SW_PLL 0x3 + +#define RCC_CFGR2 (*(volatile uint32_t *)(RCC_BASE + 0x20)) /* RM0456 - Table 108 */ + +#define RCC_CFGR2_HPRE_SHIFT (0x00) +#define RCC_CFGR2_PPRE2_SHIFT (0x08) +#define RCC_CFGR2_PPRE1_SHIFT (0x04) + +#define RCC_CFGR3 (*(volatile uint32_t *)(RCC_BASE + 0x24)) /* RM0456 - Table 108 */ +#define RCC_CFGR3_PPRE3_SHIFT (0x04) + +#define RCC_PLL1CFGR (*(volatile uint32_t *)(RCC_BASE + 0x28)) /* RM0456 - Table 108 */ +#define RCC_PLL1CFGR_PLL1REN (1 << 18) +#define RCC_PLL1CFGR_PLL1QEN (1 << 17) +#define RCC_PLL1CFGR_PLL1PEN (1 << 16) +#define RCC_PLL1CFGR_PLL1FRACEN (1 << 4) +#define RCC_PLL1CFGR_PLL1RGE_SHIFT (2) +#define RCC_PLL1VCIRANGE_1 0x03 + +#define RCC_PLL1CFGR_PLLM_SHIFT (8) +#define RCC_PLL1CFGR_PLL1MBOOST_SHIFT (12) +#define RCC_PLL1CFGR_PLL1MBOOST_DIV4 0x02 + +#define RCC_PLLCKSELR_PLLSRC_NONE 0x0 +#define RCC_PLLCKSELR_PLLSRC_MSI 0x1 +#define RCC_PLLCKSELR_PLLSRC_HSI16 0x2 +#define RCC_PLLCKSELR_PLLSRC_HSE 0x3 + + +#define RCC_PLL1DIVR (*(volatile uint32_t *)(RCC_BASE + 0x34)) /* RM0456 - Table 108 */ +#define RCC_PLL1DIVR_PLLN_SHIFT (0) +#define RCC_PLL1DIVR_PLLP_SHIFT (9) +#define RCC_PLL1DIVR_PLLQ_SHIFT (16) +#define RCC_PLL1DIVR_PLLR_SHIFT (24) + +#define RCC_PLL1FRACR (*(volatile uint32_t *)(RCC_BASE + 0x38)) /* RM0456 - Table 108 */ +#define RCC_PLL1FRACR_SHIFT (3) + +#define RCC_CIER (*(volatile uint32_t *)(RCC_BASE + 0x50)) /* RM0456 - Table 108 */ + +#define RCC_AHB1ENR (*(volatile uint32_t *)(RCC_BASE + 0x88)) /* RM0456 - Table 108 */ +#define RCC_AHB1ENR_GTZC1EN (1 << 24) + +#define RCC_AHB3ENR (*(volatile uint32_t *)(RCC_BASE + 0x94)) /* RM0456 - Table 108 */ +#define RCC_AHB3ENR_GTZC2EN (1 << 12) +#define RCC_AHB3ENR_PWREN (1 << 2) + +#define RCC_ICSCR1 (*(volatile uint32_t *)(RCC_BASE + 0x08)) +#define RCC_ICSCR1_MSIRANGE_SHIFT (28) +#define RCC_ICSCR1_MSIRGSEL (1 << 23) +#define RCC_ICSCR1_MSIRG_0 (0) + +#define RCC_ICSCR2 (*(volatile uint32_t *)(RCC_BASE + 0x0C)) +#define RCC_ICSCR2_MSITRIM0_SHIFT (15) +#define RCC_ICSCR2_MSITRIM0_DEFAULT (0x10) + +#define RCC_ICSCR3 (*(volatile uint32_t *)(RCC_BASE + 0x10)) +#define RCC_ICSCR3_HSITRIM_SHIFT (16) +#define RCC_ICSCR3_HSITRIM_DEFAULT (0x10) + +/*** PWR ***/ +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/*Secure */ +#define PWR_BASE (0x56020800) /* RM0456 - Table 4 */ +#else +/*Non-Secure */ +#define PWR_BASE (0x46020800) /* RM0456 - Table 4 */ +#endif + +#define PWR_VOSR (*(volatile uint32_t *)(PWR_BASE + 0x0C)) +#define PWR_VOSR_BOOSTEN (1 << 18) +#define PWR_VOSR_VOS_SHIFT (16) +#define PWR_VOSR_VOS_4 (0x0) +#define PWR_VOSR_VOS_3 (0x1) +#define PWR_VOSR_VOS_2 (0x2) +#define PWR_VOSR_VOS_1 (0x3) + +#define PWR_VOSR_VOSRDY (1 << 15) +#define PWR_VOSR_BOOSTRDY (1 << 14) + +#define PWR_SVMCR (*(volatile uint32_t *)(PWR_BASE + 0x10)) +#define PWR_SVMCR_IOS2V (1 << 29) + +#define PWR_UCPDR (*(volatile uint32_t *)(PWR_BASE + 0x2C)) +#define PWR_UCPDR_DBDIS (1 << 0) + +/*** FLASH ***/ +#define SYSCFG_APB2_CLOCK_ER_VAL (1 << 0) /* <> - RCC_APB2ENR - SYSCFGEN */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/*Secure*/ +#define FLASH_BASE (0x50022000) /* RM0456 - Table 4 */ +#define FLASH_KEYR (*(volatile uint32_t *)(FLASH_BASE + 0x0C)) +#define FLASH_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x10)) +#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x24)) +#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x2C)) + +#define FLASH_SECBB1 ((volatile uint32_t *)(FLASH_BASE + 0x80)) /* Array */ +#define FLASH_SECBB2 ((volatile uint32_t *)(FLASH_BASE + 0xA0)) /* Array */ +#define FLASH_SECBB_NREGS 4 /* Array length for the two above */ + +#define FLASH_NS_BASE (0x40022000) /* RM0456 - Table 4 */ +#define FLASH_NS_KEYR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x08)) +#define FLASH_NS_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x10)) +#define FLASH_NS_SR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x20)) +#define FLASH_NS_CR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x28)) + + + +#else +/* Non-Secure only */ +#define FLASH_BASE (0x40022000) /* RM0456 - Table 4 */ +#define FLASH_NS_KEYR (*(volatile uint32_t *)(FLASH_BASE + 0x08)) +#define FLASH_NS_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x10)) +#define FLASH_NS_SR (*(volatile uint32_t *)(FLASH_BASE + 0x20)) +#define FLASH_NS_CR (*(volatile uint32_t *)(FLASH_BASE + 0x28)) +#endif + +/* Register values (for both secure and non secure registers) */ +#define FLASH_SR_EOP (1 << 0) +#define FLASH_SR_OPERR (1 << 1) +#define FLASH_SR_PROGERR (1 << 3) +#define FLASH_SR_WRPERR (1 << 4) +#define FLASH_SR_PGAERR (1 << 5) +#define FLASH_SR_SIZERR (1 << 6) +#define FLASH_SR_PGSERR (1 << 7) +#define FLASH_SR_OPTWERR (1 << 13) +#define FLASH_SR_BSY (1 << 16) +#define FLASH_SR_WDW (1 << 17) + +#define FLASH_CR_PG (1 << 0) +#define FLASH_CR_PER (1 << 1) +#define FLASH_CR_MER1 (1 << 2) +#define FLASH_CR_PNB_SHIFT 3 +#define FLASH_CR_PNB_MASK 0x7F +#define FLASH_CR_BKER (1 << 11) +#define FLASH_CR_MER2 (1 << 15) +#define FLASH_CR_STRT (1 << 16) +#define FLASH_CR_OPTSTRT (1 << 17) +#define FLASH_CR_EOPIE (1 << 24) +#define FLASH_CR_ERRIE (1 << 25) +#define FLASH_CR_OBL_LAUNCH (1 << 27) +#define FLASH_CR_INV (1 << 29) +#define FLASH_CR_OPTLOCK (1 << 30) +#define FLASH_CR_LOCK (1 << 31) + + +#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00)) +#define FLASH_ACR_LATENCY_MASK (0x0F) +#define FLASH_ACR_PRFTEN (1<<8) + +#define FLASH_OPTR (*(volatile uint32_t *)(FLASH_BASE + 0x40)) +#define FLASH_OPTR_DBANK (1 << 21) +#define FLASH_OPTR_SWAP_BANK (1 << 20) + +#define FLASHMEM_ADDRESS_SPACE (0x08000000) +#define FLASH_PAGE_SIZE (0x2000) /* 8KB */ +#define FLASH_BANK2_BASE (0x08100000) /*!< Base address of Flash Bank2 */ +#define BOOTLOADER_SIZE (0x8000) +#define FLASH_TOP (0x081FFFFF) /*!< FLASH end address */ + +#define FLASH_KEY1 (0x45670123) +#define FLASH_KEY2 (0xCDEF89AB) +#define FLASH_OPTKEY1 (0x08192A3BU) +#define FLASH_OPTKEY2 (0x4C5D6E7FU) + +/* GPIO*/ +#define GPIOH_BASE 0x52021C00 + +#define GPIOH_SECCFGR (*(volatile uint32_t *)(GPIOH_BASE + 0x30)) + +#define LED_BOOT_PIN (7) /* PH7 - Discovery - Green Led */ +#define LED_USR_PIN (6) /* PH6 - Discovery - Red Led */ + +#define RCC_AHB2ENR1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C )) +#define GPIOH_AHB2ENR1_CLOCK_ER (1 << 7) + +/* Reset */ +#define OPTR_SWAP_BANK (1 << 20) + +#define AIRCR *(volatile uint32_t *)(0xE000ED0C) +#define AIRCR_VKEY (0x05FA << 16) +#define AIRCR_SYSRESETREQ (1 << 2) + + +static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates) +{ + uint32_t reg = FLASH_ACR; + if ((reg & FLASH_ACR_LATENCY_MASK) != waitstates) + FLASH_ACR = (reg & ~FLASH_ACR_LATENCY_MASK) | waitstates; +} + +static RAMFUNCTION void flash_wait_complete(uint8_t bank) +{ + while ((FLASH_NS_SR & (FLASH_SR_BSY | FLASH_SR_WDW)) != 0) + ; +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) + while ((FLASH_SR & (FLASH_SR_BSY | FLASH_SR_WDW)) != 0) + ; +#endif + +} + +static void RAMFUNCTION flash_clear_errors(uint8_t bank) +{ + + FLASH_NS_SR |= (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR | + FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR +#if !(defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) + | FLASH_SR_OPTWERR +#endif + ); +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) + FLASH_SR |= (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR | + FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR | + FLASH_SR_OPTWERR); +#endif + +} + +int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len) +{ + int i = 0; + uint32_t *src, *dst; + uint32_t qword[4]; + volatile uint32_t *sr, *cr; + + flash_clear_errors(0); + src = (uint32_t*)data; + dst = (uint32_t*)address; + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((((FLASH_OPTR & FLASH_OPTR_DBANK) == 0) && (address <= FLASH_TOP)) || (address < FLASH_BANK2_BASE)) { + cr = &FLASH_CR; + sr = &FLASH_SR; + /* Convert into secure address space */ + dst = (uint32_t *)((address & (~FLASHMEM_ADDRESS_SPACE)) | FLASH_SECURE_MMAP_BASE); + } + else if (address >= (FLASH_BANK2_BASE) && (address <= (FLASH_TOP) )) { + cr = &FLASH_NS_CR; + sr = &FLASH_NS_SR; + } + else { + return 0; /* Address out of range */ + } +#else + cr = &FLASH_NS_CR; + sr = &FLASH_NS_SR; +#endif + + while (i < len) { + qword[0] = src[i >> 2]; + qword[1] = src[(i >> 2) + 1]; + qword[2] = src[(i >> 2) + 2]; + qword[3] = src[(i >> 2) + 3]; + *cr |= FLASH_CR_PG; + dst[i >> 2] = qword[0]; + ISB(); + dst[(i >> 2) + 1] = qword[1]; + ISB(); + dst[(i >> 2) + 2] = qword[2]; + ISB(); + dst[(i >> 2) + 3] = qword[3]; + ISB(); + flash_wait_complete(0); + if ((*sr & FLASH_SR_EOP) != 0) + *sr |= FLASH_SR_EOP; + *cr &= ~FLASH_CR_PG; + i += 16; + } + + return 0; +} + +void RAMFUNCTION hal_flash_unlock(void) +{ + flash_wait_complete(0); +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) + if ((FLASH_CR & FLASH_CR_LOCK) != 0) { + FLASH_KEYR = FLASH_KEY1; + DMB(); + FLASH_KEYR = FLASH_KEY2; + DMB(); + while ((FLASH_CR & FLASH_CR_LOCK) != 0) + ; + } +#endif + if ((FLASH_NS_CR & FLASH_CR_LOCK) != 0) { + FLASH_NS_KEYR = FLASH_KEY1; + DMB(); + FLASH_NS_KEYR = FLASH_KEY2; + DMB(); + while ((FLASH_NS_CR & FLASH_CR_LOCK) != 0) + ; + } +} + +void RAMFUNCTION hal_flash_lock(void) +{ + flash_wait_complete(0); +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) + if ((FLASH_CR & FLASH_CR_LOCK) == 0) + FLASH_CR |= FLASH_CR_LOCK; +#endif + if ((FLASH_NS_CR & FLASH_CR_LOCK) == 0) + FLASH_NS_CR |= FLASH_CR_LOCK; +} + +void RAMFUNCTION hal_flash_opt_unlock(void) +{ + flash_wait_complete(0); + + if ((FLASH_NS_CR & FLASH_CR_OPTLOCK) != 0) { + FLASH_NS_OPTKEYR = FLASH_OPTKEY1; + DMB(); + FLASH_NS_OPTKEYR = FLASH_OPTKEY2; + DMB(); + while ((FLASH_NS_CR & FLASH_CR_LOCK) != 0) + ; + } +} + +void RAMFUNCTION hal_flash_opt_lock(void) +{ + + FLASH_NS_CR |= FLASH_CR_OPTSTRT; + flash_wait_complete(0); + FLASH_NS_CR |= FLASH_CR_OBL_LAUNCH; + if ((FLASH_NS_CR & FLASH_CR_OPTLOCK) == 0) + FLASH_NS_CR |= FLASH_CR_OPTLOCK; +} + +int RAMFUNCTION hal_flash_erase(uint32_t address, int len) +{ + uint32_t end_address; + uint32_t p; + volatile uint32_t *cr; + + flash_clear_errors(0); + if (len == 0) + return -1; + + if (address < ARCH_FLASH_OFFSET) + return -1; + + end_address = address + len - 1; + for (p = address; p < end_address; p += FLASH_PAGE_SIZE) { + uint32_t reg; + uint32_t base; + uint32_t bker = 0; + cr = &FLASH_NS_CR; + + if ((((FLASH_OPTR & FLASH_OPTR_DBANK) == 0) && (p <= FLASH_TOP)) || (p < FLASH_BANK2_BASE)) { +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + cr = &FLASH_CR; +#endif + base = FLASHMEM_ADDRESS_SPACE; + } + else if (p >= (FLASH_BANK2_BASE) && (p <= (FLASH_TOP) )) { + bker = FLASH_CR_BKER; + base = FLASH_BANK2_BASE; + } + else { + *cr &= ~FLASH_CR_PER ; + return 0; /* Address out of range */ + } + reg = *cr & (~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT) | FLASH_CR_BKER)); + reg |= ((((p - base) >> 13) << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER | bker ); + *cr = reg; + DMB(); + *cr |= FLASH_CR_STRT; + flash_wait_complete(0); + } + /* If the erase operation is completed, disable the associated bits */ + *cr &= ~FLASH_CR_PER ; + return 0; +} + +static void clock_pll_off(void) +{ + uint32_t reg32, flash_waitstates ; + + /* Select MSI as SYSCLK source. */ + reg32 = RCC_CFGR1; + reg32 &= ~((1 << 1) | (1 << 0)); + RCC_CFGR1 = (reg32 | RCC_CFGR_SW_MSI); + DMB(); + + /* Wait for MSI clock to be selected. */ + while ((RCC_CFGR1 & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_MSI) {}; + + flash_waitstates = 1; + flash_set_waitstates(flash_waitstates); + + /* Turn off PLL */ + RCC_CR &= ~RCC_CR_HSION; + RCC_CR &= ~RCC_CR_PLL1ON; + DMB(); +} + +/* This implementation will setup MSI 48 MHz as PLL Source Mux, PLLCLK as + * System Clock Source */ +static void clock_pll_on(int powersave) +{ + uint32_t reg32; + uint32_t pll1n, pll1m, pll1mboost, pll1q, pll1p, pll1r, pll1fracn, pll1rge; + uint32_t hpre, apb1pre, apb2pre, apb3pre, flash_waitstates; + + /* Reset the RCC clock configuration to the default reset state ----------*/ + /* Set MSION bit */ + RCC_CR = RCC_CR_MSISON; + + /* Reset CFGR register */ + RCC_CFGR1 = 0U; + RCC_CFGR2 = 0U; + RCC_CFGR3 = 0U; + + /* Reset HSEON, CSSON , HSION, PLLxON bits */ + RCC_CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); + + /* Reset PLLCFGR register */ + RCC_PLL1CFGR = 0U; + + /* Reset HSEBYP bit */ + RCC_CR &= ~(RCC_CR_HSEBYP); + + /* Disable all interrupts */ + RCC_CIER = 0U; + + SCB_VTOR = FLASH_SECURE_MMAP_BASE; /* Vector Table Relocation in Internal FLASH */ + + FLASH_ACR|=FLASH_ACR_PRFTEN; + + RCC_AHB3ENR |= RCC_AHB3ENR_PWREN; + RCC_AHB1ENR |= RCC_AHB1ENR_GTZC1EN; + RCC_AHB3ENR |= RCC_AHB3ENR_GTZC2EN; + + PWR_UCPDR |= PWR_UCPDR_DBDIS; + + PWR_SVMCR |= PWR_SVMCR_IOS2V; + PWR_VOSR &= ~( (PWR_VOSR_VOS_1 << PWR_VOSR_VOS_SHIFT) | PWR_VOSR_BOOSTEN ); + PWR_VOSR|= ((PWR_VOSR_VOS_1<< PWR_VOSR_VOS_SHIFT) | PWR_VOSR_BOOSTEN); + + /* Wait until VOSRDY is rised */ + reg32 = PWR_VOSR; + while ((PWR_VOSR & PWR_VOSR_VOSRDY) == 0) {}; + + RCC_ICSCR1|= RCC_ICSCR1_MSIRGSEL; + reg32 = RCC_ICSCR1; + reg32 &= ~( (0xF << RCC_ICSCR1_MSIRANGE_SHIFT)); + reg32|= (RCC_ICSCR1_MSIRG_0 << RCC_ICSCR1_MSIRANGE_SHIFT); + RCC_ICSCR1 = reg32; + reg32 = RCC_ICSCR1; + DMB(); + + /* Adjusts the Multiple Speed oscillator (MSI) calibration value */ + reg32 = RCC_ICSCR2; + reg32 &= ~((0x1F << RCC_ICSCR2_MSITRIM0_SHIFT)); + reg32 |= (RCC_ICSCR2_MSITRIM0_DEFAULT << RCC_ICSCR2_MSITRIM0_SHIFT); + RCC_ICSCR2 = reg32; + reg32 = RCC_ICSCR2; + DMB(); + + flash_waitstates = 1; + flash_set_waitstates(flash_waitstates); + + /*----------------------------- HSI Configuration ------------------------*/ + /* Enable the Internal High Speed oscillator (HSI) */ + RCC_CR |= RCC_CR_HSION; + /* Wait till HSI is ready */ + while ((RCC_CR & RCC_CR_HSIRDY) == 0) {}; + /* Adjusts the Internal High Speed oscillator (HSI) calibration value */ + reg32 = RCC_ICSCR3; + reg32 &= ~((1 << 20) | (1 << 19) | (1 << 18) | (1 << 17) | (1 << 16) ); + reg32 |= (RCC_ICSCR3_HSITRIM_DEFAULT << RCC_ICSCR3_HSITRIM_SHIFT); + RCC_ICSCR3 = reg32; + reg32 = RCC_ICSCR3; + DMB(); + + /*-------------------------------- PLL Configuration ---------------------*/ + + /* Select clock parameters (CPU Speed = 160 MHz) */ + pll1m = 3; + pll1mboost = RCC_PLL1CFGR_PLL1MBOOST_DIV4; + pll1n = 10; + pll1p = 2; + pll1q = 2; + pll1r = 1; + pll1fracn = 0; + pll1rge = RCC_PLL1VCIRANGE_1; + hpre = RCC_AHB_PRESCALER_DIV_NONE; + apb1pre = RCC_APB_PRESCALER_DIV_NONE; + apb2pre = RCC_APB_PRESCALER_DIV_NONE; + apb3pre = RCC_APB_PRESCALER_DIV_NONE; + + /* Disable the main PLL */ + RCC_CR &= ~RCC_CR_PLL1ON; + + /* Wait till PLL is ready */ + while ((RCC_CR & RCC_CR_PLL1RDY) != 0) {}; + + /* Enable PWR CLK */ + RCC_AHB3ENR|= RCC_AHB3ENR_PWREN; + + /*Disable EPOD to configure PLL1MBOOST*/ + PWR_VOSR &= ~PWR_VOSR_BOOSTEN; + + /* Configure the main PLL clock source, multiplication and division factors */ + reg32 = RCC_PLL1CFGR ; + reg32 &= ~((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12) | (1 << 11) | + (1 << 10) | (1 << 9) | (1 << 8) | (1 << 1) | (1 << 0)); + reg32 |= RCC_PLLCKSELR_PLLSRC_MSI; + reg32 |= ((pll1m-1) << RCC_PLL1CFGR_PLLM_SHIFT); + reg32 |= ((pll1mboost) << RCC_PLL1CFGR_PLL1MBOOST_SHIFT); + RCC_PLL1CFGR = reg32; + + reg32 =0; + reg32 |= ((pll1n-1) << RCC_PLL1DIVR_PLLN_SHIFT); + reg32 |= ((pll1p-1) << RCC_PLL1DIVR_PLLP_SHIFT); + reg32 |= ((pll1q-1) << RCC_PLL1DIVR_PLLQ_SHIFT); + reg32 |= ((pll1r-1) << RCC_PLL1DIVR_PLLR_SHIFT); + RCC_PLL1DIVR = reg32; + DMB(); + + /* Disable PLL1FRACN */ + RCC_PLL1CFGR&= ~RCC_PLL1CFGR_PLL1FRACEN; + + /* Configure PLL PLL1FRACN */ + reg32 = RCC_PLL1FRACR ; + reg32 &= ~((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12) | (1 << 11) | + (1 << 10) | (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) | + (1 << 5) | (1 << 4) | (1 << 3)); + reg32 |= ((pll1fracn) << RCC_PLL1FRACR_SHIFT); + RCC_PLL1FRACR = reg32; + + /* Enable PLL1FRACN */ + RCC_PLL1CFGR|= RCC_PLL1CFGR_PLL1FRACEN; + + /* Select PLL1 input reference frequency range: VCI */ + reg32 = RCC_PLL1CFGR ; + reg32 &= ~((1 << 3) | (1 << 2)); + reg32 |= ((pll1rge) << RCC_PLL1CFGR_PLL1RGE_SHIFT); + RCC_PLL1CFGR = reg32; + + /* Enable the EPOD to reach max frequency */ + PWR_VOSR |= PWR_VOSR_BOOSTEN; + + /* Disable PWR clk */ + RCC_AHB3ENR&=~RCC_AHB3ENR_PWREN; + + /* Enable PLL System Clock output */ + RCC_PLL1CFGR|=RCC_PLL1CFGR_PLL1REN; + + /* Enable the main PLL */ + RCC_CR|=RCC_CR_PLL1ON; + + /* Wait till PLL is ready */ + while ((RCC_CR & RCC_CR_PLL1RDY) == 0) {}; + + /* Increasing the number of wait states because of higher CPU frequency */ + flash_waitstates = 4; + flash_set_waitstates(flash_waitstates); + + /* Enable PWR CLK */ + RCC_AHB3ENR|= RCC_AHB3ENR_PWREN; + + /* Wait till BOOST is ready */ + while ((PWR_VOSR & PWR_VOSR_BOOSTRDY) == 0) {}; + + /*Disable PWR clk */ + RCC_AHB3ENR&=~RCC_AHB3ENR_PWREN; + + /* Select PLL as SYSCLK source. */ + reg32 = RCC_CFGR1; + reg32 &= ~((1 << 1) | (1 << 0)); + RCC_CFGR1 = (reg32 | RCC_CFGR_SW_PLL); + DMB(); + + /* Wait for PLL clock to be selected. */ + while ((RCC_CFGR1 & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_PLL) {}; + + /* HCLK Configuration */ + reg32 = RCC_CFGR2 ; + reg32 &= ~((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); + reg32 |= hpre; + RCC_CFGR2 = reg32; + DMB(); + + /* PRE1 and PRE2 conf */ + reg32 = RCC_CFGR2 ; + reg32 &= ~((1 << 6) | (1 << 5) | (1 << 4)); + reg32 |= ((apb1pre) << RCC_CFGR2_PPRE1_SHIFT) ; + reg32 &= ~((1 << 10) | (1 << 9) | (1 << 8)); + reg32 |= ((apb2pre) << RCC_CFGR2_PPRE2_SHIFT) ; + RCC_CFGR2 = reg32; + DMB(); + + /* PRE3 conf */ + reg32 = RCC_CFGR3; + reg32 &= ~((1 << 6) | (1 << 5) | (1 << 4)); + reg32 |= ((apb3pre) << RCC_CFGR3_PPRE3_SHIFT) ; + RCC_CFGR3 = reg32; + DMB(); + + /* Disable PWR clk */ + RCC_AHB3ENR&=~RCC_AHB3ENR_PWREN; +} + +static void gtzc_init(void) +{ + /* configure SRAM3 - SECCFGR */ + SET_GTZC1_MPCBBx_SECCFGR(3,0); + SET_GTZC1_MPCBBx_SECCFGR(3,1); + SET_GTZC1_MPCBBx_SECCFGR(3,2); + SET_GTZC1_MPCBBx_SECCFGR(3,3); + SET_GTZC1_MPCBBx_SECCFGR(3,4); + SET_GTZC1_MPCBBx_SECCFGR(3,5); + SET_GTZC1_MPCBBx_SECCFGR(3,6); + SET_GTZC1_MPCBBx_SECCFGR(3,7); + SET_GTZC1_MPCBBx_SECCFGR(3,8); + SET_GTZC1_MPCBBx_SECCFGR(3,9); + SET_GTZC1_MPCBBx_SECCFGR(3,10); + SET_GTZC1_MPCBBx_SECCFGR(3,11); + SET_GTZC1_MPCBBx_SECCFGR(3,12); + SET_GTZC1_MPCBBx_SECCFGR(3,13); + SET_GTZC1_MPCBBx_SECCFGR(3,14); + SET_GTZC1_MPCBBx_SECCFGR(3,15); + SET_GTZC1_MPCBBx_SECCFGR(3,16); + SET_GTZC1_MPCBBx_SECCFGR(3,17); + SET_GTZC1_MPCBBx_SECCFGR(3,18); + SET_GTZC1_MPCBBx_SECCFGR(3,19); + SET_GTZC1_MPCBBx_SECCFGR(3,20); + SET_GTZC1_MPCBBx_SECCFGR(3,21); + SET_GTZC1_MPCBBx_SECCFGR(3,22); + SET_GTZC1_MPCBBx_SECCFGR(3,23); + SET_GTZC1_MPCBBx_SECCFGR(3,24); + SET_GTZC1_MPCBBx_SECCFGR(3,25); + SET_GTZC1_MPCBBx_SECCFGR(3,26); + SET_GTZC1_MPCBBx_SECCFGR(3,27); + SET_GTZC1_MPCBBx_SECCFGR(3,28); + SET_GTZC1_MPCBBx_SECCFGR(3,29); + SET_GTZC1_MPCBBx_SECCFGR(3,30); + SET_GTZC1_MPCBBx_SECCFGR(3,31); + + /* configure SRAM3 - PRIVCFGR */ + SET_GTZC1_MPCBBx_PRIVCFGR(3,0); + SET_GTZC1_MPCBBx_PRIVCFGR(3,1); + SET_GTZC1_MPCBBx_PRIVCFGR(3,2); + SET_GTZC1_MPCBBx_PRIVCFGR(3,3); + SET_GTZC1_MPCBBx_PRIVCFGR(3,4); + SET_GTZC1_MPCBBx_PRIVCFGR(3,5); + SET_GTZC1_MPCBBx_PRIVCFGR(3,6); + SET_GTZC1_MPCBBx_PRIVCFGR(3,7); + SET_GTZC1_MPCBBx_PRIVCFGR(3,8); + SET_GTZC1_MPCBBx_PRIVCFGR(3,9); + SET_GTZC1_MPCBBx_PRIVCFGR(3,10); + SET_GTZC1_MPCBBx_PRIVCFGR(3,11); + SET_GTZC1_MPCBBx_PRIVCFGR(3,12); + SET_GTZC1_MPCBBx_PRIVCFGR(3,13); + SET_GTZC1_MPCBBx_PRIVCFGR(3,14); + SET_GTZC1_MPCBBx_PRIVCFGR(3,15); + SET_GTZC1_MPCBBx_PRIVCFGR(3,16); + SET_GTZC1_MPCBBx_PRIVCFGR(3,17); + SET_GTZC1_MPCBBx_PRIVCFGR(3,18); + SET_GTZC1_MPCBBx_PRIVCFGR(3,19); + SET_GTZC1_MPCBBx_PRIVCFGR(3,20); + SET_GTZC1_MPCBBx_PRIVCFGR(3,21); + SET_GTZC1_MPCBBx_PRIVCFGR(3,22); + SET_GTZC1_MPCBBx_PRIVCFGR(3,23); + SET_GTZC1_MPCBBx_PRIVCFGR(3,24); + SET_GTZC1_MPCBBx_PRIVCFGR(3,25); + SET_GTZC1_MPCBBx_PRIVCFGR(3,26); + SET_GTZC1_MPCBBx_PRIVCFGR(3,27); + SET_GTZC1_MPCBBx_PRIVCFGR(3,28); + SET_GTZC1_MPCBBx_PRIVCFGR(3,29); + SET_GTZC1_MPCBBx_PRIVCFGR(3,30); + SET_GTZC1_MPCBBx_PRIVCFGR(3,31); +} + +static void RAMFUNCTION stm32u5_reboot(void) +{ + AIRCR = AIRCR_SYSRESETREQ | AIRCR_VKEY; + while(1) + ; +} + +void RAMFUNCTION hal_flash_dualbank_swap(void) +{ + uint32_t cur_opts; + hal_flash_unlock(); + hal_flash_opt_unlock(); + cur_opts = (FLASH_OPTR & FLASH_OPTR_SWAP_BANK) >> 20; + if (cur_opts) + FLASH_OPTR &= (~FLASH_OPTR_SWAP_BANK); + else + FLASH_OPTR |= FLASH_OPTR_SWAP_BANK; + hal_flash_opt_lock(); + hal_flash_lock(); + stm32u5_reboot(); +} + +static void led_unsecure() +{ + uint32_t pin; + + /* Enable clock for User LED GPIOs */ + RCC_AHB2ENR1_CLOCK_ER|= GPIOH_AHB2ENR1_CLOCK_ER; + + /* Un-secure User LED GPIO pins */ + GPIOH_SECCFGR&=~(1< FLASH + .edidx : + { + . = ALIGN(4); + *(.ARM.exidx*) + } > FLASH + + + _stored_data = .; + .data : AT (_stored_data) + { + _start_data = .; + KEEP(*(.data*)) + . = ALIGN(8); + KEEP(*(.ramcode)) + . = ALIGN(8); + _end_data = .; + } > RAM + + .bss (NOLOAD) : + { + _start_bss = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + _end_bss = .; + __bss_end__ = .; + _end = .; + } > RAM + . = ALIGN(8); + +} + +END_STACK = ORIGIN(RAM) + LENGTH(RAM); diff --git a/hal/stm32u5_ns.c b/hal/stm32u5_ns.c new file mode 100644 index 00000000..f1f2f528 --- /dev/null +++ b/hal/stm32u5_ns.c @@ -0,0 +1,560 @@ +/* stm32u5_ns.c + * + * Copyright (C) 2021 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#include +#include +#include +#include "stm32u5_partition.h" + +/* Assembly helpers */ +#define DMB() __asm__ volatile ("dmb") +#define ISB() __asm__ volatile ("isb") +#define DSB() __asm__ volatile ("dsb") + +/* STM32 U5 register configuration */ +/*** RCC ***/ +/*!< Memory & Instance aliases and base addresses for Non-Secure peripherals */ +/*Non-Secure */ +#define RCC_BASE (0x46020C00) /* RM0456 - Table 4 */ + +#define FLASH_SECURE_MMAP_BASE (0x0C000000) + +#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00)) /* RM0456 - Table 108 */ +#define RCC_CR_PLL3RDY (1 << 29) +#define RCC_CR_PLL3ON (1 << 28) +#define RCC_CR_PLL2RDY (1 << 27) +#define RCC_CR_PLL2ON (1 << 26) +#define RCC_CR_PLL1RDY (1 << 25) +#define RCC_CR_PLL1ON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +#define RCC_CR_HSIRDY (1 << 10) +#define RCC_CR_HSION (1 << 8) +#define RCC_CR_MSIPLLEN (1 << 3) +#define RCC_CR_MSIRDY (1 << 2) +#define RCC_CR_MSISON (1 << 0) + +#define RCC_CFGR1 (*(volatile uint32_t *)(RCC_BASE + 0x1C)) /* RM0456 - Table 108 */ +#define RCC_CFGR1_SWS (1 << 2) + +/*** APB1&2 PRESCALER ***/ +#define RCC_APB_PRESCALER_DIV_NONE 0x0 /* 0xx: HCLK not divided */ + +/*** AHB PRESCALER ***/ + #define RCC_AHB_PRESCALER_DIV_NONE 0x0 /* 0xxx: SYSCLK not divided */ + +#define RCC_CFGR_SW_MSI 0x0 +#define RCC_CFGR_SW_HSI16 0x1 +#define RCC_CFGR_SW_HSE 0x2 +#define RCC_CFGR_SW_PLL 0x3 + +#define RCC_CFGR2 (*(volatile uint32_t *)(RCC_BASE + 0x20)) /* RM0456 - Table 108 */ + +#define RCC_CFGR2_HPRE_SHIFT (0x00) +#define RCC_CFGR2_PPRE2_SHIFT (0x08) +#define RCC_CFGR2_PPRE1_SHIFT (0x04) + +#define RCC_CFGR3 (*(volatile uint32_t *)(RCC_BASE + 0x24)) /* RM0456 - Table 108 */ +#define RCC_CFGR3_PPRE3_SHIFT (0x04) + +#define RCC_PLL1CFGR (*(volatile uint32_t *)(RCC_BASE + 0x28)) /* RM0456 - Table 108 */ +#define RCC_PLL1CFGR_PLL1REN (1 << 18) +#define RCC_PLL1CFGR_PLL1QEN (1 << 17) +#define RCC_PLL1CFGR_PLL1PEN (1 << 16) +#define RCC_PLL1CFGR_PLL1FRACEN (1 << 4) +#define RCC_PLL1CFGR_PLL1RGE_SHIFT (2) +#define RCC_PLL1VCIRANGE_1 0x03 + +#define RCC_PLL1CFGR_PLLM_SHIFT (8) +#define RCC_PLL1CFGR_PLL1MBOOST_SHIFT (12) +#define RCC_PLL1CFGR_PLL1MBOOST_DIV4 0x02 + +#define RCC_PLLCKSELR_PLLSRC_NONE 0x0 +#define RCC_PLLCKSELR_PLLSRC_MSI 0x1 +#define RCC_PLLCKSELR_PLLSRC_HSI16 0x2 +#define RCC_PLLCKSELR_PLLSRC_HSE 0x3 + + +#define RCC_PLL1DIVR (*(volatile uint32_t *)(RCC_BASE + 0x34)) /* RM0456 - Table 108 */ +#define RCC_PLL1DIVR_PLLN_SHIFT (0) +#define RCC_PLL1DIVR_PLLP_SHIFT (9) +#define RCC_PLL1DIVR_PLLQ_SHIFT (16) +#define RCC_PLL1DIVR_PLLR_SHIFT (24) + +#define RCC_PLL1FRACR (*(volatile uint32_t *)(RCC_BASE + 0x38)) /* RM0456 - Table 108 */ +#define RCC_PLL1FRACR_SHIFT (3) + +#define RCC_CIER (*(volatile uint32_t *)(RCC_BASE + 0x50)) /* RM0456 - Table 108 */ + +#define RCC_AHB1ENR (*(volatile uint32_t *)(RCC_BASE + 0x88)) /* RM0456 - Table 108 */ +#define RCC_AHB1ENR_GTZC1EN (1 << 24) + +#define RCC_AHB3ENR (*(volatile uint32_t *)(RCC_BASE + 0x94)) /* RM0456 - Table 108 */ +#define RCC_AHB3ENR_GTZC2EN (1 << 12) +#define RCC_AHB3ENR_PWREN (1 << 2) + +#define RCC_ICSCR1 (*(volatile uint32_t *)(RCC_BASE + 0x08)) +#define RCC_ICSCR1_MSIRANGE_SHIFT (28) +#define RCC_ICSCR1_MSIRGSEL (1 << 23) +#define RCC_ICSCR1_MSIRG_0 (0) + +#define RCC_ICSCR2 (*(volatile uint32_t *)(RCC_BASE + 0x0C)) +#define RCC_ICSCR2_MSITRIM0_SHIFT (15) +#define RCC_ICSCR2_MSITRIM0_DEFAULT (0x10) + +#define RCC_ICSCR3 (*(volatile uint32_t *)(RCC_BASE + 0x10)) +#define RCC_ICSCR3_HSITRIM_SHIFT (16) +#define RCC_ICSCR3_HSITRIM_DEFAULT (0x10) + +/*** PWR ***/ +/*!< Memory & Instance aliases and base addresses for Non-Secure peripherals */ +#define PWR_BASE (0x46020800) /* RM0456 - Table 4 */ + +#define PWR_VOSR (*(volatile uint32_t *)(PWR_BASE + 0x0C)) +#define PWR_VOSR_BOOSTEN (1 << 18) +#define PWR_VOSR_VOS_SHIFT (16) +#define PWR_VOSR_VOS_4 (0x0) +#define PWR_VOSR_VOS_3 (0x1) +#define PWR_VOSR_VOS_2 (0x2) +#define PWR_VOSR_VOS_1 (0x3) + +#define PWR_VOSR_VOSRDY (1 << 15) +#define PWR_VOSR_BOOSTRDY (1 << 14) + +#define PWR_SVMCR (*(volatile uint32_t *)(PWR_BASE + 0x10)) +#define PWR_SVMCR_IOS2V (1 << 29) + +#define PWR_UCPDR (*(volatile uint32_t *)(PWR_BASE + 0x2C)) +#define PWR_UCPDR_DBDIS (1 << 0) + +/*** FLASH ***/ +#define SYSCFG_APB2_CLOCK_ER_VAL (1 << 0) /* <> - RCC_APB2ENR - SYSCFGEN */ + +/* Non-Secure only */ +#define FLASH_BASE (0x40022000) /* <> - Table 4 */ +#define FLASH_KEYR (*(volatile uint32_t *)(FLASH_BASE + 0x08)) +#define FLASH_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x10)) +#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x20)) +#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x28)) + +/* Register values (for both secure and non secure registers) */ +#define FLASH_SR_EOP (1 << 0) +#define FLASH_SR_OPERR (1 << 1) +#define FLASH_SR_PROGERR (1 << 3) +#define FLASH_SR_WRPERR (1 << 4) +#define FLASH_SR_PGAERR (1 << 5) +#define FLASH_SR_SIZERR (1 << 6) +#define FLASH_SR_PGSERR (1 << 7) +#define FLASH_SR_OPTWERR (1 << 13) +#define FLASH_SR_BSY (1 << 16) + +#define FLASH_CR_PG (1 << 0) +#define FLASH_CR_PER (1 << 1) +#define FLASH_CR_MER1 (1 << 2) +#define FLASH_CR_PNB_SHIFT 3 +#define FLASH_CR_PNB_MASK 0x7F +#define FLASH_CR_BKER (1 << 11) +#define FLASH_CR_MER2 (1 << 15) +#define FLASH_CR_STRT (1 << 16) +#define FLASH_CR_OPTSTRT (1 << 17) +#define FLASH_CR_EOPIE (1 << 24) +#define FLASH_CR_ERRIE (1 << 25) +#define FLASH_CR_OBL_LAUNCH (1 << 27) +#define FLASH_CR_INV (1 << 29) +#define FLASH_CR_OPTLOCK (1 << 30) +#define FLASH_CR_LOCK (1 << 31) + + +#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00)) +#define FLASH_ACR_LATENCY_MASK (0x0F) +#define FLASH_ACR_PRFTEN (1<<8) + +#define FLASH_OPTR (*(volatile uint32_t *)(FLASH_BASE + 0x40)) +#define FLASH_OPTR_DBANK (1 << 21) +#define FLASH_OPTR_SWAP_BANK (1 << 20) + +#define FLASHMEM_ADDRESS_SPACE (0x08000000) +#define FLASH_PAGE_SIZE (0x2000) /* 8KB */ +#define FLASH_BANK2_BASE (0x08100000) /*!< Base address of Flash Bank2 */ +#define BOOTLOADER_SIZE (0x8000) +#define FLASH_TOP (0x081FFFFF) /*!< FLASH end address */ + +#define FLASH_KEY1 (0x45670123) +#define FLASH_KEY2 (0xCDEF89AB) +#define FLASH_OPTKEY1 (0x08192A3BU) +#define FLASH_OPTKEY2 (0x4C5D6E7FU) + + +static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates) +{ + uint32_t reg = FLASH_ACR; + if ((reg & FLASH_ACR_LATENCY_MASK) != waitstates) + FLASH_ACR = (reg & ~FLASH_ACR_LATENCY_MASK) | waitstates ; +} + +static RAMFUNCTION void flash_wait_complete(uint8_t bank) +{ + while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY) + ; +} + +static void RAMFUNCTION flash_clear_errors(uint8_t bank) +{ + FLASH_SR |= (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR | + FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR); +} + +int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len) +{ + int i = 0; + uint32_t *src, *dst; + uint32_t qword[4]; + volatile uint32_t *sr, *cr; + + cr = &FLASH_CR; + sr = &FLASH_SR; + + flash_clear_errors(0); + src = (uint32_t *)data; + dst = (uint32_t *)address; + + while (i < len) { + qword[0] = src[i >> 2]; + qword[1] = src[(i >> 2) + 1]; + qword[2] = src[(i >> 2) + 2]; + qword[3] = src[(i >> 2) + 3]; + *cr |= FLASH_CR_PG; + dst[i >> 2] = qword[0]; + ISB(); + dst[(i >> 2) + 1] = qword[1]; + ISB(); + dst[(i >> 2) + 2] = qword[2]; + ISB(); + dst[(i >> 2) + 3] = qword[3]; + ISB(); + flash_wait_complete(0); + if ((*sr & FLASH_SR_EOP) != 0) + *sr |= FLASH_SR_EOP; + *cr &= ~FLASH_CR_PG; + i += 16; + } + + return 0; +} + +void RAMFUNCTION hal_flash_unlock(void) +{ + flash_wait_complete(0); + if ((FLASH_CR & FLASH_CR_LOCK) != 0) { + FLASH_KEYR = FLASH_KEY1; + DMB(); + FLASH_KEYR = FLASH_KEY2; + DMB(); + while ((FLASH_CR & FLASH_CR_LOCK) != 0) + ; + } +} + +void RAMFUNCTION hal_flash_lock(void) +{ + flash_wait_complete(0); + if ((FLASH_CR & FLASH_CR_LOCK) == 0) + FLASH_CR |= FLASH_CR_LOCK; +} + +int RAMFUNCTION hal_flash_erase(uint32_t address, int len) +{ + uint32_t end_address; + uint32_t p; + + flash_clear_errors(0); + if (len == 0) + return -1; + + if (address < ARCH_FLASH_OFFSET) + return -1; + + end_address = address + len - 1; + for (p = address; p < end_address; p += FLASH_PAGE_SIZE) { + uint32_t reg; + uint32_t base; + uint32_t bker = 0; + if ((((FLASH_OPTR & FLASH_OPTR_DBANK) == 0) && (p <= FLASH_TOP)) || (p < FLASH_BANK2_BASE)) { + base = FLASHMEM_ADDRESS_SPACE; + } + else if(p >= (FLASH_BANK2_BASE) && (p <= (FLASH_TOP) )) + { + bker = FLASH_CR_BKER; + base = FLASH_BANK2_BASE; + } else { + FLASH_CR &= ~FLASH_CR_PER ; + return 0; /* Address out of range */ + } + reg = FLASH_CR & (~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT) | FLASH_CR_BKER)); + reg |= ((((p - base) >> 13) << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER | bker ); + FLASH_CR = reg; + DMB(); + FLASH_CR |= FLASH_CR_STRT; + flash_wait_complete(0); + } + + /* If the erase operation is completed, disable the associated bits */ + FLASH_CR &= ~FLASH_CR_PER ; + return 0; +} + +static void clock_pll_off(void) +{ + uint32_t reg32, flash_waitstates ; + + /* Select MSI as SYSCLK source. */ + reg32 = RCC_CFGR1; + reg32 &= ~((1 << 1) | (1 << 0)); + RCC_CFGR1 = (reg32 | RCC_CFGR_SW_MSI); + DMB(); + + /* Wait for MSI clock to be selected. */ + while ((RCC_CFGR1 & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_MSI) {}; + + flash_waitstates = 1; + flash_set_waitstates(flash_waitstates); + + /* Turn off PLL */ + RCC_CR &= ~RCC_CR_HSION; + RCC_CR &= ~RCC_CR_PLL1ON; + DMB(); +} + +/* This implementation will setup MSI 48 MHz as PLL Source Mux, PLLCLK as + * System Clock Source */ +static void clock_pll_on(int powersave) +{ + uint32_t reg32; + uint32_t pll1n, pll1m, pll1mboost, pll1q, pll1p, pll1r, pll1fracn, pll1rge; + uint32_t hpre, apb1pre, apb2pre, apb3pre, flash_waitstates; + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC_CR = RCC_CR_MSISON; + + /* Reset CFGR register */ + RCC_CFGR1 = 0U; + RCC_CFGR2 = 0U; + RCC_CFGR3 = 0U; + + /* Reset HSEON, CSSON , HSION, PLLxON bits */ + RCC_CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); + + /* Reset PLLCFGR register */ + RCC_PLL1CFGR = 0U; + + /* Reset HSEBYP bit */ + RCC_CR &= ~(RCC_CR_HSEBYP); + + /* Disable all interrupts */ + RCC_CIER = 0U; + + SCB_VTOR = FLASH_SECURE_MMAP_BASE; /* Vector Table Relocation in Internal FLASH */ + + FLASH_ACR|=FLASH_ACR_PRFTEN; + + RCC_AHB3ENR |= RCC_AHB3ENR_PWREN; + RCC_AHB1ENR |= RCC_AHB1ENR_GTZC1EN; + RCC_AHB3ENR |= RCC_AHB3ENR_GTZC2EN; + + PWR_UCPDR |= PWR_UCPDR_DBDIS; + + PWR_SVMCR |= PWR_SVMCR_IOS2V; + PWR_VOSR &= ~( (PWR_VOSR_VOS_1 << PWR_VOSR_VOS_SHIFT) | PWR_VOSR_BOOSTEN ); + PWR_VOSR|= ((PWR_VOSR_VOS_1<< PWR_VOSR_VOS_SHIFT) | PWR_VOSR_BOOSTEN); + + /* Wait until VOSRDY is rised */ + reg32 = PWR_VOSR; + while ((PWR_VOSR & PWR_VOSR_VOSRDY) == 0) {}; + + RCC_ICSCR1|= RCC_ICSCR1_MSIRGSEL; + reg32 = RCC_ICSCR1; + reg32 &= ~( (0xF << RCC_ICSCR1_MSIRANGE_SHIFT)); + reg32|= (RCC_ICSCR1_MSIRG_0 << RCC_ICSCR1_MSIRANGE_SHIFT); + RCC_ICSCR1 = reg32; + reg32 = RCC_ICSCR1; + DMB(); + + /* Adjusts the Multiple Speed oscillator (MSI) calibration value */ + reg32 = RCC_ICSCR2; + reg32 &= ~((0x1F << RCC_ICSCR2_MSITRIM0_SHIFT)); + reg32 |= (RCC_ICSCR2_MSITRIM0_DEFAULT << RCC_ICSCR2_MSITRIM0_SHIFT); + RCC_ICSCR2 = reg32; + reg32 = RCC_ICSCR2; + DMB(); + + flash_waitstates = 1; + flash_set_waitstates(flash_waitstates); + + /*----------------------------- HSI Configuration --------------------------*/ + /* Enable the Internal High Speed oscillator (HSI) */ + RCC_CR |= RCC_CR_HSION; + /* Wait till HSI is ready */ + while ((RCC_CR & RCC_CR_HSIRDY) == 0) {}; + /* Adjusts the Internal High Speed oscillator (HSI) calibration value */ + reg32 = RCC_ICSCR3; + reg32 &= ~((1 << 20) | (1 << 19) | (1 << 18) | (1 << 17) | (1 << 16) ); + reg32 |= (RCC_ICSCR3_HSITRIM_DEFAULT << RCC_ICSCR3_HSITRIM_SHIFT); + RCC_ICSCR3 = reg32; + reg32 = RCC_ICSCR3; + DMB(); + + /*-------------------------------- PLL Configuration -----------------------*/ + + /* Select clock parameters (CPU Speed = 160 MHz) */ + pll1m = 3; + pll1mboost = RCC_PLL1CFGR_PLL1MBOOST_DIV4; + pll1n = 10; + pll1p = 2; + pll1q = 2; + pll1r = 1; + pll1fracn = 0; + pll1rge = RCC_PLL1VCIRANGE_1; + hpre = RCC_AHB_PRESCALER_DIV_NONE; + apb1pre = RCC_APB_PRESCALER_DIV_NONE; + apb2pre = RCC_APB_PRESCALER_DIV_NONE; + apb3pre = RCC_APB_PRESCALER_DIV_NONE; + + /* Disable the main PLL */ + RCC_CR &= ~RCC_CR_PLL1ON; + + /* Wait till PLL is ready */ + while ((RCC_CR & RCC_CR_PLL1RDY) != 0) {}; + + /* Enable PWR CLK */ + RCC_AHB3ENR|= RCC_AHB3ENR_PWREN; + + /*Disable EPOD to configure PLL1MBOOST*/ + PWR_VOSR &= ~PWR_VOSR_BOOSTEN; + + /* Configure the main PLL clock source, multiplication and division factors */ + reg32 = RCC_PLL1CFGR ; + reg32 &= ~((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12) | (1 << 11) | + (1 << 10) | (1 << 9) | (1 << 8) | (1 << 1) | (1 << 0)); + reg32 |= RCC_PLLCKSELR_PLLSRC_MSI; + reg32 |= ((pll1m-1) << RCC_PLL1CFGR_PLLM_SHIFT); + reg32 |= ((pll1mboost) << RCC_PLL1CFGR_PLL1MBOOST_SHIFT); + RCC_PLL1CFGR = reg32; + + reg32 =0; + reg32 |= ((pll1n-1) << RCC_PLL1DIVR_PLLN_SHIFT); + reg32 |= ((pll1p-1) << RCC_PLL1DIVR_PLLP_SHIFT); + reg32 |= ((pll1q-1) << RCC_PLL1DIVR_PLLQ_SHIFT); + reg32 |= ((pll1r-1) << RCC_PLL1DIVR_PLLR_SHIFT); + RCC_PLL1DIVR = reg32; + DMB(); + + /* Disable PLL1FRACN */ + RCC_PLL1CFGR&= ~RCC_PLL1CFGR_PLL1FRACEN; + + /* Configure PLL PLL1FRACN */ + reg32 = RCC_PLL1FRACR ; + reg32 &= ~((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12) | (1 << 11) | + (1 << 10) | (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) | + (1 << 5) | (1 << 4) | (1 << 3)); + reg32 |= ((pll1fracn) << RCC_PLL1FRACR_SHIFT); + RCC_PLL1FRACR = reg32; + + /* Enable PLL1FRACN */ + RCC_PLL1CFGR|= RCC_PLL1CFGR_PLL1FRACEN; + + /* Select PLL1 input reference frequency range: VCI */ + reg32 = RCC_PLL1CFGR ; + reg32 &= ~((1 << 3) | (1 << 2)); + reg32 |= ((pll1rge) << RCC_PLL1CFGR_PLL1RGE_SHIFT); + RCC_PLL1CFGR = reg32; + + /* Enable the EPOD to reach max frequency */ + PWR_VOSR |= PWR_VOSR_BOOSTEN; + + /* Disable PWR clk */ + RCC_AHB3ENR&=~RCC_AHB3ENR_PWREN; + + /* Enable PLL System Clock output */ + RCC_PLL1CFGR|=RCC_PLL1CFGR_PLL1REN; + + /* Enable the main PLL */ + RCC_CR|=RCC_CR_PLL1ON; + + /* Wait till PLL is ready */ + while ((RCC_CR & RCC_CR_PLL1RDY) == 0) {}; + + /* Increasing the number of wait states because of higher CPU frequency */ + flash_waitstates = 4; + flash_set_waitstates(flash_waitstates); + + /* Enable PWR CLK */ + RCC_AHB3ENR|= RCC_AHB3ENR_PWREN; + + /* Wait till BOOST is ready */ + while ((PWR_VOSR & PWR_VOSR_BOOSTRDY) == 0) {}; + + /*Disable PWR clk */ + RCC_AHB3ENR&=~RCC_AHB3ENR_PWREN; + + /* Select PLL as SYSCLK source. */ + reg32 = RCC_CFGR1; + reg32 &= ~((1 << 1) | (1 << 0)); + RCC_CFGR1 = (reg32 | RCC_CFGR_SW_PLL); + DMB(); + + /* Wait for PLL clock to be selected. */ + while ((RCC_CFGR1 & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_PLL) {}; + + /* HCLK Configuration */ + reg32 = RCC_CFGR2 ; + reg32 &= ~((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); + reg32 |= hpre; + RCC_CFGR2 = reg32; + DMB(); + + /* PRE1 and PRE2 conf */ + reg32 = RCC_CFGR2 ; + reg32 &= ~((1 << 6) | (1 << 5) | (1 << 4)); + reg32 |= ((apb1pre) << RCC_CFGR2_PPRE1_SHIFT) ; + reg32 &= ~((1 << 10) | (1 << 9) | (1 << 8)); + reg32 |= ((apb2pre) << RCC_CFGR2_PPRE2_SHIFT) ; + RCC_CFGR2 = reg32; + DMB(); + + /* PRE3 conf */ + reg32 = RCC_CFGR3 ; + reg32 &= ~((1 << 6) | (1 << 5) | (1 << 4)); + reg32 |= ((apb3pre) << RCC_CFGR3_PPRE3_SHIFT) ; + RCC_CFGR3 = reg32; + DMB(); + + /* Disable PWR clk */ + RCC_AHB3ENR&=~RCC_AHB3ENR_PWREN; + +} + +void hal_init(void) +{ + clock_pll_on(0); +} diff --git a/hal/stm32u5_partition.h b/hal/stm32u5_partition.h new file mode 100644 index 00000000..a8fb6b14 --- /dev/null +++ b/hal/stm32u5_partition.h @@ -0,0 +1,482 @@ +/* stm32u5_partition.h + * + * Copyright (C) 2021 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef STM32U5_PARTITION_H +#define STM32U5_PARTITION_H + +#define SCS_BASE (0xE000E000UL) +#define SCS_NS_BASE (0xE002E000UL) +#define SCB_BASE (SCS_BASE + 0x0D00UL) +#define SCB_NS_BASE (SCS_BASE + 0x0D00UL) +#define SAU_BASE (SCS_BASE + 0x0DD0UL) +#define FPU_BASE (SCS_BASE + 0x0F30UL) +#define NVIC_BASE (SCS_BASE + 0x0100UL) + +#define SAU_CTRL (*(volatile uint32_t *)(SAU_BASE + 0x00)) +#define SAU_RNR (*(volatile uint32_t *)(SAU_BASE + 0x08)) +#define SAU_RBAR (*(volatile uint32_t *)(SAU_BASE + 0x0C)) +#define SAU_RLAR (*(volatile uint32_t *)(SAU_BASE + 0x10)) + +#define SCB_CPACR (*(volatile uint32_t *)(SCB_BASE + 0x88)) +#define SCB_NSACR (*(volatile uint32_t *)(SCB_BASE + 0x8C)) +#define SCB_VTOR (*(volatile uint32_t *)(SCB_BASE + 0x08)) +#define FPU_FPCCR (*(volatile uint32_t *)(FPU_BASE + 0x04)) + +#define SCB_NS_CPACR (*(volatile uint32_t *)(SCB_NS_BASE + 0x88)) + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ + +#define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */ +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */ +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20040000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x200BFFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 + +// Setup behaviour of Floating Point Unit + +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + + +#define SAU_INIT_REGION(n) \ + SAU_RNR = (n & SAU_RNR_REGION_Msk); \ + SAU_RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU_RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +#define GTZC1_MPCBB3_S_BASE (0x50033400) +#define GTZC1_MPCBB3_S_CR (*(volatile uint32_t *)(GTZC1_MPCBB3_S_BASE + 0x00)) +#define GTZC1_MPCBB3_S_CFGLOCKR1 (*(volatile uint32_t *)(GTZC1_MPCBB3_S_BASE + 0x10)) +#define GTZC1_MPCBB3_S_SECCFGR0 (GTZC1_MPCBB3_S_BASE + 0x100) +#define GTZC1_MPCBB3_S_PRIVCFGR0 (GTZC1_MPCBB3_S_BASE + 0x200) + +#define SET_GTZC1_MPCBBx_SECCFGR(x,n) \ + (*((volatile uint32_t *)(GTZC1_MPCBB##x##_S_SECCFGR0 ) + n ))= GTZC1_MPCBB##x##_S_SECCFGR##n##_VAL + +#define SET_GTZC1_MPCBBx_PRIVCFGR(x,n) \ + (*((volatile uint32_t *)(GTZC1_MPCBB##x##_S_PRIVCFGR0 ) + n ))= GTZC1_MPCBB##x##_S_PRIVCFGR##n##_VAL + +/*SRAM3 - SECCFG*/ +#define GTZC1_MPCBB3_S_SECCFGR0_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR1_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR2_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR3_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR4_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR5_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR6_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR7_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR8_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR9_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR10_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR11_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR12_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR13_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR14_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR15_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR16_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR17_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR18_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR19_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR20_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR21_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR22_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR23_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR24_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR25_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR26_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR27_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR28_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR29_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR30_VAL (0x00000000) +#define GTZC1_MPCBB3_S_SECCFGR31_VAL (0x00000000) + +/*SRAM3 - PRIVCFG*/ +#define GTZC1_MPCBB3_S_PRIVCFGR0_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR1_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR2_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR3_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR4_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR5_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR6_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR7_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR8_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR9_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR10_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR11_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR12_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR13_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR14_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR15_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR16_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR17_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR18_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR19_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR20_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR21_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR22_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR23_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR24_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR25_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR26_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR27_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR28_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR29_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR30_VAL (0x00000000) +#define GTZC1_MPCBB3_S_PRIVCFGR31_VAL (0x00000000) + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +static __inline void TZ_SAU_Setup (void) +{ + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + SAU_CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + + #if defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB_NSACR = (SCB_NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + SCB_CPACR |= ((0x3 << 20)|(0x3 << 22)); /* set CP10 and CP11 Full Access */ + + FPU_FPCCR = (FPU_FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + + #endif + +} + +#endif /* STM32U5_PARTITION_H */ diff --git a/src/boot_arm.c b/src/boot_arm.c index 98bbf1cd..a9d8c4bd 100644 --- a/src/boot_arm.c +++ b/src/boot_arm.c @@ -429,7 +429,7 @@ void (* const IV[])(void) = 0, // reserved isr_empty, // PendSV isr_empty, // SysTick -#ifdef PLATFORM_stm32l5 /* Fill with extra unused handlers */ +#if defined(PLATFORM_stm32l5) ||defined(PLATFORM_stm32u5) /* Fill with extra unused handlers */ isr_empty, isr_empty, isr_empty, diff --git a/test-app/ARM-stm32u5-ns.ld b/test-app/ARM-stm32u5-ns.ld new file mode 100644 index 00000000..73194afa --- /dev/null +++ b/test-app/ARM-stm32u5-ns.ld @@ -0,0 +1,47 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = ##WOLFBOOT_TEST_APP_ADDRESS##, LENGTH = ##WOLFBOOT_TEST_APP_SIZE## + RAM (rwx) : ORIGIN = 0x20040000, LENGTH = 64K /* Run in lowmem */ +} + +SECTIONS +{ + .text : + { + _start_text = .; + . = ALIGN(8); + KEEP(*(.isr_vector)) + . = ALIGN(8); + *(.init) + *(.fini) + *(.text*) + *(.rodata*) + . = ALIGN(8); + _end_text = .; + } > FLASH + + _stored_data = .; + + .data : AT (_stored_data) + { + _start_data = .; + KEEP(*(.data*)) + . = ALIGN(8); + KEEP(*(.ramcode)) + . = ALIGN(8); + _end_data = .; + } > RAM + + .bss : + { + _start_bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + _end_bss = .; + _end = .; + } > RAM +} + +PROVIDE(_start_heap = _end); +PROVIDE(_end_stack = ORIGIN(RAM) + LENGTH(RAM)); diff --git a/test-app/ARM-stm32u5.ld b/test-app/ARM-stm32u5.ld new file mode 100644 index 00000000..23c89c3c --- /dev/null +++ b/test-app/ARM-stm32u5.ld @@ -0,0 +1,47 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = ##WOLFBOOT_TEST_APP_ADDRESS##, LENGTH = ##WOLFBOOT_TEST_APP_SIZE## + RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 64K /* Run in lowmem */ +} + +SECTIONS +{ + .text : + { + _start_text = .; + . = ALIGN(8); + KEEP(*(.isr_vector)) + . = ALIGN(8); + *(.init) + *(.fini) + *(.text*) + *(.rodata*) + . = ALIGN(8); + _end_text = .; + } > FLASH + + _stored_data = .; + + .data : AT (_stored_data) + { + _start_data = .; + KEEP(*(.data*)) + . = ALIGN(8); + KEEP(*(.ramcode)) + . = ALIGN(8); + _end_data = .; + } > RAM + + .bss : + { + _start_bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + _end_bss = .; + _end = .; + } > RAM +} + +PROVIDE(_start_heap = _end); +PROVIDE(_end_stack = ORIGIN(RAM) + LENGTH(RAM)); diff --git a/test-app/Makefile b/test-app/Makefile index a02e1bbf..ddc27f70 100644 --- a/test-app/Makefile +++ b/test-app/Makefile @@ -99,6 +99,15 @@ ifeq ($(TARGET),stm32l5) LDFLAGS+=-mcpu=cortex-m33 endif +ifeq ($(TARGET),stm32u5) + ifeq ($(TZEN),1) + LSCRIPT_TEMPLATE=ARM-stm32u5-ns.ld + else + LSCRIPT_TEMPLATE=ARM-stm32u5.ld + endif + CFLAGS+=-mcpu=cortex-m33 + LDFLAGS+=-mcpu=cortex-m33 +endif ifeq ($(TARGET),ti_hercules) diff --git a/test-app/app_stm32u5.c b/test-app/app_stm32u5.c new file mode 100644 index 00000000..16d5ce1f --- /dev/null +++ b/test-app/app_stm32u5.c @@ -0,0 +1,106 @@ +/* app_stm32u5.c + * + * Test bare-metal application. + * + * Copyright (C) 2021 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#include +#include +#include +#include +#include "system.h" +#include "hal.h" +#include "wolfboot/wolfboot.h" + +#define LED_BOOT_PIN (7) /* PH7 - Discovery - Green Led */ +#define LED_USR_PIN (6) /* PH6 - Discovery - Red Led */ + +/*Non-Secure */ +#define RCC_BASE (0x46020C00) /* RM0456 - Table 4 */ +#define PWR_BASE (0x46020800) /* RM0456 - Table 4 */ +#define GPIOH_BASE 0x42021C00 + + +#define GPIOH_MODER (*(volatile uint32_t *)(GPIOH_BASE + 0x00)) +#define GPIOH_PUPDR (*(volatile uint32_t *)(GPIOH_BASE + 0x0C)) +#define GPIOH_BSRR (*(volatile uint32_t *)(GPIOH_BASE + 0x18)) + +#define RCC_AHB2ENR1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C )) +#define GPIOH_AHB2ENR1_CLOCK_ER (1 << 7) + +#define PWR_CR2 (*(volatile uint32_t *)(PWR_BASE + 0x04)) +#define PWR_CR2_IOSV (1 << 9) + +static void boot_led_on(void) +{ + uint32_t reg; + uint32_t pin = LED_BOOT_PIN; + + RCC_AHB2ENR1_CLOCK_ER|= GPIOH_AHB2ENR1_CLOCK_ER; + /* Delay after an RCC peripheral clock enabling */ + reg = RCC_AHB2ENR1_CLOCK_ER; + +#if 0 + /* Disabled, may not need it */ + PWR_CR2 |= PWR_CR2_IOSV; +#endif + + reg = GPIOH_MODER & ~(0x03 << (pin * 2)); + GPIOH_MODER = reg | (1 << (pin * 2)); + GPIOH_PUPDR &= ~(0x03 << (pin * 2)); + GPIOH_BSRR |= (1 << (pin + 16)); +} + +static void boot_led_off(void) +{ + GPIOH_BSRR |= (1 << (LED_BOOT_PIN)); +} + +void usr_led_on(void) +{ + uint32_t reg; + uint32_t pin = LED_USR_PIN; + + RCC_AHB2ENR1_CLOCK_ER|= GPIOH_AHB2ENR1_CLOCK_ER; + /* Delay after an RCC peripheral clock enabling */ + reg = RCC_AHB2ENR1_CLOCK_ER; + + reg = GPIOH_MODER & ~(0x03 << (pin * 2)); + GPIOH_MODER = reg | (1 << (pin * 2)); + GPIOH_PUPDR &= ~(0x03 << (pin * 2)); + GPIOH_BSRR |= (1 << (pin + 16)); +} + +void usr_led_off(void) +{ + GPIOH_BSRR |= (1 << (LED_USR_PIN)); +} + +void main(void) +{ + hal_init(); + boot_led_on(); + usr_led_on(); + boot_led_off(); + if (wolfBoot_current_firmware_version() > 1) + boot_led_on(); + while(1) + ; +} diff --git a/test-app/startup_arm.c b/test-app/startup_arm.c index 10dc7e29..077c1630 100644 --- a/test-app/startup_arm.c +++ b/test-app/startup_arm.c @@ -176,7 +176,7 @@ void (* const IV[])(void) = isr_empty, // CAN2 isr_empty, // Ethernet isr_empty, // Hibernate -#elif PLATFORM_stm32l5 +#elif (defined(PLATFORM_stm32l5) ||defined(PLATFORM_stm32u5)) /* Fill with extra unused handlers */ isr_empty, // WWDG_IRQHandler isr_empty, // PVD_PVM_IRQHandler isr_empty, // RTC_IRQHandler diff --git a/tools/scripts/prepare_update_u5.sh b/tools/scripts/prepare_update_u5.sh new file mode 100644 index 00000000..afdc4984 --- /dev/null +++ b/tools/scripts/prepare_update_u5.sh @@ -0,0 +1,15 @@ +#!/bin/bash + +SIGN_TOOL="python3 ./tools/keytools/sign.py" +if [ -f "./tools/keytools/sign" ]; then + SIGN_TOOL="./tools/keytools/sign" +fi + +# SIZE is WOLFBOOT_PARTITION_SIZE - 5 +SIZE=131067 +VERSION=8 +APP=test-app/image_v"$VERSION"_signed.bin +$SIGN_TOOL --sha256 --ecc256 test-app/image.bin ecc256.der $VERSION +dd if=/dev/zero bs=$SIZE count=1 2>/dev/null | tr "\000" "\377" > update.bin +dd if=$APP of=update.bin bs=1 conv=notrunc +printf "pBOOT" >> update.bin \ No newline at end of file diff --git a/tools/scripts/prepare_update_u5_dualbank.sh b/tools/scripts/prepare_update_u5_dualbank.sh new file mode 100644 index 00000000..a0601675 --- /dev/null +++ b/tools/scripts/prepare_update_u5_dualbank.sh @@ -0,0 +1,15 @@ +#!/bin/bash + +SIGN_TOOL="python3 ./tools/keytools/sign.py" +if [ -f "./tools/keytools/sign" ]; then + SIGN_TOOL="./tools/keytools/sign" +fi + +# SIZE is WOLFBOOT_PARTITION_SIZE - 5 +SIZE=229371 +VERSION=8 +APP=test-app/image_v"$VERSION"_signed.bin +$SIGN_TOOL --ecc256 test-app/image.bin ecc256.der $VERSION +dd if=/dev/zero bs=$SIZE count=1 2>/dev/null | tr "\000" "\377" > update.bin +dd if=$APP of=update.bin bs=1 conv=notrunc +printf "pBOOT" >> update.bin