diff --git a/arch.mk b/arch.mk
index 353aa981..fd7825cd 100644
--- a/arch.mk
+++ b/arch.mk
@@ -76,7 +76,8 @@ ifeq ($(ARCH),ARM)
 
   ifeq ($(TARGET),stm32l5)
     CORTEX_M33=1
-    CFLAGS+=-Ihal
+    CFLAGS+=-Ihal -DCORTEX_M33
+    ARCH_FLASH_OFFSET=0x08000000
   endif
 
   ## Cortex-M CPU
diff --git a/config/examples/stm32l5.config b/config/examples/stm32l5.config
index f3152c67..d3ce893c 100644
--- a/config/examples/stm32l5.config
+++ b/config/examples/stm32l5.config
@@ -1,8 +1,9 @@
 ARCH?=ARM
+TZEN?=1
 TARGET?=stm32l5
 SIGN?=ECC256
 HASH?=SHA256
-DEBUG?=0
+DEBUG?=1
 VTOR?=1
 CORTEX_M0?=0
 CORTEX_M33?=1
@@ -10,7 +11,7 @@ NO_ASM?=0
 EXT_FLASH?=0
 SPI_FLASH?=0
 ALLOW_DOWNGRADE?=0
-NVM_FLASH_WRITEONCE?=0
+NVM_FLASH_WRITEONCE?=1
 WOLFBOOT_VERSION?=1
 V?=0
 SPMATH?=1
diff --git a/docs/Targets.md b/docs/Targets.md
index 5664672b..4e742912 100644
--- a/docs/Targets.md
+++ b/docs/Targets.md
@@ -84,8 +84,7 @@ SECWM1_PSTRT=0x0  SECWM1_PEND=0x7F  All 128 pages of internal Flash Bank1 set as
 SECWM2_PSTRT=0x1  SECWM2_PEND=0x0   No page of internal Flash Bank2 set as secure, hence Bank2 non-secure
 ```
 
-- NOTE: STM32CubeProgrammer V2.3.0 is recommended  (v2.4.0 has a known bug for STM32L5)
-- typical path: C:\Program Files\STMicroelectronics\STM32Cube\STM32CubeProgrammer\bin
+- NOTE: STM32CubeProgrammer V2.3.0 is required  (v2.4.0 has a known bug for STM32L5)
 
 ### How to use it
 
@@ -100,6 +99,16 @@ SECWM2_PSTRT=0x1  SECWM2_PEND=0x0   No page of internal Flash Bank2 set as secur
     - `STM32_Programmer_CLI -c port=swd -d .\test-app\image_v1_signed.bin 0x8040000`
 6. RED LD9 will be on
 
+### Debugging
+
+- STM32CubeIDE v.1.3.0 required
+- Run the debugger via:
+
+`ST-LINK_gdbserver -d -cp /opt/st/stm32cubeide_1.3.0/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.linux64_1.3.0.202002181050/tools/bin -e -r 1 -p 3333`
+
+- Connect with arm-none-eabi-gdb
+
+
 
 ## STM32L0x3
 
diff --git a/hal/stm32l5.c b/hal/stm32l5.c
index 72498794..0f648c5b 100644
--- a/hal/stm32l5.c
+++ b/hal/stm32l5.c
@@ -280,7 +280,7 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
   flash_clear_errors(0);
 
   src = (uint32_t *)data;
-  dst = (uint32_t *)(address + FLASHMEM_ADDRESS_SPACE);
+  dst = (uint32_t *)address;
 
   while (i < len) {
     FLASH_CR |= FLASH_CR_PG;
@@ -326,18 +326,22 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
         return -1;
     end_address = address + len - 1;
     for (p = address; p < end_address; p += FLASH_PAGE_SIZE) {
-       // considering DBANK = 1
-        if (p < (FLASH_BANK2_BASE -FLASHMEM_ADDRESS_SPACE) )
+        uint32_t reg;
+        uint32_t base;
+        // considering DBANK = 1
+        if (p < (FLASH_BANK2_BASE) )
         {
           FLASH_CR &= ~FLASH_CR_BKER;
+          base = FLASHMEM_ADDRESS_SPACE;
         }
-        if(p>=(FLASH_BANK2_BASE -FLASHMEM_ADDRESS_SPACE) && (p <= (FLASH_TOP -FLASHMEM_ADDRESS_SPACE) ))
+        if(p>=(FLASH_BANK2_BASE) && (p <= (FLASH_TOP) ))
         {
           FLASH_CR |= FLASH_CR_BKER;
+          base = FLASH_BANK2_BASE;
         }
 
-        uint32_t reg = FLASH_CR & (~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT)| FLASH_CR_PER));
-        FLASH_CR = reg | (((p >> 11) << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER );
+        reg = FLASH_CR & (~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT)| FLASH_CR_PER));
+        FLASH_CR = reg | ((((p - base)  >> 11) << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER );
         DMB();
         FLASH_CR |= FLASH_CR_STRT;
         flash_wait_complete(0);
diff --git a/src/boot_arm.c b/src/boot_arm.c
index 93215635..d132fa2d 100644
--- a/src/boot_arm.c
+++ b/src/boot_arm.c
@@ -225,26 +225,37 @@ void isr_empty(void)
 #else
 #define VTOR (*(volatile uint32_t *)(0xE000ED08))
 #endif
+
+
 static void  *app_entry;
 static uint32_t app_end_stack;
 
 
 
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#if defined CORTEX_M33
 
 /* Armv8 boot procedure */
 void RAMFUNCTION do_boot(const uint32_t *app_offset)
 {
+    /* Get stack pointer, entry point */
+    app_end_stack = (*((uint32_t *)(app_offset)));
+    app_entry = (void *)(*((uint32_t *)(app_offset + 1)));
     /* Disable interrupts */
     asm volatile("cpsid i");
     /* Update IV */
     VTOR = ((uint32_t)app_offset);
     asm volatile("msr msplim, %0" ::"r"(0));
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
     asm volatile("msr msp_ns, %0" ::"r"(app_end_stack));
+    /* Jump to non secure app_entry */
     asm volatile("mov r7, %0" ::"r"(app_entry));
     asm volatile("bic.w   r7, r7, #1");
-    /* Jump to non secure app_entry */
     asm volatile("blxns   r7" );
+#else
+    asm volatile("msr msp, %0" ::"r"(app_end_stack));
+    asm volatile("mov pc, %0":: "r"(app_entry));
+#endif
+
 }
 #else
 /* Armv6/v7 */
diff --git a/test-app/ARM-stm32l5-ns.ld b/test-app/ARM-stm32l5-ns.ld
new file mode 100644
index 00000000..b509fc7f
--- /dev/null
+++ b/test-app/ARM-stm32l5-ns.ld
@@ -0,0 +1,47 @@
+MEMORY
+{
+    FLASH (rx) : ORIGIN = ##WOLFBOOT_TEST_APP_ADDRESS##, LENGTH = ##WOLFBOOT_TEST_APP_SIZE##
+    RAM (rwx) : ORIGIN = 0x20018000, LENGTH = 16K /* Run in lowmem */
+}
+
+SECTIONS
+{
+    .text :
+    {
+        _start_text = .;
+        . = ALIGN(8);
+        KEEP(*(.isr_vector))
+        . = ALIGN(8);
+        *(.init)
+        *(.fini)
+        *(.text*)
+        *(.rodata*)
+        . = ALIGN(8);
+        _end_text = .;
+    } > FLASH
+
+    _stored_data = .;
+
+    .data : AT (_stored_data)
+    {
+        _start_data = .;
+        KEEP(*(.data*))
+        . = ALIGN(8);
+        KEEP(*(.ramcode))
+        . = ALIGN(8);
+        _end_data = .;
+    } > RAM
+
+    .bss :
+    {
+        _start_bss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end_bss = .;
+        _end = .;
+    } > RAM
+}
+
+PROVIDE(_start_heap = _end);
+PROVIDE(_end_stack  = ORIGIN(RAM) + LENGTH(RAM));
diff --git a/test-app/ARM-stm32l5.ld b/test-app/ARM-stm32l5.ld
index b509fc7f..496417c1 100644
--- a/test-app/ARM-stm32l5.ld
+++ b/test-app/ARM-stm32l5.ld
@@ -1,7 +1,7 @@
 MEMORY
 {
     FLASH (rx) : ORIGIN = ##WOLFBOOT_TEST_APP_ADDRESS##, LENGTH = ##WOLFBOOT_TEST_APP_SIZE##
-    RAM (rwx) : ORIGIN = 0x20018000, LENGTH = 16K /* Run in lowmem */
+    RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 16K /* Run in lowmem */
 }
 
 SECTIONS
diff --git a/test-app/Makefile b/test-app/Makefile
index fd9201ee..1452149a 100644
--- a/test-app/Makefile
+++ b/test-app/Makefile
@@ -60,11 +60,17 @@ ifeq ($(TARGET),stm32f7)
   LSCRIPT_TEMPLATE=ARM-stm32f7.ld
   CFLAGS+=-DDUALBANK_SWAP
 endif
+
 ifeq ($(TARGET),stm32l5)
-  LSCRIPT_TEMPLATE=ARM-stm32l5.ld
+  ifeq ($(TZEN),1)
+    LSCRIPT_TEMPLATE=ARM-stm32l5-ns.ld
+  else
+    LSCRIPT_TEMPLATE=ARM-stm32l5.ld
+  endif
   CFLAGS+=-mcpu=cortex-m33  
+  LDFLAGS+=-mcpu=cortex-m33
 endif
-LDFLAGS:=$(CFLAGS) -T $(LSCRIPT) -Wl,-gc-sections -Wl,-Map=image.map
+LDFLAGS+=$(CFLAGS) -T $(LSCRIPT) -Wl,-gc-sections -Wl,-Map=image.map
 
 ifeq ($(EXT_FLASH),1)
   CFLAGS+=-DEXT_FLASH=1 -DPART_UPDATE_EXT=1
diff --git a/tools/scripts/prepare_update_l5.sh b/tools/scripts/prepare_update_l5.sh
new file mode 100755
index 00000000..52a893bb
--- /dev/null
+++ b/tools/scripts/prepare_update_l5.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+# SIZE is WOLFBOOT_PARTITION_SIZE - 5
+SIZE=129019
+VERSION=8
+APP=test-app/image_v"$VERSION"_signed.bin
+./tools/keytools/sign.py test-app/image.bin ecc256.der $VERSION
+dd if=/dev/zero bs=$SIZE count=1 2>/dev/null | tr "\000" "\377" > update.bin
+dd if=$APP of=update.bin bs=1 conv=notrunc
+printf "pBOOT"  >> update.bin
+