mirror of https://github.com/wolfSSL/wolfBoot.git
Various items for STM32WB55
parent
485253f305
commit
5779baa8a9
5
arch.mk
5
arch.mk
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@ -43,6 +43,11 @@ ifeq ($(ARCH),ARM)
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SPI_TARGET=stm32
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endif
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ifeq ($(TARGET),stm32wb)
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ARCH_FLASH_OFFSET=0x08000000
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SPI_TARGET=stm32
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endif
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## Cortex-M CPU
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ifeq ($(CORTEX_M0),1)
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CFLAGS+=-mcpu=cortex-m0
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@ -0,0 +1,10 @@
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TARGET=stm32wb
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SIGN=ECC256
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WOLFBOOT_SECTOR_SIZE?=0x1000
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WOLFBOOT_PARTITION_SIZE?=0x20000
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x8000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x28000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x48000
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NVM_FLASH_WRITEONCE=1
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PKA=0
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WOLFTPM=1
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@ -0,0 +1,8 @@
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source [find interface/stlink.cfg]
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source [find target/stm32wbx.cfg]
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$_TARGETNAME configure -event reset-init {
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mmw 0xe0042004 0x7 0x0
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}
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init
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reset
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halt
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@ -88,6 +88,7 @@ Compile with:
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`make TARGET=stm32g0 NVM_FLASH_WRITEONCE=1`
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## STM32WB55
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Example partitioning on Nucleo-68 board:
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@ -115,6 +116,30 @@ Compile with:
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`make TARGET=stm32wb NVM_FLASH_WRITEONCE=1`
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### Loading the firmware
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`openocd --file ./config/openocd/openocd_stm32wbx.cfg`
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```
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telnet localhost 4444
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flash write_image unlock erase wolfboot.bin 0x08000000
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flash verify_bank 0 wolfboot.bin
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flash write_image unlock erase test-app/image_v1_signed.bin 0x080008000
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flash verify_bank 0 test-app/image_v1_signed.bin 0x080008000
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reset
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```
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### Debugging
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Use `make DEBUG=1` and reload firmware.
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```
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arm-none-eabi-gdb wolfboot.elf -ex "set remotetimeout 240" -ex "target extended-remote localhost:3333"
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(gdb) add-symbol-file test-app/image.elf 0x8000
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(gdb) add-symbol-file wolfboot.elf 0x0
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```
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## SiFive HiFive1 RISC-V
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### Features
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@ -367,9 +392,8 @@ telnet localhost 4444
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flash write_image unlock erase wolfboot.bin 0x08000000
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flash verify_bank 0 wolfboot.bin
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flash write_image unlock erase test-app/image_v1_signed.bin 0x08020000
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flash verify_bank 0 test-app/image_v1_signed.bin 0x20000
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flash verify_bank 0 test-app/image_v1_signed.bin 0x08020000
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reset
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resume 0x08000000
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```
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To sign the same application image as new version (2), use the python script `sign.py` provided:
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@ -44,9 +44,10 @@
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#define GPIOC_BASE (0x48000800)
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#define GPIOD_BASE (0x48000C00)
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/* STM32WB55 NUCLEO: CN9: D13=SCK, D12=MISO, D11=MOSI, FLASHCS=D10, TPMCS=D9 */
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#define SPI_CS_GPIO GPIOA_BASE
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#define SPI_CS_FLASH 4 /* Flash CS connected to GPIOA4 */
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#define SPI_CS_TPM 0 /* TPM CS connected to GPIOA0 */
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#define SPI_CS_TPM 9 /* TPM CS connected to GPIOA9 */
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#define SPI1_PIN_AF 5 /* Alternate function for SPI pins */
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#define SPI1_CLOCK_PIN 5 /* SPI_SCK: PA5 */
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#define SPI1_MISO_PIN 6 /* SPI_MISO PA6 */
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@ -1 +1 @@
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Subproject commit 9fd56281482bac15de56269e68162b26f2fab6e7
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Subproject commit 2aa8fa2de688b93c5efd21145c6b899b53eb2da9
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