mirror of https://github.com/wolfSSL/wolfBoot.git
Removed custom assembly code for psoc6: using boot_arm startup (in C)
Daniele Lacamera
David Garske
parent
c3e19daa5d
commit
5d932fe857
1
arch.mk
1
arch.mk
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@ -153,7 +153,6 @@ endif
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ifeq ($(TARGET),psoc6)
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CORTEX_M0=1
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OBJS+=hal/psoc6_02_cm0plus.o
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PKA_EXTRA_OBJS+= $(CYPRESS_PDL)/drivers/source/cy_flash.o \
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$(CYPRESS_PDL)/drivers/source/cy_ipc_pipe.o \
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$(CYPRESS_PDL)/drivers/source/cy_ipc_sema.o \
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@ -1,378 +0,0 @@
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/**************************************************************************//**
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* @file startup_psoc6_02_cm0plus.S
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* @brief CMSIS Core Device Startup File for
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* ARMCM0plus Device Series
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* @version V5.00
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* @date 02. March 2016
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******************************************************************************/
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/*
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* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* Address of the NMI handler */
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#define CY_NMI_HANLDER_ADDR 0x0000000D
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/* The CPU VTOR register */
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#define CY_CPU_VTOR_ADDR 0xE000ED08
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/* DONT / Copy flash vectors and data section to RAM */
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// DONT / #define __STARTUP_COPY_MULTIPLE
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// #define RAM_VECTORS
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#define __NO_SYSTEM_INIT
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/* Clear single BSS section */
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#define __STARTUP_CLEAR_BSS
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.syntax unified
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.arch armv6-m
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.section .stack
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.align 3
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#ifdef __STACK_SIZE
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.equ Stack_Size, __STACK_SIZE
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#else
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.equ Stack_Size, 0x00001000
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#endif
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.globl __StackTop
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.globl __StackLimit
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__StackLimit:
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.space Stack_Size
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.size __StackLimit, . - __StackLimit
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.align 3
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#ifdef __HEAP_SIZE
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.equ Heap_Size, __HEAP_SIZE
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#else
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.equ Heap_Size, 0x00000400
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#endif
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.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
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.if Heap_Size
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.space Heap_Size
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.endif
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
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.section .vectors
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.align 2
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.globl __Vectors
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__Vectors:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long CY_NMI_HANLDER_ADDR /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External interrupts Description */
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.long NvicMux0_IRQHandler /* CPU User Interrupt #0 */
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.long NvicMux1_IRQHandler /* CPU User Interrupt #1 */
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.long NvicMux2_IRQHandler /* CPU User Interrupt #2 */
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.long NvicMux3_IRQHandler /* CPU User Interrupt #3 */
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.long NvicMux4_IRQHandler /* CPU User Interrupt #4 */
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.long NvicMux5_IRQHandler /* CPU User Interrupt #5 */
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.long NvicMux6_IRQHandler /* CPU User Interrupt #6 */
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.long NvicMux7_IRQHandler /* CPU User Interrupt #7 */
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.long Internal0_IRQHandler /* Internal SW Interrupt #0 */
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.long Internal1_IRQHandler /* Internal SW Interrupt #1 */
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.long Internal2_IRQHandler /* Internal SW Interrupt #2 */
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.long Internal3_IRQHandler /* Internal SW Interrupt #3 */
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.long Internal4_IRQHandler /* Internal SW Interrupt #4 */
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.long Internal5_IRQHandler /* Internal SW Interrupt #5 */
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.long Internal6_IRQHandler /* Internal SW Interrupt #6 */
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.long Internal7_IRQHandler /* Internal SW Interrupt #7 */
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.size __Vectors, . - __Vectors
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.equ __VectorsSize, . - __Vectors
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.section .ram_vectors
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.align 2
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.globl __ramVectors
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__ramVectors:
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.space __VectorsSize
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.size __ramVectors, . - __ramVectors
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.text
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.thumb
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.thumb_func
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.align 2
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/*
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* Device startup customization
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*
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* Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
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* because this function is executed as the first instruction in the ResetHandler.
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* The PDL is also not initialized to use the proper register offsets.
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* The user of this function is responsible for initializing the PDL and resources before using them.
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*/
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.weak Cy_OnResetUser
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.func Cy_OnResetUser, Cy_OnResetUser
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.type Cy_OnResetUser, %function
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Cy_OnResetUser:
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bx lr
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.size Cy_OnResetUser, . - Cy_OnResetUser
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.endfunc
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/* Reset handler */
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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bl Cy_OnResetUser
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cpsid i
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/* Firstly it copies data from read only memory to RAM. There are two schemes
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* to copy. One can copy more than one sections. Another can only copy
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* one section. The former scheme needs more instructions and read-only
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* data to implement than the latter.
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* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
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#ifdef __STARTUP_COPY_MULTIPLE
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/* Multiple sections scheme.
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*
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* Between symbol address __copy_table_start__ and __copy_table_end__,
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* there are array of triplets, each of which specify:
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* offset 0: LMA of start of a section to copy from
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* offset 4: VMA of start of a section to copy to
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* offset 8: size of the section to copy. Must be multiply of 4
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r4, =__copy_table_start__
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ldr r5, =__copy_table_end__
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.L_loop0:
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cmp r4, r5
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bge .L_loop0_done
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ldr r1, [r4]
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ldr r2, [r4, #4]
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ldr r3, [r4, #8]
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.L_loop0_0:
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subs r3, #4
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blt .L_loop0_0_done
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ldr r0, [r1, r3]
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str r0, [r2, r3]
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b .L_loop0_0
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.L_loop0_0_done:
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adds r4, #12
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b .L_loop0
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.L_loop0_done:
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#else
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/* Single section scheme.
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*
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* The ranges of copy from/to are specified by following symbols
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* __etext: LMA of start of the section to copy from. Usually end of text
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* __data_start__: VMA of start of the section to copy to
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* __data_end__: VMA of end of the section to copy to
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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subs r3, r2
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ble .L_loop1_done
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.L_loop1:
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subs r3, #4
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ldr r0, [r1,r3]
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str r0, [r2,r3]
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bgt .L_loop1
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.L_loop1_done:
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#endif /*__STARTUP_COPY_MULTIPLE */
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/* This part of work usually is done in C library startup code. Otherwise,
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* define this macro to enable it in this startup.
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*
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* There are two schemes too. One can clear multiple BSS sections. Another
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* can only clear one section. The former is more size expensive than the
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* latter.
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*
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* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
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* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
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*/
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#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
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/* Multiple sections scheme.
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*
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* Between symbol address __copy_table_start__ and __copy_table_end__,
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* there are array of tuples specifying:
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* offset 0: Start of a BSS section
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* offset 4: Size of this BSS section. Must be multiply of 4
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*/
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ldr r3, =__zero_table_start__
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ldr r4, =__zero_table_end__
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.L_loop2:
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cmp r3, r4
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bge .L_loop2_done
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ldr r1, [r3]
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ldr r2, [r3, #4]
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movs r0, 0
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.L_loop2_0:
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subs r2, #4
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blt .L_loop2_0_done
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str r0, [r1, r2]
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b .L_loop2_0
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.L_loop2_0_done:
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adds r3, #8
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b .L_loop2
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.L_loop2_done:
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#elif defined (__STARTUP_CLEAR_BSS)
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/* Single BSS section scheme.
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*
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* The BSS section is specified by following symbols
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* __bss_start__: start of the BSS section.
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* __bss_end__: end of the BSS section.
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*
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* Both addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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movs r0, 0
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subs r2, r1
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ble .L_loop3_done
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.L_loop3:
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subs r2, #4
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str r0, [r1, r2]
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bgt .L_loop3
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.L_loop3_done:
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#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
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#ifdef RAM_VECTORS
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/* Update Vector Table Offset Register. */
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ldr r0, =__ramVectors
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ldr r1, =CY_CPU_VTOR_ADDR
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str r0, [r1]
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dsb 0xF
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#endif
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#ifndef __NO_SYSTEM_INIT
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bl SystemInit
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#endif
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bl main
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/* Should never get here */
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b .
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.pool
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.size Reset_Handler, . - Reset_Handler
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.align 1
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.thumb_func
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.weak Default_Handler
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.type Default_Handler, %function
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Default_Handler:
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b .
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.size Default_Handler, . - Default_Handler
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.weak Cy_SysLib_FaultHandler
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.type Cy_SysLib_FaultHandler, %function
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Cy_SysLib_FaultHandler:
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b .
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.size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
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.type Fault_Handler, %function
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Fault_Handler:
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/* Storing LR content for Creator call stack trace */
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push {LR}
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movs r0, #4
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mov r1, LR
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tst r0, r1
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beq .L_MSP
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mrs r0, PSP
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b .L_API_call
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.L_MSP:
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mrs r0, MSP
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.L_API_call:
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/* Compensation of stack pointer address due to pushing 4 bytes of LR */
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adds r0, r0, #4
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bl Cy_SysLib_FaultHandler
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b .
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.size Fault_Handler, . - Fault_Handler
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.macro def_fault_Handler fault_handler_name
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.weak \fault_handler_name
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.set \fault_handler_name, Fault_Handler
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.endm
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.set \handler_name, Default_Handler
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.endm
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def_irq_handler NMI_Handler
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def_fault_Handler HardFault_Handler
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def_irq_handler SVC_Handler
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
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def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */
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def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */
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def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */
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def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */
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def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */
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def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */
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def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */
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def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */
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def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */
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def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */
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def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */
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def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */
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def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */
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def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */
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def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */
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def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */
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.end
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/* [] END OF FILE */
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@ -35,7 +35,6 @@ extern uint32_t *END_STACK;
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extern void main(void);
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#if !defined(PLATFORM_psoc6)
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void isr_reset(void) {
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register unsigned int *src, *dst;
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@ -77,8 +76,6 @@ void isr_empty(void)
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/* Ignore unmapped event and continue */
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}
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#endif
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/* This is the main loop for the bootloader.
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*
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@ -125,7 +122,6 @@ typedef void(*NMIHANDLER)(void);
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# define isr_NMI isr_empty
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#endif
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#ifndef PLATFORM_psoc6
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__attribute__ ((section(".isr_vector")))
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void (* const IV[])(void) =
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{
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@ -188,7 +184,6 @@ void (* const IV[])(void) =
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isr_empty,
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isr_empty,
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};
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#endif /* ! TARGET_psoc6 */
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#ifdef RAM_CODE
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