mirror of https://github.com/wolfSSL/wolfBoot.git
nRF5340 TrustZone port
Mattia Moffa
parent
530619e3ab
commit
5fb5b4b6ea
6
arch.mk
6
arch.mk
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@ -690,6 +690,12 @@ ifeq ($(TARGET),mcxw)
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$(MCUXPRESSO_DRIVERS)/drivers/fsl_romapi.o
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endif
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ifeq ($(TARGET),nrf5340)
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ifneq ($(TZEN), 1)
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LSCRIPT_IN=hal/$(TARGET)-ns.ld
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endif
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endif
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ifeq ($(TARGET),nrf5340_net)
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# Net core doesn't support DSP and FP
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CFLAGS+=-mcpu=cortex-m33+nodsp+nofp
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@ -0,0 +1,73 @@
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ARCH?=ARM
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TZEN?=1
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TARGET?=nrf5340
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SIGN?=ECC384
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HASH?=SHA384
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WOLFBOOT_VERSION?=1
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VTOR?=1
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CORTEX_M0?=0
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CORTEX_M33?=1
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NO_ASM?=0
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NO_MPU=1
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=0
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DELTA_UPDATES?=1
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SPMATH?=1
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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FLAGS_HOME=0
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DISABLE_BACKUP=0
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EXT_FLASH?=1
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SPI_FLASH?=0
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QSPI_FLASH?=1
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# Flash is 4KB pages (app)
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WOLFBOOT_SECTOR_SIZE?=0x1000
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# Flash keyvault: 112K
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WOLFBOOT_KEYVAULT_ADDRESS?=0x20000
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WOLFBOOT_KEYVAULT_SIZE?=0x1C000
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# Flash NSC: 16K
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WOLFBOOT_NSC_ADDRESS?=0x3C000
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WOLFBOOT_NSC_SIZE?=0x04000
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# Application offset (reserve 256K for wolfBoot + keyvault + NSC)
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x40000
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# Application Partition Size (768KB)
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WOLFBOOT_PARTITION_SIZE?=0xC0000
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# External Flash offset for application update (1MB)
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x0
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# External Flash offset for network update at 0x100000 (size=256KB)
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# External Flash offset for swap (4KB)
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x140000
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V?=0
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DEBUG?=0
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DEBUG_UART?=1
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USE_GCC=1
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OPTIMIZATION_LEVEL=2
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# Optionally wait for network core to boot before starting application core
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CFLAGS_EXTRA+=-DNRF_SYNC_CORES
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# Use larger block size for swapping sectors (performance improvement)
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CFLAGS_EXTRA+=-DFLASHBUFFER_SIZE=0x1000
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# Enable optional power control pin (active low) P1.00
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#CFLAGS_EXTRA+=-DQSPI_PWR_CTRL_PORT=1 -DQSPI_PWR_CTRL_PIN=0
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# Use UART0 on P0.22
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#CFLAGS_EXTRA+=-DUART_PORT=0 -DUART_PIN=22
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#CFLAGS_EXTRA+=-DDEBUG_FLASH
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#CFLAGS_EXTRA+=-DDEBUG_QSPI=1
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# Hard fault debugging
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#CFLAGS_EXTRA+=-DDEBUG_HARDFAULT
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@ -2425,7 +2425,7 @@ c
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NXP MCXW716 is a Cortex-M33 microcontroller running at 96MHz.
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The support has been tested using FRDM-MCXW716 with the onboard MCU-Link configured in JLink mode.
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This requires the MCXW SDK from the NXP MCUXpresso SDK Builder. We tested using [mcux-sdk](https://github.com/nxp-mcuxpresso/mcux-sdk) and [CMSIS_5](https://github.com/nxp-mcuxpresso/CMSIS_5)`
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This requires the MCXW SDK from the NXP MCUXpresso SDK Builder. We tested using [mcux-sdk](https://github.com/nxp-mcuxpresso/mcux-sdk) and [CMSIS_5](https://github.com/nxp-mcuxpresso/CMSIS_5)
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placed under "../NXP". Adjust the MCUXPRESSO and MCUXPRESSO_CMSIS variables in your .config file according to your paths.
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### MCX W: Configuring and compiling
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@ -2549,6 +2549,13 @@ Tested with the Nordic nRF5340-DK. This device has two cores:
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1) Application core: Cortex-M33 at 128MHz, w/TrustZone, 1MB flash, 512KB RAM
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2) Network core: Cortex-M33 at 64MHz, 256KB Flash and 64KB RAM
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Three different configurations are available at `config/examples`:
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- `nrf5340.config`: for the app core; does not make use of TrustZone, i.e. it
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always runs in secure mode.
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- `nrf5340-tz.config`: for the app core; makes use of TrustZone, i.e. boots the
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application as non-secure code.
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- `nrf5340_net.config`: for the net core.
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The DK board has two virtual COM ports. Application core and Network core will each output to different VCOM ports.
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The cores communicate firmware updates using shared memory hosted on application core.
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@ -0,0 +1,53 @@
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MEMORY
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{
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FLASH (rx) : ORIGIN = @ARCH_FLASH_OFFSET@, LENGTH = @BOOTLOADER_PARTITION_SIZE@
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FLASH_NET (rx) : ORIGIN = 0x01000000, LENGTH = 256K
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
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}
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SECTIONS
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{
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.text :
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{
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_start_text = .;
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KEEP(*(.isr_vector))
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*(.boot*)
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*(.text*)
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*(.rodata*)
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*(.init*)
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*(.fini*)
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. = ALIGN(4);
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_end_text = .;
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} > FLASH
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.edidx :
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{
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. = ALIGN(4);
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*(.ARM.exidx*)
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} > FLASH
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_stored_data = .;
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.data : AT (_stored_data)
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{
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_start_data = .;
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KEEP(*(.data*))
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. = ALIGN(4);
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_end_data = .;
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} > RAM
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.bss (NOLOAD) :
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{
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_start_bss = .;
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_end_bss = .;
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__bss_end__ = .;
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_end = .;
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} > RAM
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. = ALIGN(4);
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}
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END_STACK = ORIGIN(RAM) + LENGTH(RAM);
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@ -29,6 +29,8 @@
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#include "printf.h"
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#include "nrf5340.h"
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#include "spi_flash.h"
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#include "hal/armv8m_tz.h"
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#include "target.h"
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/* TODO:
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* Key Storage: See 7.1.18.4.2 Key storage:
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@ -133,6 +135,50 @@ static SharedMem_t* shm = (SharedMem_t*)&shm_shadow;
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#endif
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#endif
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#ifdef TZEN
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static void hal_spu_init(void) {
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uint8_t nsc_size_index;
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uint8_t region;
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uint8_t start_region;
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uint8_t end_region;
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/* Make sure SAU is disabled, configure everything through SPU */
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SAU_CTRL = SAU_INIT_CTRL_ALLNS;
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/* Flash: Non-Secure Callable */
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nsc_size_index = (WOLFBOOT_NSC_SIZE > 2048) ? 8 :
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(WOLFBOOT_NSC_SIZE > 1024) ? 7 :
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(WOLFBOOT_NSC_SIZE > 512) ? 6 :
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(WOLFBOOT_NSC_SIZE > 256) ? 5 :
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(WOLFBOOT_NSC_SIZE > 128) ? 4 :
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(WOLFBOOT_NSC_SIZE > 64) ? 3 :
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(WOLFBOOT_NSC_SIZE > 32) ? 2 :
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(WOLFBOOT_NSC_SIZE > 0) ? 1 : 0;
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SPU_FLASHNSC_REGION(0) = ((WOLFBOOT_NSC_ADDRESS / SPU_FLASH_BLOCK_SIZE) &
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SPU_FLASHNSC_REGION_MASK) | SPU_FLASHNSC_REGION_LOCK;
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SPU_FLASHNSC_SIZE(0) = nsc_size_index | SPU_FLASHNSC_SIZE_LOCK;
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/* Flash: non-secure application area */
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start_region = WOLFBOOT_PARTITION_BOOT_ADDRESS / SPU_FLASH_BLOCK_SIZE;
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end_region = (WOLFBOOT_PARTITION_BOOT_ADDRESS + WOLFBOOT_PARTITION_SIZE) / SPU_FLASH_BLOCK_SIZE;
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for (region = start_region; region < end_region; region++) {
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SPU_FLASHREGION_PERM(region) = (SPU_FLASHREGION_PERM(region) &
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~SPU_FLASHREGION_PERM_SECATTR) | SPU_FLASHREGION_PERM_LOCK;
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}
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/* RAM: non-secure application area */
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start_region = 0x20000 / SPU_RAM_BLOCK_SIZE;
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end_region = 0x24000 / SPU_RAM_BLOCK_SIZE;
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for (region = start_region; region < end_region; region++) {
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SPU_RAMREGION_PERM(region) = (SPU_RAMREGION_PERM(region) &
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~SPU_RAMREGION_PERM_SECATTR) | SPU_RAMREGION_PERM_LOCK;
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}
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}
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#endif
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void uart_init(void)
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{
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/* nRF5340-DK: (P0.20 or P1.01)
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@ -220,8 +266,9 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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((((uint32_t)data) + i) & 0x03) == 0)) {
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src = (uint32_t *)data;
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dst = (uint32_t *)address;
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/* set both secure and non-secure registers */
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#if TZ_SECURE() || defined(TARGET_nrf5340_net)
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NVMC_CONFIG = NVMC_CONFIG_WEN;
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#endif
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NVMC_CONFIGNS = NVMC_CONFIG_WEN;
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while (NVMC_READY == 0);
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dst[i >> 2] = src[i >> 2];
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@ -234,8 +281,9 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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dst = (uint32_t *)(address - off);
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val = dst[i >> 2];
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vbytes[off] = data[i];
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/* set both secure and non-secure registers */
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#if TZ_SECURE() || defined(TARGET_nrf5340_net)
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NVMC_CONFIG = NVMC_CONFIG_WEN;
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#endif
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NVMC_CONFIGNS = NVMC_CONFIG_WEN;
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while (NVMC_READY == 0);
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dst[i >> 2] = val;
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@ -257,7 +305,9 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
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address &= ~(FLASH_PAGE_SIZE-1);
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for (p = address; p <= end; p += FLASH_PAGE_SIZE) {
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/* set both secure and non-secure registers */
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#if TZ_SECURE() || defined(TARGET_nrf5340_net)
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NVMC_CONFIG = NVMC_CONFIG_EEN;
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#endif
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NVMC_CONFIGNS = NVMC_CONFIG_EEN;
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while (NVMC_READY == 0);
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*(volatile uint32_t *)p = 0xFFFFFFFF;
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@ -716,6 +766,10 @@ void hal_init(void)
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hal_net_check_version();
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#endif
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#ifdef TZEN
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hal_spu_init();
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#endif
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}
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#ifdef __WOLFBOOT
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@ -733,8 +787,8 @@ int hal_flash_protect(uint32_t start, uint32_t len)
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if (start + len > FLASH_SIZE)
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len = FLASH_SIZE - start;
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region = (start / SPU_BLOCK_SIZE);
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n = (len / SPU_BLOCK_SIZE);
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region = (start / SPU_FLASH_BLOCK_SIZE);
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n = (len / SPU_FLASH_BLOCK_SIZE);
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for (i = 0; i < n; i++) {
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/* do not allow write to this region and lock till next reset */
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@ -749,6 +803,25 @@ int hal_flash_protect(uint32_t start, uint32_t len)
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return 0;
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}
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#ifdef TZEN
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static void periph_unsecure() {
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/* Unsecure both GPIO ports */
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SPU_PERIPHID_PERM(GPIO_PERIPHID) &= ~SPU_PERIPHID_PERM_SECATTR;
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//SPU_GPIOPORT_PERM(0) = (1 << 29);
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SPU_GPIOPORT_PERM(0) = 0;
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SPU_GPIOPORT_PERM(1) = 0;
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/* Unsecure UARTE0 */
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SPU_PERIPHID_PERM(SERIAL0_PERIPHID) &= ~SPU_PERIPHID_PERM_SECATTR;
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/* Unsecure NVMC */
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SPU_PERIPHID_PERM(KMU_NVMC_PERIPHID) &= ~SPU_PERIPHID_PERM_SECATTR;
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/* Unsecure RTC0 */
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SPU_PERIPHID_PERM(RTC0_PERIPHID) &= ~SPU_PERIPHID_PERM_SECATTR;
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}
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#endif
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void hal_prepare_boot(void)
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{
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/* Write protect bootloader region of flash */
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@ -771,16 +844,28 @@ void hal_prepare_boot(void)
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#endif
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#if defined(TARGET_nrf5340_app) && defined(NRF_SYNC_CORES)
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/* if core synchronization enabled,
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* then wait for update_done or do_boot (5 seconds, 30 for update) */
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/* If core synchronization enabled,
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* then wait for update_done or do_boot (5 seconds, 30 for update).
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* Longer wait in DEBUG mode because the net core boots much
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* slower. */
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wolfBoot_printf("Waiting for network core...\n");
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#ifndef DEBUG
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(void)hal_shm_status_wait(&shm->core.net,
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(SHARED_STATUS_UPDATE_DONE | SHARED_STATUS_DO_BOOT),
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doUpdateNet ? 30*1000 : 5*1000);
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#else
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(void)hal_shm_status_wait(&shm->core.net,
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(SHARED_STATUS_UPDATE_DONE | SHARED_STATUS_DO_BOOT),
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doUpdateNet ? 45*1000 : 20*1000);
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#endif
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#endif
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}
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hal_shm_cleanup();
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#ifdef TZEN
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periph_unsecure();
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#endif
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}
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#endif /* __WOLFBOOT */
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@ -22,6 +22,12 @@
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#ifndef _HAL_NRF5340_H_
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#define _HAL_NRF5340_H_
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#if !defined(TARGET_nRF5340_net) && !(defined(TZEN) && defined(NONSECURE_APP))
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# define TZ_SECURE() (1)
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#else
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# define TZ_SECURE() (0)
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#endif
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/* Build-time gate for secure or non-secure peripherals.
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* At boot-time peripherals are secure */
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#ifdef TARGET_nrf5340_net
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@ -32,10 +38,6 @@
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/* Application core */
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#define TARGET_nrf5340_app
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#define CORE_STR "app"
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#ifndef TZEN
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/* at reset/power on wolfBoot is using secure bases */
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#define TZEN
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#endif
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#endif
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/* Clock */
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@ -77,7 +79,7 @@ void sleep_us(uint32_t usec);
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/* Domain Configuration */
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#ifdef TARGET_nrf5340_app
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#ifdef TZEN
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#if TZ_SECURE()
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#define DCNF_BASE (0x50000000)
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#else
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#define DCNF_BASE (0x40000000)
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@ -97,6 +99,7 @@ void sleep_us(uint32_t usec);
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#ifdef TARGET_nrf5340_app
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/* SPU */
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#define SPU_BASE 0x50003000UL
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#define SPU_EXTDOMAIN_PERM(n) *((volatile uint32_t *)(SPU_BASE + 0x440 + (((n) & 0x0) * 0x4)))
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#define SPU_EXTDOMAIN_PERM_SECATTR_NONSECURE 0
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#define SPU_EXTDOMAIN_PERM_SECATTR_SECURE (1 << 4)
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@ -104,13 +107,56 @@ void sleep_us(uint32_t usec);
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#define SPU_EXTDOMAIN_PERM_LOCK (1 << 8)
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#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_MASK (0x3)
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#define SPU_BLOCK_SIZE (16 * 1024)
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#define SPU_FLASHREGION_PERM(n) *((volatile uint32_t *)(SPU_BASE + 0x600 + (((n) & 0x3F) * 0x4)))
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#define SPU_GPIOPORT_PERM(n) (*(volatile uint32_t *)(SPU_BASE + 0x4C0 + ((n) & 0x1) * 0x8))
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#define SPU_GPIOPORT_LOCK(n) (*(volatile uint32_t *)(SPU_BASE + 0x4C4 + ((n) & 0x1) * 0x8))
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#define SPU_FLASH_BLOCK_SIZE (16 * 1024)
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#define SPU_RAM_BLOCK_SIZE (8 * 1024)
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#define SPU_FLASHNSC_REGION(n) (*(volatile uint32_t *)(SPU_BASE + 0x500 + ((n) & 0x1) * 0x8))
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#define SPU_FLASHNSC_REGION_MASK 0x0000003F
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#define SPU_FLASHNSC_REGION_LOCK (1 << 8)
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#define SPU_FLASHNSC_SIZE(n) (*(volatile uint32_t *)(SPU_BASE + 0x504 + ((n) & 0x1) * 0x8))
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#define SPU_FLASHNSC_SIZE_MASK 0x0000000F
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#define SPU_FLASHNSC_SIZE_LOCK (1 << 8)
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#define SPU_RAMNSC_REGION(n) (*(volatile uint32_t *)(SPU_BASE + 0x540 + ((n) & 0x1) * 0x8))
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#define SPU_RAMNSC_REGION_MASK 0x0000003F
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#define SPU_RAMNSC_REGION_LOCK (1 << 8)
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#define SPU_RAMNSC_SIZE(n) (*(volatile uint32_t *)(SPU_BASE + 0x544 + ((n) & 0x1) * 0x8))
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#define SPU_RAMNSC_SIZE_MASK 0x0000000F
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#define SPU_RAMNSC_SIZE_LOCK (1 << 8)
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|
||||
#define SPU_FLASHREGION_PERM(n) (*(volatile uint32_t *)(SPU_BASE + 0x600 + ((n) & 0x3F) * 0x4))
|
||||
#define SPU_FLASHREGION_PERM_EXEC (1 << 0) /* Allow instruction fetches from flash region */
|
||||
#define SPU_FLASHREGION_PERM_WRITE (1 << 1) /* Allow write operation to region */
|
||||
#define SPU_FLASHREGION_PERM_READ (1 << 2) /* Allow read operation from flash region */
|
||||
#define SPU_FLASHREGION_PERM_SECATTR (1 << 4) /* Flash region n security attribute is secure */
|
||||
#define SPU_FLASHREGION_PERM_LOCK (1 << 8) /* The content of this register can't be changed until the next reset */
|
||||
|
||||
#define SPU_RAMREGION_PERM(n) (*(volatile uint32_t *)(SPU_BASE + 0x700 + ((n) & 0x3F) * 0x4))
|
||||
#define SPU_RAMREGION_PERM_EXEC (1 << 0) /* Allow instruction fetches from flash region */
|
||||
#define SPU_RAMREGION_PERM_WRITE (1 << 1) /* Allow write operation to region */
|
||||
#define SPU_RAMREGION_PERM_READ (1 << 2) /* Allow read operation from flash region */
|
||||
#define SPU_RAMREGION_PERM_SECATTR (1 << 4) /* Flash region n security attribute is secure */
|
||||
#define SPU_RAMREGION_PERM_LOCK (1 << 8) /* The content of this register can't be changed until the next reset */
|
||||
|
||||
#define SPU_PERIPHID_PERM(n) (*(volatile uint32_t *)(SPU_BASE + 0x800 + ((n) & 0xFF) * 0x4))
|
||||
#define SPU_PERIPHID_PERM_SECUREMAPPING_MASK 0x00000003
|
||||
#define SPU_PERIPHID_PERM_SECUREMAPPING_NONSECURE (0 << 0)
|
||||
#define SPU_PERIPHID_PERM_SECUREMAPPING_SECURE (1 << 0)
|
||||
#define SPU_PERIPHID_PERM_SECUREMAPPING_USERSEL (2 << 0)
|
||||
#define SPU_PERIPHID_PERM_SECUREMAPPING_SPLIT (3 << 0)
|
||||
#define SPU_PERIPHID_PERM_DMA_MASK 0x0000000C
|
||||
#define SPU_PERIPHID_PERM_DMA_NODMA (0 << 2)
|
||||
#define SPU_PERIPHID_PERM_DMA_NOSEPATTR (1 << 2)
|
||||
#define SPU_PERIPHID_PERM_DMA_SEPATTR (2 << 2)
|
||||
#define SPU_PERIPHID_PERM_SECATTR (1 << 4)
|
||||
#define SPU_PERIPHID_PERM_DMASEC (1 << 5)
|
||||
#define SPU_PERIPHID_PERM_LOCK (1 << 8)
|
||||
#define SPU_PERIPHID_PERM_PRESENT (1 << 31)
|
||||
#endif
|
||||
|
||||
/* UICR */
|
||||
|
|
@ -130,14 +176,14 @@ void sleep_us(uint32_t usec);
|
|||
#else
|
||||
#define CTRLAP_BASE (0x41006000)
|
||||
#endif
|
||||
#define CTRLAP_APPROTECT_LOCK (*(volatile uint32_t *)(CTRLAP_BASE 0x540))
|
||||
#define CTRLAP_APPROTECT_DISABLE (*(volatile uint32_t *)(CTRLAP_BASE 0x544))
|
||||
#define CTRLAP_SECUREAPPROTECT_LOCK (*(volatile uint32_t *)(CTRLAP_BASE 0x548))
|
||||
#define CTRLAP_SECUREAPPROTECT_DISABLE (*(volatile uint32_t *)(CTRLAP_BASE 0x54C))
|
||||
#define CTRLAP_APPROTECT_LOCK (*(volatile uint32_t *)(CTRLAP_BASE + 0x540))
|
||||
#define CTRLAP_APPROTECT_DISABLE (*(volatile uint32_t *)(CTRLAP_BASE + 0x544))
|
||||
#define CTRLAP_SECUREAPPROTECT_LOCK (*(volatile uint32_t *)(CTRLAP_BASE + 0x548))
|
||||
#define CTRLAP_SECUREAPPROTECT_DISABLE (*(volatile uint32_t *)(CTRLAP_BASE + 0x54C))
|
||||
|
||||
/* Reset */
|
||||
#ifdef TARGET_nrf5340_app
|
||||
#ifdef TZEN
|
||||
#if TZ_SECURE()
|
||||
#define RESET_BASE (0x50005000)
|
||||
#else
|
||||
#define RESET_BASE (0x40005000)
|
||||
|
|
@ -158,8 +204,10 @@ void sleep_us(uint32_t usec);
|
|||
|
||||
|
||||
/* Non-volatile memory controller */
|
||||
#define KMU_NVMC_PERIPHID 57
|
||||
|
||||
#ifdef TARGET_nrf5340_app
|
||||
#ifdef TZEN
|
||||
#if TZ_SECURE()
|
||||
#define NVMC_BASE (0x50039000)
|
||||
#else
|
||||
#define NVMC_BASE (0x40039000)
|
||||
|
|
@ -183,7 +231,7 @@ void sleep_us(uint32_t usec);
|
|||
|
||||
/* Clock control */
|
||||
#ifdef TARGET_nrf5340_app
|
||||
#ifdef TZEN
|
||||
#if TZ_SECURE()
|
||||
#define CLOCK_BASE (0x50005000)
|
||||
#else
|
||||
#define CLOCK_BASE (0x40005000)
|
||||
|
|
@ -223,8 +271,10 @@ void sleep_us(uint32_t usec);
|
|||
|
||||
|
||||
/* GPIO Port (0-1) */
|
||||
#define GPIO_PERIPHID 66
|
||||
|
||||
#ifdef TARGET_nrf5340_app
|
||||
#ifdef TZEN
|
||||
#if TZ_SECURE()
|
||||
#define GPIO_BASE(n) (0x50842500 + (((n) & 0x1) * 0x300))
|
||||
#else
|
||||
#define GPIO_BASE(n) (0x40842500 + (((n) & 0x1) * 0x300))
|
||||
|
|
@ -251,8 +301,13 @@ void sleep_us(uint32_t usec);
|
|||
#define GPIO_CNF_MCUSEL(n) (((n) & 0x7) << 28)
|
||||
|
||||
/* UART (0-1) */
|
||||
#define SERIAL0_PERIPHID 8
|
||||
#define SERIAL1_PERIPHID 9
|
||||
#define SERIAL2_PERIPHID 11
|
||||
#define SERIAL3_PERIPHID 12
|
||||
|
||||
#ifdef TARGET_nrf5340_app
|
||||
#ifdef TZEN
|
||||
#if TZ_SECURE()
|
||||
#define UART_BASE(n) (0x50008000 + (((n) & 0x1) * 0x1000))
|
||||
#else
|
||||
#define UART_BASE(n) (0x40008000 + (((n) & 0x1) * 0x1000))
|
||||
|
|
@ -279,7 +334,7 @@ void uart_write_sz(const char* c, unsigned int sz);
|
|||
|
||||
/* SPI (0-2) */
|
||||
#ifdef TARGET_nrf5340_app
|
||||
#ifdef TZEN
|
||||
#if TZ_SECURE()
|
||||
#define SPI_BASE(n) (0x50008000 + (((n) & 0x3) * 0x1000))
|
||||
#else
|
||||
#define SPI_BASE(n) (0x40008000 + (((n) & 0x3) * 0x1000))
|
||||
|
|
@ -316,7 +371,7 @@ void uart_write_sz(const char* c, unsigned int sz);
|
|||
|
||||
/* QSPI */
|
||||
#ifdef TARGET_nrf5340_app
|
||||
#ifdef TZEN
|
||||
#if TZ_SECURE()
|
||||
#define QSPI_BASE (0x5002B000)
|
||||
#else
|
||||
#define QSPI_BASE (0x4002B000)
|
||||
|
|
@ -398,7 +453,7 @@ void uart_write_sz(const char* c, unsigned int sz);
|
|||
|
||||
/* interprocessor communication (IPC) peripheral */
|
||||
#ifdef TARGET_nrf5340_app
|
||||
#ifdef TZEN
|
||||
#if TZ_SECURE()
|
||||
#define IPC_BASE (0x5002A000)
|
||||
#else
|
||||
#define IPC_BASE (0x4002A000)
|
||||
|
|
@ -415,8 +470,11 @@ void uart_write_sz(const char* c, unsigned int sz);
|
|||
#define IPC_GPMEM(n) *((volatile uint32_t *)(IPC_BASE + 0x610 + (((n) & 0x1) * 0x4)))
|
||||
|
||||
/* RTC - uses LFCLK - 24-bit counter/compare */
|
||||
#define RTC0_PERIPHID 20
|
||||
#define RTC1_PERIPHID 21
|
||||
|
||||
#ifdef TARGET_nrf5340_app
|
||||
#ifdef TZEN
|
||||
#if TZ_SECURE()
|
||||
#define RTC_BASE(n) ((0x50014000) + (((n) & 0x1) * 0x1000))
|
||||
#else
|
||||
#define RTC_BASE(n) ((0x40014000) + (((n) & 0x1) * 0x1000))
|
||||
|
|
|
|||
|
|
@ -1,8 +1,12 @@
|
|||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = @ARCH_FLASH_OFFSET@, LENGTH = @BOOTLOADER_PARTITION_SIZE@
|
||||
FLASH_NET (rx) : ORIGIN = 0x01000000, LENGTH = 256K
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
FLASH (rx) : ORIGIN = @ARCH_FLASH_OFFSET@, LENGTH = @WOLFBOOT_KEYVAULT_ADDRESS@ - @ARCH_FLASH_OFFSET@
|
||||
FLASH_NET (rx) : ORIGIN = 0x01000000, LENGTH = 0x40000 /* 256K */
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000 /* 64K */
|
||||
RAM_HEAP (rw) : ORIGIN = 0x20010000, LENGTH = 0xc000 /* 48K */
|
||||
RAM_KV (rw) : ORIGIN = 0x2001c000, LENGTH = 0x2000 /* 8K */
|
||||
FLASH_KEYVAULT (rw) : ORIGIN = @WOLFBOOT_KEYVAULT_ADDRESS@, LENGTH = @WOLFBOOT_KEYVAULT_SIZE@
|
||||
FLASH_NSC(rx) : ORIGIN = @WOLFBOOT_NSC_ADDRESS@, LENGTH = @WOLFBOOT_NSC_SIZE@
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
|
|
@ -26,6 +30,14 @@ SECTIONS
|
|||
*(.ARM.exidx*)
|
||||
} > FLASH
|
||||
|
||||
.gnu.sgstubs :
|
||||
{
|
||||
. += 0x400;
|
||||
. = ALIGN(4);
|
||||
*(.gnu.sgstubs*) /* Secure Gateway Stubs */
|
||||
. = ALIGN(4);
|
||||
} > FLASH_NSC
|
||||
|
||||
_stored_data = .;
|
||||
|
||||
.data : AT (_stored_data)
|
||||
|
|
@ -51,3 +63,12 @@ SECTIONS
|
|||
}
|
||||
|
||||
END_STACK = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
||||
_keyvault_origin = ORIGIN(RAM_KV);
|
||||
_keyvault_size = LENGTH(RAM_KV);
|
||||
|
||||
_flash_keyvault = ORIGIN(FLASH_KEYVAULT);
|
||||
_flash_keyvault_size = LENGTH(FLASH_KEYVAULT);
|
||||
|
||||
_start_heap = ORIGIN(RAM_HEAP);
|
||||
_heap_size = LENGTH(RAM_HEAP);
|
||||
|
|
|
|||
|
|
@ -596,7 +596,7 @@ endif
|
|||
# allow elf inclusion of debug symbols even with optimizations enabled
|
||||
# make DEBUG_SYMBOLS=1
|
||||
ifeq ($(DEBUG_SYMBOLS),1)
|
||||
CFLAGS+=-g
|
||||
CFLAGS+=-g -DDEBUG_SYMBOLS
|
||||
ifeq ($(USE_GCC),1)
|
||||
CFLAGS+=-ggdb3
|
||||
else ifneq ($(ARCH),AURIX_TC3)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,57 @@
|
|||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = @WOLFBOOT_TEST_APP_ADDRESS@, LENGTH = @WOLFBOOT_TEST_APP_SIZE@
|
||||
RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 16K /* Run in lowmem */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
_start_text = .;
|
||||
KEEP(*(.isr_vector))
|
||||
*(.init)
|
||||
*(.fini)
|
||||
*(.text*)
|
||||
KEEP(*(.rodata*))
|
||||
. = ALIGN(4);
|
||||
_end_text = .;
|
||||
} > FLASH
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > FLASH
|
||||
|
||||
_stored_data = .;
|
||||
|
||||
.data : AT (_stored_data)
|
||||
{
|
||||
_start_data = .;
|
||||
KEEP(*(.data*))
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.ramcode))
|
||||
. = ALIGN(4);
|
||||
_end_data = .;
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
_start_bss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_end_bss = .;
|
||||
_end = .;
|
||||
} > RAM
|
||||
}
|
||||
|
||||
_wolfboot_partition_boot_address = @WOLFBOOT_PARTITION_BOOT_ADDRESS@;
|
||||
_wolfboot_partition_size = @WOLFBOOT_PARTITION_SIZE@;
|
||||
_wolfboot_partition_update_address = @WOLFBOOT_PARTITION_UPDATE_ADDRESS@;
|
||||
_wolfboot_partition_swap_address = @WOLFBOOT_PARTITION_SWAP_ADDRESS@;
|
||||
|
||||
PROVIDE(_start_heap = _end);
|
||||
PROVIDE(_end_stack = ORIGIN(RAM) + LENGTH(RAM));
|
||||
|
|
@ -234,6 +234,14 @@ ifeq ($(TARGET),stm32u5)
|
|||
LDFLAGS+=-mcpu=cortex-m33
|
||||
endif
|
||||
|
||||
ifeq ($(TARGET),nrf5340)
|
||||
ifeq ($(TZEN),1)
|
||||
LSCRIPT_TEMPLATE=ARM-nrf5340-ns.ld
|
||||
else
|
||||
LSCRIPT_TEMPLATE=ARM.ld
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(TARGET),nrf5340_net)
|
||||
CFLAGS+=-mcpu=cortex-m33+nodsp+nofp
|
||||
LDFLAGS+=-mcpu=cortex-m33+nodsp+nofp
|
||||
|
|
|
|||
|
|
@ -56,10 +56,15 @@ void main(void)
|
|||
|
||||
wolfBoot_printf("========================\n");
|
||||
wolfBoot_printf("nRF5340 wolfBoot (app core)\n");
|
||||
wolfBoot_printf("Copyright 2024 wolfSSL Inc\n");
|
||||
wolfBoot_printf("Copyright 2025 wolfSSL Inc\n");
|
||||
wolfBoot_printf("GPL v3\n");
|
||||
wolfBoot_printf("Version : 0x%lx\n", app_version);
|
||||
wolfBoot_printf("Compiled: " __DATE__ ":" __TIME__ "\n");
|
||||
#ifdef TZEN
|
||||
wolfBoot_printf("TrustZone enabled: yes\n");
|
||||
#else
|
||||
wolfBoot_printf("TrustZone enabled: no\n");
|
||||
#endif
|
||||
wolfBoot_printf("========================\n");
|
||||
|
||||
/* mark boot successful */
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ void main(void)
|
|||
|
||||
wolfBoot_printf("========================\n");
|
||||
wolfBoot_printf("nRF5340 wolfBoot (net core)\n");
|
||||
wolfBoot_printf("Copyright 2024 wolfSSL Inc\n");
|
||||
wolfBoot_printf("Copyright 2025 wolfSSL Inc\n");
|
||||
wolfBoot_printf("GPL v3\n");
|
||||
wolfBoot_printf("Version : 0x%lx\n", app_version);
|
||||
wolfBoot_printf("Compiled: " __DATE__ ":" __TIME__ "\n");
|
||||
|
|
|
|||
|
|
@ -57,6 +57,7 @@ while test $# -gt 0; do
|
|||
echo "-h, --help show brief help"
|
||||
echo "-c, --clean cleanup build artifacts"
|
||||
echo "-b, --build build release with symbols"
|
||||
echo "-tz, --trustzone" use TrustZone configuration
|
||||
echo "-d, --debug build debug"
|
||||
echo "-v, --verbose build verbose"
|
||||
echo "--version use custom version"
|
||||
|
|
@ -80,6 +81,11 @@ while test $# -gt 0; do
|
|||
echo "Build release with symbols"
|
||||
shift
|
||||
;;
|
||||
-tz|--trustzone)
|
||||
DO_TRUSTZONE=1
|
||||
echo "Build with TrustZone config"
|
||||
shift
|
||||
;;
|
||||
-d|--debug)
|
||||
DO_BUILD=1
|
||||
MAKE_ARGS+=" DEBUG=1"
|
||||
|
|
@ -167,6 +173,12 @@ fi
|
|||
|
||||
if [[ $DO_BUILD == 1 ]]; then
|
||||
# Build internal flash images for both cores
|
||||
|
||||
if [[ $DO_TRUSTZONE == 1 ]]; then
|
||||
config_app=config/examples/nrf5340-tz.config
|
||||
else
|
||||
config_app=config/examples/nrf5340.config
|
||||
fi
|
||||
|
||||
# Build net
|
||||
cp config/examples/nrf5340_net.config .config
|
||||
|
|
@ -181,7 +193,7 @@ if [[ $DO_BUILD == 1 ]]; then
|
|||
fi
|
||||
|
||||
# Build app
|
||||
cp config/examples/nrf5340.config .config
|
||||
cp "$config_app" .config
|
||||
make clean
|
||||
make $MAKE_ARGS
|
||||
cp test-app/image.bin tools/scripts/nrf5340/image_app.bin
|
||||
|
|
|
|||
Loading…
Reference in New Issue